Parallel-to-serial conversion circuit, parallel-to-serial conversion circuit layout and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a parallel-serial conversion circuit, a parallel-serial conversion circuit layout and a memory, which comprises a plurality of parallel branches, each of the parallel branches comprising a first input end, a second input end, a control end and an output end; the first input end is configured to receive a high-level signal, the second input end is configured to receive a low-level signal, the control end is connected to a selection unit, and the output end is connected to a serial wire; the selection unit is configured to receive a selection signal and at least two branch signals, and based on the selection signal, one branch signal is selected to be transmitted to the parallel branch; the serial wire is configured to organize the signals output by the plurality of parallel branches into a serial signal; a plurality of driving units are connected to the serial wire in parallel, and are configured to enhance the driving capability of the serial wire; the output ends of the driving units are connected to each other, and are configured to output the serial signal; each driving unit is arranged adjacent to one parallel branch, thereby greatly reducing the load of the internal nodes of the conversion circuit and effectively improving the performance of the internal nodes of the conversion circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a parallel-to-serial conversion circuit, a parallel-to-serial conversion circuit layout, and a memory. Background Technology

[0002] For parallel-to-serial conversion circuits in memory, the delays of each parallel input and serial output need to be consistent. Therefore, additional wiring is required in the circuit design to ensure that the connection distances from each parallel input to the serial output are consistent.

[0003] Similarly, for serial-to-parallel conversion circuits in memory, the delay of the serial input and each parallel output must be kept consistent. Therefore, additional wiring is required in the circuit design to ensure that the connection distance from the serial input to each parallel output is consistent.

[0004] The extra winding of the conversion circuit increases the load on the conversion circuit, thereby reducing the performance of the conversion circuit. The signal swing of the transmitted signal in the overloaded line is small and the waveform duty cycle deviation is large, which can easily cause write / read errors in the memory. Summary of the Invention

[0005] This disclosure provides a parallel-to-serial conversion circuit, a parallel-to-serial conversion circuit layout, and a memory, which greatly reduces the load on the internal nodes of the conversion circuit, effectively improves the performance of the internal nodes of the conversion circuit, and enables the signal in the conversion circuit to have a larger swing and a smaller duty cycle loss.

[0006] This disclosure provides a parallel-to-serial conversion circuit, including: multiple parallel branches, each parallel branch including: a first input terminal, a second input terminal, a control terminal, and an output terminal; wherein, the first input terminal is used to receive a high-level signal, the second input terminal is used to receive a low-level signal, the control terminal is connected to a selection unit, and the output terminal is connected to a serial wire; the selection unit is used to receive a selection signal and at least two branch signals, and is configured to select one branch signal based on the selection signal and transmit it to the parallel branch; the serial wire is used to organize the signals output from the multiple parallel branches into a serial signal; multiple driving units are connected in parallel to the serial wire to enhance the driving capability of the serial wire, and the output terminals of the multiple driving units are interconnected to output a serial signal; wherein, each driving unit is arranged adjacent to a parallel branch.

[0007] Each parallel branch receives multiple parallel signals through a selection unit. The received multiple parallel signals are then selected by a selection signal, enabling the transmission of multiple parallel signals through a single parallel branch. This reduces the number of parallel branches required and further reduces the length of the serial wires, thus lowering the load on the serial wires. In addition, by reducing the number of parallel branches, the layout area occupied by some of the parallel branches is saved, thereby reducing the layout area of ​​the parallel-to-serial conversion circuit and achieving a greater degree of integration. Furthermore, by reducing the number of parallel branches, the number of layout layers required for setting up parallel branches is reduced, thereby reducing the layout layer height of the parallel-to-serial conversion circuit.

[0008] In addition, the number of driving units is equal to the number of parallel branches to further ensure that the connection distance from each parallel input to the serial output is consistent.

[0009] In addition, the selection unit includes a multiplexer and a selection subunit; the multiplexer is used to receive at least two branch signals and is connected to the selection subunit; the selection subunit is used to receive a selection command and generate a selection signal based on the selection command; the multiplexer is configured to select one branch signal based on the selection signal and transmit it to the parallel branch through the control terminal.

[0010] In addition, the multiplexer only receives two branch signals, and the selection command is the internal clock signal.

[0011] In addition, the period of the selection signal is n times the period of the internal clock signal, and n is the number of branches of the multiple parallel branches.

[0012] In addition, at most one of the selection signal and branch signal received by the same selection unit is a continuous signal. In order to prevent the signal of other parallel branches from affecting the signal, at most one of the selection signal and branch signal connected to the same selection unit is a continuous signal. This ensures that when other parallel branches are working, the switching PMOS transistors or switching NMOS transistors in other parallel branches are not turned on, and other parallel branches will not affect the signal in the serial wire.

[0013] In addition, the high-level data is alternately distributed in the selection signals received by the selection units connected to multiple parallel branches.

[0014] In addition, the high-level data in the selection signals received by the selection units connected to multiple parallel branches have overlapping portions.

[0015] Additionally, the parallel branch includes: a switching PMOS transistor and a switching NMOS transistor; the gates of the switching PMOS transistor and the switching NMOS transistor serve as control terminals for the parallel branch, used to connect to the selection unit; the source and drain of the switching PMOS transistor are connected to a serial wire; the drain of the switching PMOS transistor serves as the first input terminal of the parallel branch, used to receive a high-level signal; the source of the switching NMOS transistor serves as the second input terminal of the parallel branch, used to receive a low-level signal. Both the gates of the switching PMOS transistor and the switching NMOS transistor serve as control terminals, ensuring that only one of them can be turned on based on the parallel signal output from the selection unit. When the switching PMOS transistor is turned on, the serial wire connects to the high-level signal V. DD Connected to output a high-level signal, when the switch NMSO is turned on, the serial wire is connected to the low-level signal GND to output a low-level signal.

[0016] In addition, the driving unit includes two inverters, wherein the input of one inverter is connected to a serial wire, the output of the other inverter is connected to the input of the other inverter, and the output of the other inverter is used to output a serial signal.

[0017] Additionally, the inverter includes a driving PMOS transistor and a driving NMOS transistor. The gates of the driving PMOS transistor and the driving NMOS transistor are connected, and the source and drain of the driving PMOS transistor are connected. The drain of the driving PMOS transistor receives a high-level signal, and the source of the driving NMOS transistor receives a low-level signal. The gates of the driving PMOS transistor and the driving NMOS transistor are connected as the input terminals of the inverter. When the input is high, the driving NMOS transistor is turned on, and the output terminal of the inverter is connected to a low-level signal to output low-level data. When the input is low, the driving PMOS transistor is turned on, and the output terminal of the inverter is connected to a high-level signal to output high-level data, thereby achieving data inversion. Furthermore, the output high-level data is a high-level signal, and the output low-level data is a low-level signal, thereby increasing the signal swing and reducing the signal duty cycle loss.

[0018] This disclosure provides a parallel-to-serial conversion circuit layout for forming the aforementioned parallel-to-serial conversion circuit, including: a parallel branch layout for forming parallel branches, and a selection unit connected to the parallel branches; a driver unit layout for forming driver units; wherein, adjacent parallel branch layouts and driver unit layouts are disposed in the same layout layer, the projections of multiple parallel branch layouts in a direction perpendicular to the layout layer overlap, the projections of multiple driver unit layouts in a direction perpendicular to the layout layer overlap; and the projections of serial wires connecting the parallel branch layouts and driver unit layouts in a direction perpendicular to the layout layer overlap.

[0019] By reducing the number of parallel branches, the layout area occupied by some parallel branch layouts is saved, thereby reducing the layout area of ​​the parallel-to-serial conversion circuit and achieving a greater degree of integration. In addition, by reducing the number of parallel branch layouts, the number of layout layers for setting up parallel branch layouts is reduced, thereby reducing the layout layer height of the parallel-to-serial conversion circuit layout. By setting the parallel branch layout and the driver unit layout in the same position on different layout layers, the delay between parallel input and serial output is kept consistent.

[0020] In addition, the number of drive unit layouts is equal to the number of parallel branch layouts.

[0021] This disclosure provides a memory in which the above-described parallel-to-serial conversion circuit is applied.

[0022] This disclosure provides a memory whose layout architecture adopts the above-described parallel-to-serial conversion circuit layout. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a parallel-to-serial conversion circuit provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of each parallel branch provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the structure of a selection unit provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the structure of a driving unit provided in an embodiment of the present disclosure; Figure 5 Based on an embodiment of this disclosure Figures 1-4 A schematic diagram of the parallel-to-serial conversion circuit of the structural components shown; Figure 6 Provided for an embodiment of this disclosure Figure 5 The circuit shown is a schematic diagram of the waveform of the selected signal. Figure 7 Provided for an embodiment of this disclosure Figure 6 The circuit shown contains the specific waveform of the selected signal. Figure 8 A schematic diagram of the layout of a parallel-to-serial conversion circuit with two parallel branches, provided for another embodiment of this disclosure; Figure 9 A schematic diagram of the layout of a parallel-to-serial conversion circuit with four parallel branches, provided for another embodiment of this disclosure. Detailed Implementation

[0024] The extra winding of the conversion circuit increases the load on the conversion circuit, thereby reducing the performance of the conversion circuit. The signal swing of the transmitted signal in the overloaded line is small and the waveform duty cycle deviation is large, which can easily cause write / read errors in the memory.

[0025] This disclosure provides a parallel-to-serial conversion circuit that greatly reduces the load on the internal nodes of the conversion circuit, effectively improves the performance of the internal nodes of the conversion circuit, and enables the signal in the conversion circuit to have a larger swing and a smaller duty cycle loss.

[0026] It will be understood by those skilled in the art that many technical details have been presented in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 This is a schematic diagram of the parallel-to-serial conversion circuit provided in this embodiment. Figure 2 This is a schematic diagram of the structure of each parallel branch provided in this embodiment. Figure 3 This is a schematic diagram of the selection unit provided in this embodiment. Figure 4 This is a schematic diagram of the drive unit provided in this embodiment. Figure 5 The embodiment provided is based on Figures 1-4 The schematic diagram of the parallel-to-serial conversion circuit of the structural components shown is as follows. Figure 6 Provided for this embodiment Figure 5 The circuit shown is a waveform diagram of the selected signal. Figure 7 Provided for this embodiment Figure 6 The circuit shown illustrates the specific waveform of the selected signal. The following is a detailed description of the parallel-to-serial conversion circuit provided in this embodiment, in conjunction with the accompanying drawings: refer to Figure 1 The parallel-to-serial conversion circuit includes: multiple parallel branches 101, serial wires 102, and multiple driving units 103.

[0028] For details, please refer to the following: Figure 2 Each parallel branch 101 includes: a first input terminal K1, a second input terminal K2, a control terminal C, and an output terminal D; wherein, the first input terminal K1 is used to receive a high-level signal V. DD The second input terminal K2 is used to receive the low-level signal GND, the control terminal C is connected to the selection unit 104, and the output terminal D is connected to the serial wire 102.

[0029] Selection unit 104 is used to receive selection signal and at least two branch signals. Selection unit 104 is configured to select one branch signal based on the selection signal and transmit it to parallel branch 101.

[0030] The serial wire 102 is used to organize the signals output from multiple parallel branches 101 into a serial signal.

[0031] Multiple drive units 103 are connected in parallel and then connected to a serial wire 102 to enhance the driving capability of the serial wire 102. The output terminals of the drive units 103 are interconnected to output serial signals.

[0032] Each drive unit 103 is arranged adjacent to a parallel branch 101.

[0033] Each parallel branch 101 receives multiple parallel signals through a selection unit 104. The received multiple parallel signals are selected by a selection signal, realizing the transmission of multiple parallel signals through a single parallel branch 101. This reduces the number of parallel branches 101 required and further reduces the length of the serial wires 102 required, thereby reducing the load on the serial wires 102. In addition, by reducing the number of parallel branches 101, the layout area occupied by some parallel branches is saved, thereby reducing the layout area of ​​the parallel-to-serial conversion circuit and achieving a greater degree of integration. Furthermore, by reducing the number of parallel branches 101, the number of layout layers for setting up parallel branches 101 is reduced, thereby reducing the layout layer height of the parallel-to-serial conversion circuit.

[0034] Continue to refer to Figure 2 Parallel branch 101 includes a switching PMOS transistor and a switching NMOS transistor; wherein, the gate of the switching PMOS transistor and the gate of the switching NMOS transistor serve as the control terminal C of parallel branch 101, used to connect to selection unit 104; the source of the switching PMOS transistor and the drain of the switching NMOS transistor are connected to serial wire 102; and the drain of the switching PMOS transistor serves as the first input terminal K1 of parallel branch 101, used to receive high-level signal V. DD The drain of the switching NMOS transistor serves as the second input terminal K2 of the parallel branch 101, used to receive the low-level signal GND.

[0035] Both the gate of the PMOS and the gate of the NMOS transistor serve as control terminals C, ensuring that only one of them can be turned on based on the parallel signal output from selection unit 104. When the PMOS transistor is turned on, the serial wire 102 connects to the high-level signal V. DD Connected to output a high-level signal, when the switch NMSO is turned on, the serial wire 102 is connected to the low-level signal GND to output a low-level signal.

[0036] It should be noted that in this embodiment, ground is used as the low-level signal GND for reception, and the internal power supply voltage is used as the high-level signal V. DDThis does not constitute a limitation on this embodiment; in other embodiments, any power signal that can be recognized as high level by the memory can be selected to provide a high-level signal, and similarly, any power signal that can be recognized as low level by the memory can be selected to provide a low-level signal.

[0037] Furthermore, the specific connection method of the "source" and "drain" for switching PMOS transistors and switching NMOS transistors does not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be used.

[0038] Furthermore, the aforementioned limitation of using the drain of the PMOS transistor as the first input terminal K1 and the drain of the NMOS transistor as the second input terminal K2 does not constitute a limitation on this embodiment. In other embodiments, the drain of the PMOS transistor can be used as the second input terminal K2 and the drain of the NMOS transistor as the first input terminal K1. In this case, when the PMOS transistor is turned on, the serial wire 102 is connected to the low-level signal GND to output a low-level signal; when the NMOS transistor is turned on, the serial wire 102 is connected to the high-level signal VND. DD Connect to output a high-level signal.

[0039] In some embodiments, reference Figure 3 The selection unit 104 includes a multiplexer 301 and a selection subunit 302.

[0040] The multiplexer 301 is used to receive at least two branch signals and is connected to the selection subunit 302.

[0041] The selection subunit 302 is used to receive selection commands and generate selection signals based on the selection commands. The multiplexer 301 is configured to select one branch signal based on the selection signal and transmit it to the parallel branch 101 through the control terminal C.

[0042] In some embodiments, reference Figure 4 The driving unit 103 includes two inverters, wherein the input terminal of one inverter is connected to the serial wire 102, the output terminal is connected to the input terminal of the other inverter, and the output terminal of the other inverter is used to output a serial signal.

[0043] Continue to refer to Figure 4 The inverter includes a driving PMOS transistor and a driving NMOS transistor. The gates of the driving PMOS transistor and the driving NMOS transistor are connected. The source of the driving PMOS transistor and the drain of the driving NMOS transistor are connected. The drain of the driving PMOS transistor is used to receive a high-level signal V. DD The source of the NMOS transistor is used to receive the low-level signal GND.

[0044] The gates of the driving PMOS transistor and the driving NMOS transistor are connected together as the input terminals of the inverter. When the input is high, the driving NMOS transistor is turned on, and the output terminal of the inverter is connected to the low-level signal GND to output low-level data. When the input is low, the driving PMOS transistor is turned on, and the output terminal of the inverter is connected to the high-level signal VND. DD Connected to output high-level data, thus achieving data inversion; additionally, the output high-level data is a high-level signal V. DD The low-level data output is a low-level signal GND, which increases the signal swing and reduces the signal duty cycle loss.

[0045] In one example, if the selection unit 104 receives two branch signals, that is, the multiplexer 301 only receives two branch signals and combines them... Figures 1-4 Circuit, forming Figure 5 The circuit shown.

[0046] In this example, the selection command can use the internal clock signal CK; in other examples, the selection command can use an external signal as an instruction for control.

[0047] Figure 5 The example uses a parallel-to-serial converter circuit with two parallel branches for specific illustration, and does not constitute a limitation on the number of parallel branches in a parallel-to-serial converter circuit, as follows: Specifically, the period of the selection signal corresponding to each selection unit 104 generated according to the selection command is n times the period of the internal clock signal, where n is the number of branches of the parallel branch 101 in the parallel-to-serial conversion circuit. Therefore, in this example, the period of the selection signal is twice the period of the internal clock signal. In other embodiments, if the number of branches of the parallel branch in the parallel-to-serial conversion circuit is n, then the period of the selection signal corresponding to each selection unit generated according to the selection command is n times the period of the internal clock signal.

[0048] For details, please refer to the following: Figure 6 The period of the first selection signal CK1 used for the control of the first parallel branch and the period of the second selection signal CK2 used for the control of the second parallel branch are twice the period of the internal clock signal CK.

[0049] It should be noted that the diagonal lines shown in the diagram for the first selection signal CK1 and the second selection signal CK2 can be either high or low level, thus forming a pattern as follows: Figure 7 The four sets of first selection signals CK1 and second selection signals CK2 are shown.

[0050] refer to Figure 7 As can be seen from the third group of level distributions, in the selection signals received by the selection unit 104 connected to the multiple parallel branches 101, high-level data are alternately distributed; Reference Figure 7 As can be seen from the level distribution of the first, second and fourth groups, the high-level data in the selection signals received by the selection unit 104 connected to the multiple parallel branches 101 have overlapping parts.

[0051] refer to Figure 6 The first selection signal CK1 is used to control the output of the first branch signal IN1 and the third branch signal IN3, and the second selection signal CK2 is used to control the output of the second branch signal IN2 and the fourth branch signal IN4.

[0052] Specifically, when CK1 is high, one of the first branch signal IN1 and the third branch signal IN3 controls the parallel branch 101 to switch the high-level signal V through the selection unit 104. DD Alternatively, a low-level signal GND is input to the serial wire 102; when CK1 is low, the other of the first branch signal IN1 and the third branch signal IN3 controls the parallel branch 101 to switch to a high-level signal V through the selection unit 104. DD Alternatively, a low-level signal GND is input to the serial wire 102; when CK2 is high, one of the second branch signal IN2 and the fourth branch signal IN4 controls the parallel branch 101 to switch the high-level signal V through the selection unit 104. DD Alternatively, a low-level signal GND is input to the serial wire 102; when CK2 is low, the other of the second branch signal IN2 and the fourth branch signal IN4 controls the parallel branch 101 to switch to a high-level signal V through the selection unit 104. DD Or, input the low-level signal GND to the serial wire 102.

[0053] It should be noted that, in order to prevent the signals of other parallel branches from affecting the signal, at most one of the selection signal and branch signal connected to the same selection unit is a continuous signal, so that when other parallel branches are working, the switching PMOS transistors or switching NMOS transistors in other parallel branches are not turned on, and other parallel branches will not affect the signal in the serial wire 102.

[0054] In one example, the first selection signal CK1 and the second selection signal CK2 are discontinuous signals, i.e. Figure 6 The indicated slash level is empty; in one example, the branch signals IN1, IN2, IN3 and IN4 transmitted to the selection unit are discontinuous signals. In this case, when the first selection signal CK1 and the second selection signal CK2 are valid signals, the branch signals IN1, IN2, IN3 and IN4 have valid levels; in another example, both the selection signal and the branch signals are discontinuous signals, and the valid levels of the selection signal and the branch signals overlap.

[0055] In other examples, each parallel branch is used to receive signals from more than two branches, for example, using... Figure 5 The nested connection of selection units shown can be used to enable parallel branches to receive more than 2 branch signals, or each selection unit can be used to receive more than 2 branch signals to enable each parallel branch to receive more than 2 branch signals.

[0056] In some embodiments, reference Figure 5 The number of driving units 103 is equal to the number of parallel branches 101 to further ensure that the connection distance from each parallel input to the serial output is consistent. In some embodiments, if the number of parallel branches 101 is greater than 2, the number of driving units 103 can also be set to 2, that is, the number of driving units is less than the number of parallel branches. In some embodiments, if the number of driving units 103 is greater than 2, the number of parallel branches 101 can also be set to 2, that is, the number of driving units is greater than the number of parallel branches.

[0057] This embodiment of the disclosure receives multiple parallel signals through a selection unit in each parallel branch, and selects data from the received multiple parallel signals through a selection signal. This enables the transmission of multiple parallel signals through a single parallel branch, thereby saving the number of parallel branches required and further reducing the length of the serial wires required, thus reducing the load on the serial wires. In addition, by saving the number of parallel branches, the layout area occupied by some parallel branches is saved, thereby reducing the layout area of ​​the parallel-to-serial conversion circuit and achieving a greater degree of integration. Furthermore, by saving the number of parallel branches, the number of layout layers for setting up parallel branches is saved, thereby reducing the layout layer height of the parallel-to-serial conversion circuit.

[0058] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0059] It should be noted that the features disclosed in the parallel-to-serial conversion circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of the parallel-to-serial conversion circuit.

[0060] Another embodiment of this disclosure provides a parallel-to-serial conversion circuit layout for forming the parallel-to-serial conversion circuit provided in the above embodiments. By reducing the number of parallel branches, the layout area occupied by some of the parallel branch layouts is saved, thereby reducing the layout area of ​​the parallel-to-serial conversion circuit and achieving a greater degree of integration. In addition, by reducing the number of parallel branch layouts, the number of layout layers for setting the parallel branch layouts is reduced, thereby reducing the layout layer height of the parallel-to-serial conversion circuit layout. By setting the parallel branch layouts and the driver unit layouts in the same position on different layout layers, the delay between parallel input and serial output is kept consistent.

[0061] Figure 8 This is a schematic diagram of the layout of a parallel-to-serial converter circuit with two parallel branches provided in this embodiment. Figure 9 The diagram below shows the layout of the parallel-to-serial converter circuit with four parallel branches provided in this embodiment. The following is a detailed description of the parallel-to-serial converter circuit layout provided in this embodiment, in conjunction with the accompanying drawings: refer to Figure 8 and Figure 9 The parallel-to-serial conversion circuit layout includes: Parallel branch layout 401 is used to form parallel branches and to form selection units connected to the parallel branches.

[0062] The drive unit layout 402 is used to form the drive unit.

[0063] The parallel branch layout 401 and the driving unit layout 402 are set in the same layout layer, and the projections of multiple parallel branch layouts 401 in the direction perpendicular to the layout layer overlap, and the projections of multiple driving unit layouts 402 in the direction perpendicular to the layout layer overlap.

[0064] The serial wires connecting the parallel branch layout 401 and the driver unit layout 402 are projected in a direction perpendicular to the layout layer. By setting the parallel branch layout 401 and the driver unit layout 402 at the same position on different layout layers, the delay between parallel input and serial output is kept consistent.

[0065] By reducing the number of parallel branches, the layout area occupied by the parallel branch layout 401 is reduced, thereby reducing the layout area of ​​the parallel-to-serial conversion circuit and achieving a greater degree of integration. In addition, by reducing the number of parallel branch layouts 401, the number of layout layers for the parallel branch layout 401 is reduced, thereby reducing the layout layer height of the parallel-to-serial conversion circuit layout.

[0066] This embodiment uses a parallel-to-serial conversion circuit with two or four parallel branches 401 as an example to illustrate the specific layout of the parallel-to-serial conversion circuit, as follows: refer to Figure 8 and Figure 9 Each layout layer contains a parallel branch layout 401 and a driving unit layout 402. The parallel branch layout 401 and the driving unit layout 402 are in the same position in different layout layers. That is, the projections of multiple parallel branch layouts 401 in the direction perpendicular to the layout layer overlap, and the projections of multiple driving unit layouts 402 in the direction perpendicular to the layout layer overlap.

[0067] for Figure 8 and Figure 9 The schematic diagram of the layout structure shown shows that the number of driver unit layouts 402 and the number of parallel branch layouts 401 are the same. In some embodiments, the number of driver unit layouts 402 may be less than the number of parallel branch layouts 401, for example... Figure 9 In the schematic diagram of the layout structure shown, there are no driver unit layouts located in the middle two layout layers, or no driver unit layouts located in the edge two layout layers; similarly, in some embodiments, the number of parallel branch layouts 401 can be less than the number of driver unit layouts 402, for example... Figure 9 In the circuit shown, there is no parallel branch layout located in the middle two layers of the layout, or there is no parallel branch layout located in the edge two layers of the layout.

[0068] It should be noted that when the number of parallel branches 401 in the parallel-to-serial conversion circuit is greater than 4, its layout is based on... Figure 9 The layout shown is constructed to ensure that the lengths of the serial wires connecting all parallel-to-serial conversion circuits 401 and the drive unit layout 402 are equal.

[0069] It should be noted that the description of the parallel-to-serial conversion circuit layout above is similar to the description of the parallel-to-serial conversion circuit embodiments above, and has similar beneficial effects as the parallel-to-serial conversion circuit embodiments, therefore, it will not be repeated. For technical details not disclosed in the parallel-to-serial conversion circuit layout of the embodiments of this disclosure, please refer to the description of the parallel-to-serial conversion circuit in the embodiments of this disclosure for understanding.

[0070] Another embodiment of this disclosure provides a memory that employs the parallel-to-serial conversion circuit of the above embodiments, or the layout architecture of the memory is constructed using the layout of the above parallel-to-serial conversion circuit.

[0071] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR2 memory specification.

[0072] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR3 memory specification.

[0073] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR4 memory specification.

[0074] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR5 memory specification.

[0075] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A parallel-to-serial conversion circuit, characterized in that, include: Multiple parallel branches, each of which includes: a first input terminal, a second input terminal, a control terminal, and an output terminal; Wherein, the first input terminal is used to receive a high-level signal, the second input terminal is used to receive a low-level signal, the control terminal is connected to the selection unit, and the output terminal is connected to a serial wire; the high-level signal is provided by a first power supply signal that can be recognized as high by the memory, and the low-level signal is provided by a second power supply signal that can be recognized as low by the memory; The selection unit is used to receive a selection signal and at least two branch signals, and is configured to select one of the branch signals to be transmitted to the parallel branch based on the selection signal, and at most one of the selection signal and the branch signal received by the same selection unit is a continuous signal. The serial wire is used to serially arrange the signals output by the multiple parallel branches into a serial signal in time, so as to prevent the signals output by the other parallel branches from affecting the signal output by any one of the parallel branches when the signal output by the parallel branch is output through the serial wire. Multiple driving units are connected in parallel to the serial wire to enhance the driving capability of the serial wire. The output terminals of the multiple driving units are interconnected to output the serial signal. Each of the driving units is arranged adjacent to one of the parallel branches; The parallel branches and the driving units that are set up adjacent to each other are set in the same plate layer, and the projections of the multiple parallel branches in the direction perpendicular to the plate layer coincide, and the projections of the multiple driving units in the direction perpendicular to the plate layer coincide. The projections of the serial wires connecting the parallel branch and the driving unit in the direction perpendicular to the plate layer coincide.

2. The parallel-to-serial conversion circuit according to claim 1, characterized in that, The number of drive units is equal to the number of parallel branches.

3. The parallel-to-serial conversion circuit according to claim 1, characterized in that, The selection unit includes: a multiplexer and a selection subunit; The multiplexer is used to receive at least two of the branch signals and is connected to the selection subunit; The selection subunit is used to receive a selection command and generate the selection signal based on the selection command; The multiplexer is configured to select one of the branch signals based on the selection signal and transmit it to the parallel branch through the control terminal.

4. The parallel-to-serial conversion circuit according to claim 3, characterized in that, The multiplexer receives only two of the branch signals, and the selection command is an internal clock signal.

5. The parallel-to-serial conversion circuit according to claim 4, characterized in that, The period of the selection signal is n times the period of the internal clock signal, and n is the number of branches of the multiple parallel branches.

6. The parallel-to-serial conversion circuit according to claim 4, characterized in that, In the selection signals received by the selection units connected to the multiple parallel branches, high-level data are distributed alternately.

7. The parallel-to-serial conversion circuit according to claim 4, characterized in that, In the selection signals received by the selection units connected to the multiple parallel branches, the high-level data have overlapping portions.

8. The parallel-to-serial conversion circuit according to claim 1, characterized in that, The parallel branch includes: a switching PMOS transistor and a switching NMOS transistor; The gates of the PMOS and NMOS switches serve as the control terminals of the parallel branch and are used to connect to the selection unit. The drain of the PMOS transistor and the drain of the NMOS transistor are connected to the serial wire. The source of the switching PMOS transistor serves as the first input terminal of the parallel branch, used to receive the high-level signal; The source of the NMOS transistor serves as the second input terminal of the parallel branch, used to receive the low-level signal.

9. The parallel-to-serial conversion circuit according to claim 1, characterized in that, The driving unit includes two inverters, wherein the input terminal of one inverter is connected to the serial wire, the output terminal of the other inverter is connected to the input terminal of the other inverter, and the output terminal of the other inverter is used to output the serial signal.

10. The parallel-to-serial conversion circuit according to claim 9, characterized in that, The inverter includes: a driving PMOS transistor and a driving NMOS transistor; The gate of the driving PMOS transistor is connected to the gate of the driving NMOS transistor, and the drain of the driving PMOS transistor is connected to the drain of the driving NMOS transistor. The source of the driving PMOS transistor is used to receive the high-level signal, and the source of the driving NMOS transistor is used to receive the low-level signal.

11. A parallel-to-serial conversion circuit layout for forming the parallel-to-serial conversion circuit according to any one of claims 1 to 10, characterized in that, include: A parallel branch layout for forming the parallel branches and for forming the selection units connected to the parallel branches; A driver unit layout, used to form the driver unit; The parallel branch layout and the driving unit layout are arranged in the same layout layer, and the projections of multiple parallel branch layouts in the direction perpendicular to the layout layer overlap, and the projections of multiple driving unit layouts in the direction perpendicular to the layout layer overlap. The projections of the serial wires connecting the parallel branch layout and the drive unit layout in the direction perpendicular to the layout layer coincide.

12. The parallel-to-serial conversion circuit layout according to claim 11, characterized in that, The number of drive unit layouts is equal to the number of parallel branch layouts.

13. A memory, characterized in that, The memory employs the parallel-to-serial conversion circuit described in any one of claims 1 to 10.

14. A memory, characterized in that, The layout architecture of the memory adopts the parallel-to-serial conversion circuit layout described in claim 11 or 12.

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