Signal processing methods, apparatus, electronic devices and computer-readable storage media
By receiving and storing SSBs within the same frequency SSB measurement and reception window, and processing downlink signals and measuring and storing SSBs within the activation window, the problem of insufficient allocation of processor core resources is solved, and more efficient power utilization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 伟光有限公司(CN)
- Filing Date
- 2023-03-03
- Publication Date
- 2026-06-30
Smart Images
Figure CN116456357B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of mobile communication technology, and in particular to a signal processing method, apparatus, electronic device, and computer-readable storage medium. Background Technology
[0002] In Connected Discontinuous Reception (CDRX) measurements in New Radio (NR) mode, SSB (Signal Subsequent Signal-Based Bus) measurements need to be received and measured within the co-channel SSB measurement window configured in the network. However, in some cases, the co-channel SSB measurement window may appear outside the active window of the connected discontinuous reception. This necessitates receiving and measuring SSB separately within the co-channel SSB measurement window, and processing downlink signals within the active window. Consequently, the processor core shared by SSB measurement and downlink signal processing needs to be activated separately in separate time periods, leading to underutilization of the processor core's resources and increased power consumption. Summary of the Invention
[0003] This application provides a signal processing method, apparatus, electronic device, computer-readable storage medium, computer program product, and chip that can save power.
[0004] Firstly, this application provides a signal processing method. The method includes:
[0005] Acquire and store the SSBs received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is a window within the period configured in the same frequency SSB measurement configuration;
[0006] Within the active window, downlink signals are processed, and the stored SSB is measured; the active window is a window within a discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0007] Secondly, this application also provides a signal processing apparatus. The apparatus includes:
[0008] The storage module is used to acquire and store the SSBs received within the same-frequency SSB measurement receiving window; the same-frequency SSB measurement receiving window is a window within a period configured in the same-frequency SSB measurement configuration;
[0009] The processing module is used to process downlink signals and measure the stored SSB within the active window; the active window is a window within a discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0010] Thirdly, this application also provides an electronic device. The electronic device includes a memory and a processor, the memory storing a computer program, and the processor, when executing the computer program, causes the electronic device to perform the following steps:
[0011] Acquire and store the SSBs received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is a window within the period configured in the same frequency SSB measurement configuration;
[0012] Within the active window, downlink signals are processed, and the stored SSB is measured; the active window is a window within a discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0013] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:
[0014] Acquire and store the SSBs received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is a window within the period configured in the same frequency SSB measurement configuration;
[0015] Within the active window, downlink signals are processed, and the stored SSB is measured; the active window is a window within a discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0016] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:
[0017] Acquire and store the SSBs received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is a window within the period configured in the same frequency SSB measurement configuration;
[0018] Within the active window, downlink signals are processed, and the stored SSB is measured; the active window is a window within a discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0019] Sixthly, this application also provides a chip. The chip includes a processor, which, by running a computer program, causes the chip to perform the following steps:
[0020] Acquire and store the SSBs received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is a window within the period configured in the same frequency SSB measurement configuration;
[0021] Within the active window, downlink signals are processed, and the stored SSB is measured; the active window is a window within a discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0022] The aforementioned signal processing method, apparatus, electronic device, computer-readable storage medium, computer program product, and chip acquire and store the SSB received within the same-frequency SSB measurement and reception window. Without initially measuring the SSB, they process the downlink signal and measure the stored SSB within the active window. This eliminates the need to separately activate the processor core used for SSB measurement and downlink signal processing—such as a vector digital signal processor core—during the separate time periods of the same-frequency SSB measurement and reception window and the active window. Instead, SSB measurement and downlink signal processing are unified within the active window, allowing for full utilization of the processor core's resources and resulting in greater power savings. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a diagram illustrating the application environment of a signal processing method in one embodiment;
[0025] Figure 2 This is a flowchart of a signal processing method in one embodiment;
[0026] Figure 3 This is an overall timing diagram of the signal processing method in one embodiment;
[0027] Figure 4 This is a timing diagram of the processing for each time slot in the activation window in one embodiment;
[0028] Figure 5 Here is a timing diagram of the processing for each time slot in the activation window in another embodiment;
[0029] Figure 6 Here is a timing diagram of the processing for each time slot in the activation window in another embodiment;
[0030] Figure 7 This is a structural block diagram of a signal processing device in one embodiment;
[0031] Figure 8 This is a structural block diagram of an electronic device in one embodiment. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0033] The signal processing method provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, electronic device 102 communicates with base station 104 via a network. Base station 104 can send SSBs and downlink signals to electronic device 102. Electronic device 102 can receive and store SSBs within the same-frequency SSB measurement and reception window, receive and process downlink signals within the active window, and measure and store the stored SSBs. Electronic device 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart vehicle devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Base station 104 can be a radio transceiver station that transmits information between electronic devices and mobile communication switching centers within a certain radio coverage area. Base station 104 transmits and receives messages via antennas; its main function is to provide wireless coverage, i.e., to realize wireless signal transmission between wired communication networks and wireless terminals.
[0034] In one embodiment, such as Figure 2 As shown, a signal processing method is provided, which is applied to... Figure 1 Taking electronic device 102 as an example, the following steps are included:
[0035] Step 202: Acquire and store the SSB received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is the window within the period configured in the same frequency SSB measurement configuration.
[0036] The co-frequency SSB measurement reception window is a window used for receiving and measuring SSBs within a configured period (i.e., the co-frequency SSB measurement period) in the co-frequency SSB measurement configuration. The co-frequency SSB measurement configuration (SMTC, Measurement Timing Configuration) defines the duration period of SSB measurements in NR (New Radio). Each co-frequency SSB measurement period configured in the co-frequency SSB measurement configuration contains one co-frequency SSB measurement reception window. The SSB (SS / PBCH block) is the synchronization signal and master system information block.
[0037] In one embodiment, the radio frequency (RF) of the electronic device can receive SSBs within the same-frequency SSB measurement reception window. The baseband chip (BB) of the electronic device can acquire and store the SSBs received within the same-frequency SSB measurement reception window.
[0038] like Figure 3 As shown, the radio frequency (RF) of the electronic device receives the air interface signal containing the SSB within the same-frequency SSB measurement reception window (SMTC window) of each same-frequency SSB measurement cycle (SMTC cycle). Then, the baseband chip of the electronic device stores the SSB.
[0039] Step 204: Within the active window, process the downlink signal and measure the stored SSB; the active window is the window within the discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0040] The connected discontinuous reception period (CDRX) is the period measured in connected discontinuous reception. CDRX is a mechanism that periodically puts the electronic device into sleep mode, refraining from listening to downlink signals, and waking it up when it needs to listen for downlink signals. Each CDRX period contains an active window. The active window (CDRX on duration window) is the window within the connected discontinuous reception period used for receiving and processing downlink signals. Downlink signals are signals transmitted from the base station to the electronic device.
[0041] In one embodiment, the downlink signal may include at least one of the following: downlink control information (DCI) in the Physical Downlink Control Channel (PDCCH) and signals in the Physical Downlink Shared Channel (PDSCH).
[0042] In one embodiment, the radio frequency (RF) of the electronic device can receive downlink signals within an active window. The baseband chip of the electronic device can process the downlink signals and measure the stored SSB within the active window.
[0043] like Figure 3As shown, the radio frequency (RF) of the electronic device receives the air interface signal within the active window (CDRX on duration window) of the discontinuous reception cycle in each connected state. The air interface signal contains downlink control information (DCI) from the Physical Downlink Control Channel (PDCCH) and signals from the Physical Downlink Shared Channel (PDSCH). Then, the baseband chip of the electronic device processes the downlink signal and measures the SSB.
[0044] like Figure 3 As shown, the same-frequency SSB measurement reception window (SMTC window) is outside the active window (CDRX on duration window), meaning there is no overlap between the same-frequency SSB measurement reception window and the active window. In this case, it is necessary to receive SSB within the same-frequency SSB measurement reception window and receive downlink signals within the active window.
[0045] In one embodiment, the electronic device can perform channel filtering and parameter estimation during the processing of downlink signals and the measurement of stored SSBs via a Vector Digital Signal Processor (VDSP) core.
[0046] The above signal processing method acquires and stores the SSB received within the same-frequency SSB measurement and reception window, without initially measuring it. Instead, it processes the downlink signal and measures the stored SSB within the active window. This eliminates the need to separately activate the processor core used for measuring SSB and processing downlink signals, such as a vector digital signal processor core, during the two separate time periods of the same-frequency SSB measurement and reception window and the active window. Instead, it uniformly measures SSB and processes downlink signals within the active window, allowing the processor core's resources to be fully utilized and saving power.
[0047] In one embodiment, acquiring and storing SSBs received within the same frequency SSB measurement receiving window includes: acquiring SSBs received within the same frequency SSB measurement receiving window and storing the SSBs in an external dynamic memory.
[0048] External dynamic memory refers to the dynamic memory located outside the baseband chip.
[0049] In one embodiment, the external dynamic memory may be DDR (Double Data Rate, synchronous dynamic random access memory).
[0050] In one embodiment, the baseband chip of the electronic device can acquire the SSB received within the same frequency SSB measurement reception window and store the SSB in an external dynamic memory.
[0051] In the above embodiments, instead of measuring the SSB first, the SSB is stored in an external dynamic memory. Then, the SSB is measured and the downlink signal is processed in the same active window. This allows the resources of the processor core used for measuring the SSB and processing the downlink signal to be fully utilized, resulting in greater power savings.
[0052] In one embodiment, acquiring and storing SSBs received within the same frequency SSB measurement receiving window includes: acquiring SSBs received within the same frequency SSB measurement receiving window and storing the SSBs in an internal static memory; configuring the internal static memory to maintain the storage of SSBs with low power consumption.
[0053] Internal static memory refers to the static memory inside the baseband chip.
[0054] In one embodiment, the internal static memory may be static random-access memory (SRAM).
[0055] In one embodiment, the baseband chip of the electronic device can store the SSB in an internal static memory, and configure the internal static memory to maintain the storage of the SSB in a low-power manner using memory retention.
[0056] In the above embodiments, storing the SSB in the internal static memory and configuring the internal static memory to maintain the storage of the SSB with low power consumption can reduce power consumption and save more electricity.
[0057] like Figure 3 As shown, the radio frequency (RF) of the electronic device receives SSB within the same frequency SSB measurement and reception window (SMTC window). Then, the baseband chip of the electronic device can store the SSB in DDR or store it in the internal static memory in a memory retention manner.
[0058] In one embodiment, the method further includes: determining a window interval duration based on the same-frequency SSB measurement configuration and the discontinuous reception configuration in the connected state; the window interval duration is the duration of the interval between the same-frequency SSB measurement reception window and the active window; determining a target memory based on the window interval duration; and acquiring and storing the SSBs received within the same-frequency SSB measurement reception window, including: acquiring the SSBs received within the same-frequency SSB measurement reception window and storing the SSBs in the target memory.
[0059] In one embodiment, the baseband chip of the electronic device can determine the window interval duration based on the duration between the same-frequency SSB measurement receiving window configured in the same-frequency SSB measurement configuration and the active window of the discontinuous receiving configuration in the connected state.
[0060] In one embodiment, the baseband chip of the electronic device can determine the window interval duration based on the duration between the end time of the same-frequency SSB measurement reception window configured in the same-frequency SSB measurement configuration and the start time of the active window in the discontinuous reception configuration under connected state. For example... Figure 3 In this context, t0 represents the window interval duration.
[0061] In one embodiment, the baseband chip of an electronic device can compare the window interval duration with a first preset threshold and determine the target memory based on the comparison result. The first preset threshold is a preset threshold used to determine the target memory.
[0062] In the above embodiments, the window interval duration is determined based on the same-frequency SSB measurement configuration and the discontinuous reception configuration in the connected state. Based on the window interval duration, the target memory is determined, and the SSB is stored in the target memory. This allows for the selection of a suitable target memory for storage based on the window interval duration, thereby reducing power consumption.
[0063] In one embodiment, the window interval duration is within the range between a first preset duration and a second preset duration.
[0064] The window interval duration can be determined based on the time interval between the same-frequency SSB measurement reception window and the active window configured in the network. The window interval duration configured in the network is within the range between a first preset duration and a second preset duration. The first preset duration is shorter than the second preset duration.
[0065] For example, the first preset duration can be 0ms (milliseconds), and the second preset duration can be 160ms (milliseconds). Then the window interval duration is in the range of [0, 160]. For example, the window interval duration configured in the network can be 130ms.
[0066] In the above embodiments, the window interval duration is within the range between the first preset duration and the second preset duration, which ensures that the window interval duration is within a reasonable range.
[0067] In one embodiment, determining the target memory based on the window interval duration includes: if the window interval duration is greater than a first preset threshold, determining an external dynamic memory as the target memory.
[0068] The first preset threshold varies depending on the manufacturer of the baseband chip.
[0069] In one embodiment, when the window interval duration exceeds a first preset threshold, the baseband chip of the electronic device can store the SSB in an external dynamic memory.
[0070] For example, if the first preset threshold is 160ms, then when the window interval is longer than 160ms, the baseband chip of the electronic device can store the SSB in the external dynamic memory and power off the internal static memory.
[0071] In the above embodiments, since the internal static memory uses a low-power retention method for storage, while the external dynamic memory consumes power during storage and retrieval, when the window interval is longer than the first preset threshold, if the internal static memory is used, it needs to continuously maintain low power. However, if the external dynamic memory is used, it only consumes power during storage and retrieval, and the power consumption is smaller than that of continuous low-power retention. That is, the sum of the storage power consumption of the external dynamic memory and the retrieval power consumption of the next access to the external dynamic memory is less than the storage power consumption of the internal static memory. Therefore, it is more suitable to determine the external dynamic memory as the target memory, which can reduce power consumption and save more electricity.
[0072] In one embodiment, determining the target memory based on the window interval duration includes: determining the internal static memory as the target memory when the window interval duration is less than or equal to a first preset threshold.
[0073] In one embodiment, when the window interval duration is less than or equal to a first preset threshold, the baseband chip of the electronic device can store the SSB in the internal static memory.
[0074] For example, if the first preset threshold is 160ms, then when the window interval is less than or equal to 160ms, the baseband chip of the electronic device can store the SSB in the internal static memory.
[0075] In the above embodiments, since the internal static memory uses a low-power retention method for storage, while the external dynamic memory consumes power during storage and retrieval, when the window interval is less than or equal to the first preset threshold, if the external dynamic memory is used, storage and retrieval need to be performed in a short time, resulting in higher power consumption. However, if the internal static memory is used, it only needs to be retained at low power for a short time, and the power consumption is less than that of the external dynamic memory during storage and retrieval. That is, the storage power consumption of the internal static memory is less than the sum of the storage power consumption of the external dynamic memory and the retrieval power consumption of the next access to the external dynamic memory. Therefore, it is more suitable to determine the internal static memory as the target memory, which can reduce power consumption and save more electricity.
[0076] In one embodiment, processing downlink signals and measuring stored SSB within an active window includes: processing downlink signals in a time slot within the active window, and measuring stored SSB during a spare time after processing downlink signals in the time slot.
[0077] In NR, a slot is the standard scheduling unit. An active window contains multiple slots.
[0078] In one embodiment, the baseband chip of the electronic device can first process the downlink signal in the time slot within the active window. If there is still spare time in the time slot after processing the downlink signal, the baseband chip of the electronic device can measure the stored SSB. If there is no spare time in the time slot after processing the downlink signal, it directly enters the next time slot.
[0079] In one embodiment, processing downlink signals has a high priority, while measuring SSBs has a low priority. The baseband chip of the electronic device can prioritize processing high-priority tasks in each time slot and process low-priority tasks during the idle time after processing high-priority tasks in each time slot.
[0080] In the above embodiments, the downlink signal in the time slot within the active window is processed, and the stored SSB is measured in the spare time after the downlink signal is processed in the time slot. Thus, the resources of the processor cores used for processing the downlink signal and measuring the SSB can be fully utilized, resulting in greater power saving.
[0081] In one embodiment, the method further includes: after processing the downlink signal within the active window, if there are still unmeasured SSBs, measuring the unmeasured SSBs in the remaining time slots of the active window.
[0082] It is understandable that after processing the downlink signal within the active window, some SSBs may have been measured while others, or none may have been measured. The baseband chip of the electronic device can measure the unmeasured SSBs during the remaining time slots within the active window. Specifically, if there is spare time to measure the SSBs after processing the downlink signal within a time slot, a situation may arise where some SSBs have been measured while others have not. Conversely, if there is no spare time to measure the SSBs during any downlink signal processing time slot, a situation may arise where all SSBs are unmeasured after processing the downlink signal within the active window.
[0083] In the above embodiments, after the downlink signal processing is completed within the activation window, if there are still unmeasured SSBs, the unmeasured SSBs are measured. This allows the processor core resources required for both downlink signal processing and SSB measurement to be fully utilized, resulting in greater power savings.
[0084] like Figure 4 , Figure 5 and Figure 6 In the above embodiments, the downlink signal in each time slot within the active window is processed, and the stored SSB is measured during the idle time after processing the downlink signal in the time slot. As can be seen from the three figures, in each time slot, the baseband chip of the electronic device first processes the downlink signal in the time slot (i.e., the PDCCH Process and PDSCH Process in the figure). If there is still idle time after processing the downlink signal in the time slot, the SSB is measured during the idle time (i.e., the Measurement Process in the figure). If there are still unmeasured SSBs after processing the downlink signal in the active exit window, the unmeasured SSBs are measured. For example: Figure 4 After processing the downlink signal in the first two time slots, there is still spare time. Therefore, the SSB (i.e., ...) is measured during the spare time in the first two time slots. Figure 4 If, in the measurement process, there are no unmeasured SSBs in the last time slot, then there is no need to measure SSBs in the last time slot. For example: Figure 5 The first three time slots require both detecting the downlink control signal (DCI) in the physical downlink control channel (PDCCH) and receiving and processing signals in the physical downlink shared channel (PHSS). This leaves no spare time after processing the downlink signals in the first three time slots. Therefore, the SSB is measured in the last time slot. For example: Figure 6 In the first and third time slots, it is necessary to detect the downlink control signal (DCI) in the physical downlink control channel (PDCCH) and to receive and process signals in the physical downlink shared channel (PDCCH). There is no spare time to measure the SSB. In the second time slot, there is still spare time after processing the downlink control signal in the PDCCH. Therefore, the SSB is measured during the spare time of the second time slot. After processing the downlink signal in the active window, there are still unmeasured SSBs. Therefore, the SSB is measured in the last time slot.
[0085] In one embodiment, processing downlink signals in a time slot within an active window and measuring the stored SSB during a spare time after processing downlink signals in a time slot includes: detecting downlink control signals in a physical downlink control channel within a time slot within an active window; and measuring the stored SSB during a spare time after detecting downlink control signals in a time slot if no downlink control signals are detected.
[0086] It is understandable that if no downlink control signal is detected, it indicates that there is no signal to be received in the physical downlink shared channel. Therefore, the stored SSB is measured during the empty time after the downlink control signal is detected in the time slot.
[0087] like Figure 4 In each time slot, the downlink control signal in the physical downlink control channel is detected (i.e., Figure 4 If no downlink control signal is detected during the PDCCH Process, then there is no signal to receive in the physical downlink shared channel. The SSB is measured during the idle time after detecting the downlink control signal in each time slot. Figure 6 In the second time slot, the downlink control signal in the physical downlink control channel is detected (i.e., Figure 6 If no downlink control signal is detected during the PDCCH Process, then there is no signal to be received in the physical downlink shared channel. In the spare time after detecting the downlink control signal in the physical downlink control channel in this time slot, the SSB can be measured.
[0088] In the above embodiments, in each time slot within the active window, the downlink control signal in the physical downlink control channel is detected. If no downlink control signal is detected, the stored SSB is measured during the spare time after the downlink control signal is detected in the time slot. This allows the resources of the processor cores that are used for processing downlink signals and measuring SSB to be fully utilized, resulting in greater power savings.
[0089] In one embodiment, the method further includes: upon detecting a downlink control signal, receiving a signal in the physical downlink shared channel in a time slot in response to the downlink control signal; and measuring the stored SSB during the idle time after receiving the signal in the physical downlink shared channel in the time slot.
[0090] It is understandable that when a downlink control signal is detected in a time slot, it indicates that there is a signal in the physical downlink shared channel that needs to be received. The baseband chip of the electronic device can respond to the downlink control signal and receive the signal in the physical downlink shared channel in that time slot.
[0091] In one embodiment, if there is still spare time after detecting the downlink control signal and receiving the signal in the physical downlink shared channel during a time slot, the baseband chip of the electronic device can measure the stored SSB. In another embodiment, if there is no spare time after detecting the downlink control signal and receiving the signal in the physical downlink shared channel during a time slot, the device directly proceeds to the next time slot.
[0092] like Figure 5In the first three time slots, downlink control signals are detected, and signals from the physical downlink shared channel are received within the time slots. This results in no spare time in the time slots after detecting the downlink control signal and receiving the physical downlink shared channel signal. Therefore, the SSB is measured only after the downlink signal has been processed within the active window. Figure 6 In the first and third time slots, downlink control signals are detected, and signals in the physical downlink shared channel are received in the time slots. As a result, there is no spare time in the time slot after detecting downlink control signals and receiving signals in the physical downlink shared channel, so it directly enters the next time slot without measuring SSB in the time slot.
[0093] In the above embodiments, when a downlink control signal is detected, in response to the downlink control signal, the signal in the physical downlink shared channel is received in the time slot, and the stored SSB is measured in the spare time after receiving the signal in the physical downlink shared channel. This enables the processor core resources that are needed for processing downlink signals and measuring SSB to be fully utilized, thus saving more power.
[0094] In one embodiment, the method further includes reducing the operating voltage of the baseband chip to a target operating voltage each time the stored SSB is measured.
[0095] The target operating voltage is lower than the operating voltage of the baseband chip when processing downlink signals.
[0096] In one embodiment, when measuring the stored SSB each time, the baseband chip of the electronic device can reduce the operating voltage of the baseband chip to a target operating voltage and adjust the operating frequency to the operating frequency corresponding to the target operating voltage, so as to measure the SSB with the target operating voltage and the operating frequency corresponding to the target operating voltage.
[0097] In one embodiment, the target operating voltage may have multiple corresponding operating frequencies.
[0098] In one embodiment, the target operating voltage can be the lowest operating voltage of the baseband chip.
[0099] For example, when processing downlink signals, the baseband chip operates at a voltage of 0.6V and a frequency of 500MHz. When measuring SSB, the baseband chip only needs to operate at a voltage of 0.55V and a frequency of 300MHz, which saves more power when measuring SSB.
[0100] In the above embodiments, the operating voltage of the baseband chip is reduced to the target operating voltage, and the SSB is measured at the target operating voltage and the corresponding operating frequency, which saves more power.
[0101] In one embodiment, the method further includes: adjusting the operating frequency of the baseband chip to the target operating frequency corresponding to the target operating voltage.
[0102] In one embodiment, the baseband chip of the electronic device can reduce the operating voltage to a target operating voltage and adjust the operating frequency to a target operating frequency corresponding to the target operating voltage, and measure the SSB using the target operating voltage and the target operating frequency corresponding to the target operating voltage.
[0103] In one embodiment, the target operating frequency corresponding to the target operating voltage can be the highest operating frequency corresponding to the target operating voltage. Here, the highest operating frequency corresponding to the target operating voltage refers to the highest operating frequency among the operating frequencies corresponding to the target operating voltage.
[0104] In one embodiment, the highest operating frequency corresponding to the target operating voltage can be the highest operating frequency corresponding to the lowest operating voltage.
[0105] In the above embodiments, the SSB is measured using the target operating voltage and the target operating frequency corresponding to the target operating voltage. Because the operating voltage is reduced to the target operating voltage, it is more energy-efficient. Because the target operating frequency corresponding to the target operating voltage is used, higher measurement efficiency can be guaranteed. Therefore, this embodiment can ensure high measurement efficiency while saving energy.
[0106] In one embodiment, the method further includes: entering a wake-up phase from a deep sleep phase, performing wake-up processing in the wake-up phase; entering a working phase from the wake-up phase when the same-frequency SSB measurement reception window arrives, and performing the step of acquiring and storing the SSB received within the same-frequency SSB measurement reception window in the working phase.
[0107] The deep sleep phase refers to the stage in which the signal processing components of the electronic device are in deep sleep during discontinuous reception in connected mode. The wakeup phase is the stage in discontinuous reception in connected mode that wakes the device from the deep sleep phase to prepare for the working phase. The working phase is the stage in discontinuous reception in connected mode where signals are processed. In one embodiment, the wakeup process may include at least one of the following: power restoration of the power management integrated circuit (PMIC), restoration of phase-locked loops (PLLs), memory restoration, startup of the high-speed interface of the RF-baseband chip (RF-BB), and startup of the RF chip. In one embodiment, the wakeup process does not include startup of the baseband measurement system and the downlink receiving system.
[0108] In one embodiment, starting the high-speed interface of the radio frequency-baseband (RF-BB) may include powering up, image loading, and initialization of the high-speed interface of the radio frequency-baseband (RF-BB).
[0109] In one embodiment, starting up a radio frequency (RF) chip may include powering on the RF chip, downloading code segments, and initializing it.
[0110] In the above embodiments, SSBs are received and stored within the same-frequency SSB measurement and reception window without measurement. Downlink signals are processed and stored SSBs are measured only when the activation window is reached. This eliminates the need to start the processor core used for measuring SSBs and processing downlink signals separately during the two separate time periods of the same-frequency SSB measurement and reception window and the activation window. Instead, SSBs are measured and downlink signals are processed uniformly within the activation window, allowing the processor core's resources to be fully utilized and saving power.
[0111] In one embodiment, the method further includes: entering a light sleep phase from an operating phase; entering a recovery phase from the light sleep phase before an activation window, in which the baseband measurement system and the downlink receiving system are started; and processing the downlink signal and measuring the stored SSB within the activation window, including: entering an operating phase after the recovery phase when the activation window arrives, in which the downlink signal is processed by the downlink receiving system and the stored SSB is measured by the baseband measurement system within the activation window during the operating phase.
[0112] The light sleep phase is a stage in which some components of the electronic equipment used for signal processing in connected discontinuous reception suspend operation. The resume phase is the stage in connected discontinuous reception that awakens from the light sleep phase and prepares for the operational phase. The baseband measurement system is used to measure the SSB (Special Signal Band Size). The downlink receiving system is used to receive and process downlink signals.
[0113] In one embodiment, during a light sleep phase, the baseband of the electronic device can keep the power management integrated circuit, phase-locked loop, and memory operational, while putting the high-speed interface of the radio frequency-baseband (RF-BB) and the radio frequency (RF) chip into a suspended state.
[0114] In one embodiment, during the recovery phase, in addition to activating the baseband measurement system and downlink receiving system, the baseband of the electronic device can also keep the power management integrated circuit, phase-locked loop and memory operational, and restore the high-speed interface of the radio frequency-baseband (RF-BB) and the radio frequency (RF) chip.
[0115] In the above embodiments, it is not necessary to start the baseband measurement system and downlink receiving system during the wake-up phase. Instead, the baseband measurement system and downlink receiving system are started during the recovery phase after a light sleep. This avoids the power leakage caused by keeping the baseband measurement system and downlink receiving system on during the time period between the same-frequency SSB measurement receiving window and the activation window, thereby reducing power consumption.
[0116] In one embodiment, starting the baseband measurement system and downlink receiving system during the recovery phase includes: powering on the baseband measurement system and downlink receiving system, downloading code segments, and initializing them during the recovery phase.
[0117] In the above embodiments, during the recovery phase, the baseband measurement system and the downlink receiving system are powered on, the code segment is downloaded, and initialization is performed. This avoids the power leakage caused by starting the baseband measurement system and the downlink receiving system during the wake-up phase, which would result in the baseband measurement system and the downlink receiving system remaining on during the time period between the co-frequency SSB measurement receiving window and the activation window. This reduces power consumption.
[0118] Figure 3 The horizontal axis in the diagram represents the time axis, from... Figure 3The timelines illustrate the entire process of discontinuous reception in the connected state described in this application. First, the baseband chip of the electronic device enters a deep sleep phase, then transitions to a wake-up phase. During the wake-up phase, the baseband chip can restore power to the power management integrated circuit (PMIC), restore the phase-locked loop (PLL), restore the memory (DDR), power on the high-speed interface of the RF-baseband chip (RF-BB), download and initialize the code segment, and power on, download and initialize the RF chip. When the same-frequency SSB measurement reception window arrives, the baseband chip can enter the working phase. During the working phase, the RF receiver can receive SSBs, and the baseband chip can store the SSBs. After the working phase ends, the baseband chip of the electronic device can enter a light sleep phase. In this phase, the baseband chip keeps the power management integrated circuit (PMIC), phase-locked loop (PLL), and memory (DDR) active, while suspending the high-speed interface of the RF-baseband (RF-BB) and the RF chip. Then, it enters a resume phase. In this phase, the baseband chip powers on the baseband measurement system and downlink receiving system, downloads and initializes the code segment, keeps the PMIC, PLL, and DDR active, and resumes the high-speed interface of the RF-baseband (RF-BB) and the RF chip. When the activation window arrives, it enters the working phase, processing downlink signals and measuring the SSB. After the working phase, it enters the sleep preparation phase, followed by the deep sleep phase.
[0119] In one embodiment, transitioning from a working phase to a light sleep phase includes: transitioning from a working phase to a light sleep phase when the window interval duration is less than or equal to a second preset threshold.
[0120] The second preset threshold is a pre-defined threshold used to determine whether the window interval between the receiving window and the activation window of the same-frequency SSB measurement is sufficient to enter the deep sleep stage. The second preset threshold varies depending on the baseband chip manufacturer.
[0121] It is understandable that if the window interval is less than or equal to the second preset threshold, it indicates that the interval between the same frequency SSB measurement receiving window and the activation window is insufficient to enter the deep sleep stage and then wake up from the deep sleep stage. Therefore, the electronic device can enter the light sleep stage.
[0122] For example, if the second preset threshold is 20ms, then when the window interval is less than or equal to 20ms, the electronic device can enter a light sleep stage between the same frequency SSB measurement receiving window and the activation window.
[0123] In the above embodiments, when the window interval duration is less than or equal to the second preset threshold, the system transitions from the working stage to the light sleep stage, thereby intelligently determining whether it is necessary to enter the light sleep stage.
[0124] In one embodiment, the method further includes: entering a deep sleep phase from the working phase when the window interval duration is greater than a second preset threshold; entering a wake-up phase from the deep sleep phase before activating the window, and starting the baseband measurement system and the downlink receiving system in the wake-up phase; entering the working phase when the activation window arrives, processing the downlink signal through the downlink receiving system, and measuring the stored SSB through the baseband measurement system.
[0125] For example, if the second preset threshold is 20ms, then when the window interval is longer than 20ms, the electronic device can enter a deep sleep stage between the same frequency SSB measurement receiving window and the activation window.
[0126] In the above embodiments, when the window interval duration is greater than a second preset threshold, the system transitions from the working stage to the deep sleep stage, thereby intelligently determining whether it is possible to enter the deep sleep stage.
[0127] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0128] Based on the same inventive concept, this application also provides a signal processing apparatus for implementing the signal processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more signal processing apparatus embodiments provided below can be found in the limitations of the signal processing method above, and will not be repeated here.
[0129] In one embodiment, such as Figure 7 As shown, a signal processing device 700 is provided, including: a storage module 702 and a processing module 704, wherein:
[0130] The storage module 702 is used to acquire and store the SSBs received within the same frequency SSB measurement receiving window; the same frequency SSB measurement receiving window is a window within the period configured in the same frequency SSB measurement configuration.
[0131] The processing module 704 is used to process downlink signals and measure stored SSBs within the active window; the active window is the window within the discontinuous reception period in the connected state; the same-frequency SSB measurement reception window is outside the active window.
[0132] In one embodiment, the storage module 702 is further configured to acquire the SSB received within the same frequency SSB measurement receiving window and store the SSB in an external dynamic memory.
[0133] In one embodiment, the storage module 702 is further configured to acquire the SSB received within the same frequency SSB measurement receiving window and store the SSB in the internal static memory; and configure the internal static memory to maintain the storage of the SSB with low power consumption.
[0134] In one embodiment, the storage module 702 is further configured to determine the window interval duration based on the same-frequency SSB measurement configuration and the discontinuous reception configuration in the connected state; the window interval duration is the duration between the same-frequency SSB measurement reception window and the active window; determine the target memory based on the window interval duration; acquire the SSB received within the same-frequency SSB measurement reception window, and store the SSB in the target memory.
[0135] In one embodiment, the window interval duration is within the range between a first preset duration and a second preset duration.
[0136] In one embodiment, the storage module 702 is further configured to determine the external dynamic memory as the target memory when the window interval duration is greater than a preset threshold.
[0137] In one embodiment, the storage module 702 is further configured to determine the internal static memory as the target memory when the window interval duration is less than or equal to a preset threshold.
[0138] In one embodiment, the processing module 704 is further configured to process the downlink signal in the time slot within the active window, and measure the stored SSB during the idle time after processing the downlink signal in the time slot.
[0139] In one embodiment, the processing module 704 is further configured to measure the unmeasured SSBs in the remaining time slots of the active window after processing the downlink signal within the active window, provided that there are still unmeasured SSBs.
[0140] In one embodiment, the processing module 704 is further configured to detect downlink control signals in the physical downlink control channel during a time slot within the active window; and, if no downlink control signal is detected, to measure the stored SSB during the idle time after detecting the downlink control signal in the time slot.
[0141] In one embodiment, the processing module 704 is further configured to, upon detecting a downlink control signal, receive a signal in the physical downlink shared channel in a time slot in response to the downlink control signal; and measure the stored SSB during the idle time after receiving the signal in the physical downlink shared channel in the time slot.
[0142] In one embodiment, the processing module 704 is further configured to reduce the operating voltage of the baseband chip to a target operating voltage each time the stored SSB is measured.
[0143] In one embodiment, the processing module 704 is further configured to adjust the operating frequency of the baseband chip to the target operating frequency corresponding to the target operating voltage.
[0144] In one embodiment, the processing module 704 is further configured to enter a wake-up phase from a deep sleep phase, and perform wake-up processing in the wake-up phase; and enter a working phase from the wake-up phase when the same-frequency SSB measurement reception window arrives, and perform the step of acquiring and storing the SSB received within the same-frequency SSB measurement reception window in the working phase.
[0145] In one embodiment, the processing module 704 is further configured to enter a light sleep phase from the working phase; enter a recovery phase from the light sleep phase before the activation window, in which the baseband measurement system and the downlink receiving system are started; and enter the working phase when the activation window arrives after the recovery phase, in which the downlink signal is processed by the downlink receiving system and the stored SSB is measured by the baseband measurement system within the activation window.
[0146] In one embodiment, the processing module 704 is further configured to power on, download code segments, and initialize the baseband measurement system and downlink receiving system during the recovery phase.
[0147] In one embodiment, the processing module 704 is further configured to transition from the working phase to a light sleep phase when the window interval duration is less than or equal to a second preset threshold.
[0148] In one embodiment, the processing module 704 is further configured to enter a deep sleep phase from the working phase when the window interval duration is greater than a second preset threshold; enter a wake-up phase from the deep sleep phase before activating the window, and start the baseband measurement system and downlink receiving system in the wake-up phase; enter the working phase when the activation window arrives, process the downlink signal through the downlink receiving system, and measure the stored SSB through the baseband measurement system.
[0149] The aforementioned signal processing device acquires and stores the SSB received within the same-frequency SSB measurement and reception window. Without measuring it initially, it processes the downlink signal and measures the stored SSB within the active window. This eliminates the need to separately activate the processor core used for measuring SSB and processing downlink signals, such as a vector digital signal processor core, during the two separate time periods of the same-frequency SSB measurement and reception window and the active window. Instead, it uniformly measures SSB and processes downlink signals within the active window, allowing the processor core's resources to be fully utilized and saving power.
[0150] Each module in the aforementioned signal processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independent of it, or stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each module.
[0151] In one embodiment, an electronic device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 8As shown, this electronic device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a signal processing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the electronic device, or external keyboards, touchpads, or mice, etc.
[0152] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0153] This application also provides a computer-readable storage medium. One or more non-volatile computer-readable storage media containing computer-executable instructions, which, when executed by one or more processors, cause the processors to perform the steps of a signal processing method.
[0154] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform a signal processing method.
[0155] This application also provides a chip, including a processor, which executes a computer program to implement the signal processing methods in the various embodiments of this application.
[0156] In one embodiment, the chip can be any one of a baseband chip, an application chip with an integrated baseband chip module, or a system on chip (SOC).
[0157] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0158] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0159] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A signal processing method, characterized in that, include: Acquire and store the SSBs received within the same frequency SSB measurement reception window; The same-frequency SSB measurement receiving window is the window within the period configured in the same-frequency SSB measurement configuration; Within the active window, the downlink signal is processed, and the stored SSB is measured; The activation window is the window within the discontinuous reception period in the connected state; The same-frequency SSB measurement receiving window is outside the active window.
2. The method according to claim 1, characterized in that, The step of acquiring and storing the SSB received within the same frequency SSB measurement reception window includes: Acquire the SSB received within the same frequency SSB measurement receiving window and store the SSB in an external dynamic memory.
3. The method according to claim 1, characterized in that, The step of acquiring and storing the SSB received within the same frequency SSB measurement reception window includes: Acquire the SSB received within the same frequency SSB measurement receiving window and store the SSB in the internal static memory; The internal static memory is configured to maintain the storage of the SSB with low power consumption.
4. The method according to claim 1, characterized in that, The method further includes: The window interval duration is determined based on the same-frequency SSB measurement configuration and the discontinuous reception configuration in the connected state; the window interval duration is the duration between the same-frequency SSB measurement reception window and the active window. The target memory is determined based on the window interval duration; The step of acquiring and storing the SSB received within the same frequency SSB measurement reception window includes: Acquire the SSB received within the same frequency SSB measurement receiving window and store the SSB in the target memory.
5. The method according to claim 4, characterized in that, The window interval duration is within the range between a first preset duration and a second preset duration.
6. The method according to claim 4, characterized in that, The step of determining the target memory based on the window interval duration includes: If the window interval duration is greater than a first preset threshold, the external dynamic memory is determined as the target memory.
7. The method according to claim 4, characterized in that, The step of determining the target memory based on the window interval duration includes: If the window interval duration is less than or equal to a first preset threshold, the internal static memory is determined as the target memory.
8. The method according to claim 1, characterized in that, The process of processing downlink signals and measuring the stored SSB within the activation window includes: During the time slot within the active window, the downlink signal in the time slot is processed, and during the idle time after processing the downlink signal in the time slot, the stored SSB is measured.
9. The method according to claim 8, characterized in that, The method further includes: After the downlink signal processing is completed within the active window, if there are still unmeasured SSBs, the unmeasured SSBs are measured in the remaining time slots of the active window.
10. The method according to claim 8, characterized in that, The step of processing the downlink signal in the time slot within the active window, and measuring the stored SSB during the idle time after processing the downlink signal in the time slot, includes: During the time slots within the active window, detect the downlink control signal in the physical downlink control channel; In the absence of a downlink control signal detected in the time slot, the stored SSB is measured during the idle time after the downlink control signal is detected in the time slot.
11. The method according to claim 10, characterized in that, The method further includes: Upon detection of a downlink control signal, in response to the downlink control signal, a signal in the physical downlink shared channel is received in the time slot; During the spare time after receiving the signal in the physical downlink shared channel in the time slot, the stored SSB is measured.
12. The method according to claim 8, characterized in that, The method further includes: Each time the stored SSB is measured, the operating voltage of the baseband chip is reduced to the target operating voltage.
13. The method according to claim 12, characterized in that, The method further includes: Adjust the operating frequency of the baseband chip to the target operating frequency corresponding to the target operating voltage.
14. The method according to any one of claims 1 to 13, characterized in that, The method further includes: The process begins when the body transitions from deep sleep to the wake-up stage, where wake-up procedures are performed. When the same-frequency SSB measurement and reception window arrives, the system enters the working phase from the wake-up phase, and performs the step of acquiring and storing the SSB received within the same-frequency SSB measurement and reception window during the working phase.
15. The method according to claim 14, characterized in that, The method further includes: From the aforementioned working phase, one enters a light sleep phase; Before the activation window, the system transitions from the light sleep phase to the recovery phase, during which the baseband measurement system and downlink receiving system are started. The process of processing downlink signals and measuring the stored SSB within the activation window includes: After the recovery phase, the working phase begins when the activation window arrives. During the working phase, within the activation window, the downlink signal is processed by the downlink receiving system, and the stored SSB is measured by the baseband measurement system.
16. The method according to claim 15, characterized in that, The startup of the baseband measurement system and downlink receiving system during the recovery phase includes: During the recovery phase, the baseband measurement system and downlink receiving system are powered on, code segments are downloaded, and initialization is performed.
17. The method according to claim 15, characterized in that, The transition from the working phase to the light sleep phase includes: If the window interval is less than or equal to the second preset threshold, the system transitions from the working phase to a light sleep phase.
18. The method according to claim 14, characterized in that, The method further includes: If the window interval exceeds the second preset threshold, the device transitions from the working phase to the deep sleep phase. Before the activation window, the system transitions from deep sleep to wake-up, during which the baseband measurement system and downlink receiving system are activated. When the activation window arrives, the system enters the working phase, processes the downlink signal through the downlink receiving system, and measures the stored SSB through the baseband measurement system.
19. A signal processing apparatus, characterized in that, include: The storage module is used to acquire and store the SSBs received within the same frequency SSB measurement receiving window; The same-frequency SSB measurement receiving window is the window within the period configured in the same-frequency SSB measurement configuration; The processing module is used to process the downlink signal and measure the stored SSB within the active window; The activation window is the window within the discontinuous reception period in the connected state; The same-frequency SSB measurement receiving window is outside the active window.
20. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the computer program is executed by the processor, it causes the electronic device to perform the steps of the signal processing method as described in any one of claims 1 to 18.
21. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 18.
22. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 18.
23. A chip comprising a processor, the processor executing a computer program to implement the signal processing method as described in any one of claims 1 to 18.