Circuit configuration

Abstract

A circuit structure includes a circuit board, a first microstrip line, a second microstrip line, a third microstrip line, a strip line, a first via, and a second via. The circuit board includes a first conductive layer and a second conductive layer. A first transceiver and a second transceiver are disposed on the first conductive layer. The first microstrip line is disposed on the first conductive layer to couple a first pin of the first transceiver to a second pin of the second transceiver. The second microstrip line and the third microstrip line are disposed on the first conductive layer to couple a third pin of the first transceiver and a fourth pin of the second transceiver, respectively. The strip line is disposed on the second conductive layer. The first via and the second via penetrate the first conductive layer and the second conductive layer to couple the second microstrip line and the third microstrip line to the strip line, respectively. The first pin is an inner side pin of a front row of a ball grid array of the first transceiver. The third pin is an outer side pin of the front row of the ball grid array.

Description

Technical Field

[0001] This invention relates to a circuit structure, and more particularly to a circuit structure comprising microstrip lines and striplines. Background Technology

[0002] For circuits with a large number of signals, traces are usually compressed quite densely due to the limited circuit wiring area. However, dense traces often generate significant interference (such as crosstalk). Therefore, controlling interference between traces is crucial. Summary of the Invention

[0003] This invention discloses a circuit structure for connecting a first transceiver circuit and a second transceiver circuit. The circuit structure includes a circuit board, a first microstrip line, a second microstrip line, a third microstrip line, a first microstrip line, a first path, and a second path. The circuit board includes a first conductive layer and a second conductive layer stacked together, wherein the first transceiver circuit and the second transceiver circuit are disposed on the first conductive layer. The first microstrip line is disposed on the first conductive layer and is used to couple a first pin of the first transceiver circuit to a second pin of the second transceiver circuit. The second microstrip line is disposed on the first conductive layer and is coupled to a third pin of the first transceiver circuit. The third microstrip line is disposed on the first conductive layer and is coupled to a fourth pin of the second transceiver circuit. The first microstrip line is disposed on the second conductive layer. The first path penetrates the first conductive layer and the second conductive layer and is used to couple the second microstrip line to the first microstrip line. The second path penetrates the first conductive layer and the second conductive layer and is used to couple the third microstrip line to the first microstrip line. The first pin is the inner pin of the front row of the ball grid array of the first transceiver circuit, and the third pin is the outer pin of the front row of the ball grid array of the first transceiver circuit.

[0004] This invention discloses a circuit structure connecting a control circuit and a memory circuit. The circuit structure includes a circuit board, a plurality of first microstrip lines, and a plurality of first composite conductive lines. The circuit board includes a first conductive layer and a second conductive layer stacked together, wherein the control circuit and the memory circuit are disposed on the first conductive layer. The plurality of first microstrip lines are disposed on the first conductive layer, respectively coupling a plurality of first pins of the control circuit to a plurality of second pins of the memory circuit. The plurality of first composite conductive lines respectively couple a plurality of third pins of the control circuit to a plurality of fourth pins of the memory circuit, wherein each of the plurality of first composite conductive lines is disposed on the first conductive layer and the second conductive layer. The plurality of first pins are the inner pins of the front row of the ball grid array of the control circuit, and the plurality of third pins are the outer pins of the front row of the ball grid array of the control circuit.

[0005] Compared to existing technologies, the circuit structure of the present invention reduces crosstalk between traces by using a wiring configuration without increasing the wiring area. Attached Figure Description

[0006] Various embodiments of the invention will be best understood after reading the following description and the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0007] Figure 1 This is a top view schematic diagram of the circuit system in some embodiments of the present invention.

[0008] Figure 2 This is a side view of the circuit system in some embodiments of the present invention.

[0009] Figure 3 This is a side view of the circuit system in another embodiment of the present invention. Detailed Implementation

[0010] Figure 1 This is a top view schematic diagram of an embodiment of the circuit system 10 of the present invention. The circuit system 10 includes a first transceiver circuit 11, a second transceiver circuit 12, and a circuit structure 100 connecting the first transceiver circuit 11 and the second transceiver circuit 12.

[0011] The circuit structure 100 includes a circuit board 110, microstrip lines 121-122, and composite conductive lines 131-136. The microstrip lines 121-122 and composite conductive lines 131-136 are disposed on the circuit board 110 to connect the first transceiver circuit 11 and the second transceiver circuit 12. It should be understood that the number of microstrip lines 121-122 and composite conductive lines 131-136 is merely illustrative, and the invention is not limited thereto.

[0012] In some embodiments, the second transceiver circuit 12 is a memory circuit, and the first transceiver circuit 11 is a control circuit for controlling the memory circuit. In other embodiments, the first transceiver circuit 11 is a memory circuit, and the second transceiver circuit 12 is a control circuit for controlling the memory circuit. In other words, both the first transceiver circuit 11 and the second transceiver circuit 12 have bidirectional transmission and reception functions. For ease of understanding, this invention is described using the first transceiver circuit 11 to transmit signals to the second transceiver circuit 12, while the reverse operation is omitted.

[0013] The first transceiver circuit 11 includes pins P1 to P16. The second transceiver circuit 12 includes pins B1 to B8. The first transceiver circuit 11 and the second transceiver circuit 12 transmit signals through pins P1 to P8 and pins B1 to B8, respectively. Specifically, microstrip lines 121 to 122 couple pins P1 to P2 to pins B1 to B2, and composite conductive lines 131 to 136 couple pins P3 to P8 to pins B3 to B8, respectively. For ease of understanding, the traces connecting pins P9 to P16 are not shown in the figure. In other embodiments, the traces connecting pins P9 to P16 are connected to the second transceiver circuit 12 or other circuits.

[0014] Because the usable area of ​​the circuit board 110 is limited, the microstrip lines 121-122 and the composite conductive lines 131-136 are arranged with the shortest possible distance. However, the traces of the microstrip lines 121-122 and the composite conductive lines 131-136 will inevitably be of different lengths. When longer traces (especially for microstrip lines) exist on the circuit board, the crosstalk generated on them is also greater. Based on the above problems, the present invention provides a specially configured circuit structure 100 to reduce the impact of crosstalk, the details of which are described below.

[0015] like Figure 1 As shown in the top view, microstrip lines 121-122 are arranged in a straight line, while composite conductive lines 131-136 are arranged in a non-straight line. Microstrip lines 121-122 have the shortest length among the microstrip lines 121-122 and composite conductive lines 131-136. Specifically, pins P1-P16 of the first transceiver circuit 11 are ball grid arrays (BGAs). This BGA can be divided into a front row (FL) and a rear row (BL) relative to the second transceiver circuit 12. The front row (FL) includes pins P1-P8, and the rear row (BL) includes pins P9-P16. On the inner side of the front row (FL), the inner pins P1-P2 are closest to the second transceiver circuit 12. Therefore, they are directly connected to the second transceiver circuit 12 from pins P1-P2 using straight microstrip lines 121-122. Microstrip lines 121-122 are disposed on the surface of the circuit board 110 (i.e., shown in the diagram). Figure 2 (Conductive layer 111). In addition, there are outer pins P3 to P8 on the outside of the front row FL. In order to avoid overlapping, pins P3 to P8 can only be connected to the second transceiver circuit 12 by non-straight composite conductive lines 131 to 136.

[0016] In other embodiments, the microstrip lines 121-122 may not be arranged in a straight line, as long as the microstrip lines 121-122 still have the shortest length among the microstrip lines 121-122 and the composite conductive lines 131-136.

[0017] In some embodiments, for traces of the same length, the crosstalk produced by a stripline is lower than that produced by a microstrip line. Furthermore, because the composite conductive lines 131-136 are longer than the microstrip lines 121-122, the circuit structure 100 utilizes striplines to incorporate at least a portion of each of the composite conductive lines 131-136 to reduce the number of microstrip lines and thus lower crosstalk.

[0018] Please also refer to Figure 1 and Figure 2 . Figure 2 This is a side view of an embodiment of the circuit system 10 of the present invention. As can be seen from the side view of the circuit system 10, the circuit board 110 has a multilayer structure, including stacked conductive layers 111 to 114. The first transceiver circuit 11 and the second transceiver circuit 12 are disposed on the conductive layer 111 located on the surface. In some embodiments, the circuit board 110 includes only conductive layers 111 to 112. In some embodiments, the circuit board 110 includes more conductive layers. In some embodiments, the distance between conductive layer 111 and conductive layer 112 is equal to the distance between conductive layer 113 and conductive layer 114. In some embodiments, the distance between conductive layer 111 and conductive layer 112 is less than the distance between conductive layer 112 and conductive layer 113. For ease of understanding, Figure 2 Only composite conductive line 135 is shown; the other composite conductive lines and microstrip lines are omitted.

[0019] The composite conductive line 135 includes microstrip line 201, microstrip line 202, strip line 203, and vias 204 and 205. Microstrip line 201 and microstrip line 202 are disposed on conductive layer 111. Strip line 203 is disposed on conductive layer 112. Throughs 204 and 205 are disposed in circuit board 110 and penetrate conductive layer 111 to conductive layer 114.

[0020] Microstrip line 201 is used to couple pin P7 to path 204. Stripline 203 is used to couple pin B7 to path 205. Stripline 203 is coupled between path 204 and path 205, and is coupled to microstrip line 201 and microstrip line 202 via path 204 and path 205, respectively. In this configuration, composite conductive line 135 transmits the signal between pin P7 and pin B7 sequentially through microstrip line 201, path 204, stripline 203, path 205, and microstrip line 202.

[0021] Conductive layer 111 has a ground pad 111g, and conductive layer 112 has a ground pad 112g. In a top view, stripline 203 overlaps with a portion of ground pad 111g, and microstrip lines 201 and 202 overlap with a portion of ground pad 112g.

[0022] Based on a similar configuration, composite conductive lines 131-134 and 136 also include microstrip line 201, microstrip line 202, strip line 203, path 204 and path 205, respectively. Microstrip line 201 and microstrip line 202 also overlap with a portion of ground pad 112g, and strip line 203 also overlaps with a portion of ground pad 111g.

[0023] The circuit structure 100 also includes grounding paths VG1-VG2 penetrating the conductive layers 111-114. Grounding paths VG1-VG2 are used to couple ground pad 111g to ground pad 112g, such that ground pad 111g and ground pad 112g collectively form ground shielding for the composite conductive lines 131-136. In some embodiments, the conductive layer 113 includes a ground pad 113g, wherein grounding paths VG1-VG2 are further used to couple ground pad 111g and ground pad 112g to ground pad 113g, such that ground pad 111g, ground pad 112g, and ground pad 113g collectively form ground shielding for the composite conductive lines 131-136. In a further embodiment, the conductive layer 114 includes a ground pad 114g, wherein grounding paths VG1 to VG2 are also used to couple ground pads 111g, 112g, 113g, and 114g, such that ground pads 111g, 112g, 113g, and 114g collectively form a ground shield for the composite conductive lines 131 to 136. In some embodiments, the circuit structure 100 further includes other grounding paths, and the invention is not limited to the number of grounding paths. For example, other grounding paths are disposed between the paths 205 of the composite conductive lines 134 and 136.

[0024] In some embodiments, grounding paths VG1 to VG2 are used to reduce coupling interference between adjacent paths 204 and / or path 205. For example Figure 1 As shown, the grounding path VG1 is disposed between the path 204 of the composite conductive line 135 and the path 204 of the composite conductive line 133 to reduce the coupling interference between the path 204 of the composite conductive line 135 and the path 204 of the composite conductive line 133.

[0025] In some prior art, the paths are densely packed, resulting in significant coupling interference between them. Additional grounding paths are typically placed between the paths to reduce this interference. However, due to the dense path arrangement, it is difficult to place additional grounding paths within them unless a larger wiring area is used. Compared to prior art, this invention chooses to place grounding paths VG1-VG2 between paths 204 and / or 205 of composite conductive lines 131-136. Because composite conductive lines 131-136 are coupled to the outer pins P3-P6 of the ball grid array, compared to microstrip lines 121-122 connecting the inner pins P1-P2, composite conductive lines 131-136 have more open wiring pads available and are easier to set up with additional grounding paths VG1-VG2. With the configuration of this invention, even with grounding paths VG1-VG2, composite conductive lines 131-136 do not require additional wiring area.

[0026] refer to Figure 3 . Figure 3 This is a side view of an embodiment of the circuit system 10 in another embodiment of the present invention. Figure 3 The composite conductive wire 135 includes microstrip lines 201, 202, path 204, and path 205. Figure 2 The embodiment is the same, except that the strip 203 is disposed on the conductive layer 113. The conductive layer 114 includes a ground pad 114g. Figure 3 In the top view, the strip 203 overlaps with a portion of the ground pads 112g and 114g. Grounding paths VG1 to VG2 are used to couple the ground pads 112g, 113g, and 114g, such that the ground pads 112g, 113g, and 114g together form a grounding shield for the composite conductor 135.

[0027] It should be understood that Figure 3 Taking composite conductive wire 135 as an example only, the present invention is not limited thereto. Any of composite conductive wires 131 to 136 can Figure 3 The implementation example is used to set it up.

[0028] In some embodiments, the circuit structure 100 includes composite conductive lines 137-138. Composite conductive lines 137-138 are respectively coupled to the outer pins P15-P16 of the rear row of the ball grid array of the first transceiver circuit 11. In some embodiments, composite conductive lines 137-138 are configured to... Figure 2 and / or Figure 3 The implementation example is used to set it up.

[0029] The foregoing description briefly outlines the features of certain embodiments of the present invention, enabling those skilled in the art to more fully understand the various implementations of the invention. Those skilled in the art will readily recognize that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent implementations remain within the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

[0030] Explanation of reference numerals in the attached figures:

[0031] 10: Circuit System

[0032] 11: First transceiver circuit

[0033] 12: Second transceiver circuit

[0034] 100: Circuit Structure

[0035] 110: Circuit board

[0036] 121: Microstrip line

[0037] 122: Microstrip line

[0038] 131: Composite conductive wire

[0039] 132: Composite conductive wire

[0040] 133: Composite conductive wire

[0041] 134: Composite conductive wire

[0042] 135: Composite conductive wire

[0043] 136: Composite conductive wire

[0044] 201: Microstrip Line

[0045] 202: Microstrip line

[0046] 203: With wire

[0047] 204: Passage

[0048] 205: Passage

[0049] VG1: Grounding path

[0050] VG2: Grounding path

[0051] FL: Front row

[0052] BL: Back row

[0053] P1: Pin

[0054] P2: Pin

[0055] P3: Pin

[0056] P4: Pin

[0057] P5: Pin

[0058] P6: Pin

[0059] P7: Pin

[0060] P8: Pin

[0061] P9: Pin

[0062] P10: Pin

[0063] P11: Pin

[0064] P12: Pin

[0065] P13: Pin

[0066] P14: Pin

[0067] P15: Pin

[0068] P16: Pin

[0069] B1: Pin

[0070] B2: Pin

[0071] B3: Pin

[0072] B4: Pin

[0073] B5: Pin

[0074] B6: Pin

[0075] B7: Pin

[0076] B8: Pin

[0077] 111: Conductive layer

[0078] 112: Conductive layer

[0079] 113: Conductive layer

[0080] 114: Conductive layer

[0081] 111g: Grounding pad

[0082] 112g: Grounding pad

[0083] 113g: Grounding pad

[0084] 114g: Grounding pad

Claims

1. A circuit structure for connecting a first transceiver circuit and a second transceiver circuit, comprising: A circuit board includes a first conductive layer and a second conductive layer stacked together, wherein the first transceiver circuit and the second transceiver circuit are disposed on the first conductive layer; A first microstrip line is disposed on the first conductive layer to couple the first pin of the first transceiver circuit to the second pin of the second transceiver circuit. The second microstrip line is disposed on the first conductive layer and coupled to the third pin of the first transceiver circuit; The third microstrip line is disposed on the first conductive layer and coupled to the fourth pin of the second transceiver circuit; The first strip is disposed on the second conductive layer; A first path extends through the first conductive layer and the second conductive layer to couple the second microstrip line to the first strip line; and A second path, penetrating both the first and second conductive layers, is used to couple the third microstrip line to the first microstrip line. The first pin is the inner pin of the front row of the ball grid array of the first transceiver circuit, and the third pin is the outer pin of the front row of the ball grid array of the first transceiver circuit.

2. The circuit structure as described in claim 1, wherein the circuit board further includes a third conductive layer and a fourth conductive layer, wherein the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are sequentially stacked, wherein the distance between the first conductive layer and the second conductive layer is less than the distance between the second conductive layer and the third conductive layer.

3. The circuit structure as described in claim 2, wherein the distance between the first conductive layer and the second conductive layer is equal to the distance between the third conductive layer and the fourth conductive layer.

4. The circuit structure as described in claim 2, further comprising: The fourth microstrip line is disposed on the first conductive layer; The fifth microstrip line is disposed on the first conductive layer; The second strip is disposed on the third conductive layer; A third path, passing through the circuit board, is used to couple the fourth microstrip line to the second microstrip line; and The fourth path, passing through the circuit board, is used to couple the fifth microstrip line to the second microstrip line.

5. The circuit structure as described in claim 4, wherein the fourth microstrip line is coupled to the fifth pin of the first transceiver circuit, and the fifth microstrip line is coupled to the sixth pin of the second transceiver circuit.

6. The circuit structure as described in claim 5, wherein the fifth pin is an outer pin of the front row of the ball grid array of the first transceiver circuit.

7. The circuit structure as described in claim 5, wherein the fifth pin is an outer pin of the rear row of the ball grid array of the first transceiver circuit.

8. The circuit structure of claim 1, wherein the first conductive layer includes a first ground pad, and the second conductive layer includes a second ground pad, wherein the first microstrip line overlaps a portion of the first ground pad in a top view, and the second microstrip line overlaps a portion of the second ground pad in the top view.

9. The circuit structure as described in claim 8, further comprising: The fifth path runs through the circuit board and is used to couple the first ground pad to the second ground pad.

10. A circuit structure connecting a control circuit and a memory circuit, comprising: A circuit board includes a first conductive layer and a second conductive layer stacked together, wherein the control circuit and the memory circuit are disposed on the first conductive layer; Multiple first microstrip lines are disposed on the first conductive layer, and each first pin of the control circuit is coupled to a multiple second pin of the memory circuit. and Multiple first composite conductive lines are respectively coupled to multiple third pins of the control circuit to multiple fourth pins of the memory circuit, wherein each of the multiple first composite conductive lines is disposed on the first conductive layer and the second conductive layer. The plurality of first pins are the inner pins of the front row of the ball grid array of the control circuit, and the plurality of third pins are the outer pins of the front row of the ball grid array of the control circuit.

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