Semiconductor structure and method for manufacturing the same

Abstract

The present application provides a semiconductor structure and a preparation method thereof, which relates to the field of semiconductor technology. The semiconductor structure includes a substrate and a first conductive layer, wherein the substrate has a plurality of first grooves extending along a first direction and a plurality of second grooves extending along a second direction, and a plurality of active pillars are included between the first grooves and the second grooves, wherein the first direction and the second direction intersect, and the first conductive layer is located on a portion of the sidewall of the active pillar along the first direction. The present application increases the size of the active pillar in the first direction by arranging the first conductive layer on a portion of the sidewall of the active pillar along the first direction, thereby increasing the area of ​​the active pillar, thereby reducing the contact resistance between the capacitor contact formed subsequently on the active pillar, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] A dynamic random access memory usually includes multiple repeated storage units, each of which includes a transistor and a capacitor, wherein the source or drain of the transistor is connected to the capacitor through a capacitor contact to write data information into the capacitor or read data information from the capacitor. However, there is a large contact resistance between the source or drain of the transistor and the capacitor contact, which reduces the performance of the semiconductor structure. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for preparing the same, which are used to reduce the contact resistance between a transistor and a capacitor contact, thereby improving the performance of the semiconductor structure.

[0005] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] A first aspect of an embodiment of the present application provides a semiconductor structure, comprising:

[0007] A substrate, wherein the substrate has a plurality of first grooves extending along a first direction and a plurality of second grooves extending along a second direction, wherein a plurality of active pillars are provided between the first grooves and the second grooves, wherein the first direction and the second direction intersect;

[0008] A first conductive layer is located on a portion of a sidewall of the active pillar along the first direction.

[0009] In some embodiments, the second trench includes a first isolation layer and a gap.

[0010] In some embodiments, the void is located below the first conductive layer.

[0011] In some embodiments, the gap is located between the first conductive layers.

[0012] In some embodiments, the second trench includes a first sub-trench and a second sub-trench, and the first sub-trench is located above the second sub-trench and communicates with the second sub-trench.

[0013] In some embodiments, a cross-sectional area of ​​the first sub-groove is greater than or equal to a cross-sectional area of ​​the second sub-groove.

[0014] In some embodiments, the first conductive layer is located on a sidewall of the active pillar in the first sub-trench.

[0015] In some embodiments, a bit line structure is disposed below a bottom of the first trench, and the bit line structure extends along the first direction.

[0016] In some embodiments, a sidewall of the active pillar in the first trench includes a first dielectric layer and a second conductive layer.

[0017] In some embodiments, in a cross section in a first direction, the second conductive layer is located above the first isolation layer in the second trench.

[0018] In some embodiments, a second isolation layer is included. In a first direction cross section, the second isolation layer is located above the second conductive layer in the second trench; in a second direction cross section, the second isolation layer is located between side walls of adjacent active pillars in the first trench.

[0019] In some embodiments, a depth of the first trench is less than a depth of the second trench.

[0020] A second aspect of an embodiment of the present application provides a semiconductor structure, including:

[0021] providing a substrate;

[0022] forming a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction in the substrate, wherein a plurality of active pillars are included between the first trenches and the second trenches, wherein the first direction intersects with the second direction;

[0023] A first conductive layer is formed on a portion of the sidewall of the active pillar along the first direction.

[0024] In some embodiments, in a cross section in the first direction, after a third isolation layer is formed at the bottom of the second trench, an initial first conductive layer is deposited on the second trench and the third isolation layer, a portion of the initial first conductive layer is removed, and the initial first conductive layer located on the side wall of the active pillar located in the second trench is retained to form a first conductive layer.

[0025] In some embodiments, the second groove includes a first sub-groove and a second sub-groove, a plurality of the first sub-grooves extending along the second direction are formed in the substrate, the second sub-groove is formed at the bottom of the first sub-groove, and the first sub-groove is connected to the second sub-groove.

[0026] In some embodiments, a cross-sectional area of ​​the first sub-trench is greater than or equal to a cross-sectional area of ​​the second sub-trench; and a first isolation layer and a gap are formed in the second trench.

[0027] In some embodiments, a first initial dielectric layer is deposited in the first trench, the first initial dielectric layer at the bottom of the first trench is removed, and the first initial dielectric layer on the sidewall of the first trench is retained to form a first dielectric layer, the bottom of the first trench is doped, and a bit line structure is formed below the bottom of the first trench, and the bit line structure extends along the first direction.

[0028] In some embodiments, a second conductive layer is formed on a sidewall of the active pillar located in the first trench, and in a cross section in the first direction, the second conductive layer is located above the first isolation layer in the second trench.

[0029] In some embodiments, in a cross section in the first direction, the second isolation layer is formed above the second conductive layer in the second trench; in a cross section in the second direction, the second isolation layer is formed between side walls of adjacent active pillars in the first trench.

[0030] In the semiconductor structure and preparation method thereof provided in the embodiments of the present application, a first conductive layer is arranged on a portion of the side wall of the active column along the first direction, thereby increasing the size of the active column in the first direction, thereby increasing the area of ​​the active column, thereby reducing the contact resistance between the capacitor contact subsequently formed on the active column, and improving the performance of the semiconductor structure.

[0031] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A top view of a semiconductor structure provided in an embodiment of the present application;

[0034] Figure 2 for Figure 1Sectional view along the A-A' direction;

[0035] Figure 3 for Figure 1 Cross-section along the B-B' direction;

[0036] Figure 4 A process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0037] Figure 5 A schematic cross-sectional view in the AA' direction after forming a first sub-trench in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0038] Figure 6 A schematic cross-sectional view along the AA' direction after forming a second sub-trench in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0039] Figure 7 A schematic cross-sectional view along the AA' direction after forming a third initial isolation layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 8 A schematic cross-sectional view along the AA' direction after a third isolation layer is formed in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0041] Fig. 9 A schematic cross-sectional view along the AA' direction after forming a first initial conductive layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0042] Fig.10 A schematic cross-sectional view along the AA' direction after forming a first conductive layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0043] Fig.11 A schematic cross-sectional view along the AA' direction after the third isolation layer is removed in the method for preparing the semiconductor structure provided in an embodiment of the present application;

[0044] Fig.12 A schematic cross-sectional view along the AA' direction after forming a first sub-isolation layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0045] Fig.13 A schematic cross-sectional view along the AA' direction after an insulating layer is formed in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0046] Fig.14 A schematic cross-sectional view along the AA' direction after forming a second sub-isolation layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0047] Fig.15 A schematic cross-sectional view in the BB' direction after forming a first trench in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0048] Fig.16 A schematic cross-sectional view in the BB' direction after forming a first initial dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0049] Fig.17 A schematic cross-sectional view in the BB' direction after forming the first dielectric layer in the method for preparing the semiconductor structure provided in an embodiment of the present application

[0050] Fig.18 It is a schematic cross-sectional view along the BB' direction after a bit line structure is formed in the method for preparing a semiconductor structure provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 10: substrate; 11: first trench; 12: second trench; 13: active pillar;

[0053] 20: first conductive layer; 21: first initial conductive layer;

[0054] 30: first isolation layer; 31: gap; 32: first sub-isolation layer; 33: second sub-isolation layer; 34: insulation layer;

[0055] 40: bit line structure;

[0056] 50: first dielectric layer; 51: first initial dielectric layer;

[0057] 60: second conductive layer;

[0058] 70: second isolation layer;

[0059] 80: third isolation layer; 81: third initial isolation layer; 82: third trench; 83: fourth trench. DETAILED DESCRIPTION

[0060] In an embodiment of the present application, a first conductive layer is provided on a portion of the side wall of the active column along the first direction, and the size of the active column in the first direction is increased to increase the area of ​​the active column, thereby reducing the contact resistance between the capacitor contact subsequently formed on the active column and improving the performance of the semiconductor structure.

[0061] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.

[0062] The present embodiment does not limit the semiconductor structure. The semiconductor structure is a dynamic random access memory (DRAM) as an example for description below, but the present embodiment is not limited to this. The semiconductor structure in the present embodiment can also be other structures. Figure 1-Figure 18 A detailed introduction to semiconductor structures and their preparation methods is given.

[0063] like Figures 1 to 3 As shown, the semiconductor structure provided by the embodiment of the present application includes a substrate 10 and a first conductive layer 20 .

[0064] The substrate 10 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.

[0065] like Figure 1 As shown, a substrate 10 has a plurality of first trenches 11 extending along a first direction and a plurality of second trenches 12 extending along a second direction, and a plurality of active pillars 13 are included between the first trenches 11 and the second trenches 12, wherein the first direction intersects the second direction.

[0066] It should be noted that the first direction is Figure 1 The Y direction shown in Figure 1 The X direction shown in .

[0067] A plurality of first grooves 11 are arranged at intervals along the second direction, and a plurality of second grooves 12 are arranged at intervals along the first direction, so as to separate the substrate 10 into a plurality of active pillars 13 arranged at intervals. In this embodiment, the first grooves 11 can be understood as follows: Figure 1 The area between the two transverse dotted lines in FIG. 1 , the second groove 12 can be understood as follows Figure 1 The area between the two vertical dashed lines.

[0068] The depth of the first groove 11 may be the same as or different from the depth of the second groove 12 . Exemplarily, the depth of the first groove 11 is smaller than the depth of the second groove 12 .

[0069] Continue to refer Figure 1 and Figure 2The first conductive layer 20 is located on a portion of the sidewall of the active pillar 13 along the first direction, that is, the first conductive layer 20 is located on a portion of the sidewall of the active pillar 13 facing the second trench 12. Figure 1 Taking the illustrated orientation as an example, the first conductive layer 20 is disposed on the front sidewall and the rear sidewall of each active pillar 13 , wherein the material of the first conductive layer 20 includes polysilicon.

[0070] In this embodiment, by forming a first conductive layer 20 on a portion of the side wall of the active pillar 13 facing the first groove 11, the width of the active pillar along the first direction can be increased, thereby increasing the cross-sectional area of ​​the top of the active pillar 13. In this way, the contact area between the capacitor contact and the subsequently formed top surface of the active pillar 13 is reduced, thereby reducing the contact resistance between the active pillar 13 and the capacitor contact and improving the performance of the semiconductor structure.

[0071] In addition, the first conductive layer 20 is located on a portion of the side wall of the first active pillar 13 along the first direction, that is, there is a gap between the bottom surface of the first conductive layer 20 facing the substrate 10 and the bottom surface of the second groove 12. Such a setting can prevent the subsequently formed bit line structure from being electrically connected to the top of the active pillar 13, thereby improving the yield of the semiconductor structure.

[0072] In some embodiments, continue to refer to Figure 2 The second trench 12 includes a first isolation layer 30 and a gap 31, that is, the first isolation layer 30 is arranged in the second trench 12, and the first isolation layer 30 has a gap 31. Such a setting can reduce the dielectric constant of the first isolation layer 30, thereby reducing the parasitic capacitance between adjacent bit line structures 40, thereby improving the performance of the semiconductor structure.

[0073] In this embodiment, the shape of the gap 31 can be regular or irregular, and its shape is affected by the shape of the second groove 12 and the process of forming the first isolation layer 30; in addition, the gap 31 in the same second groove 12 can be one or more, and this embodiment does not make any specific limitations here.

[0074] For example, Figure 2 Taking the orientation shown as an example, with the section perpendicular to the substrate 10 as the longitudinal section, the longitudinal section of the second sub-groove 122 can be in the shape of a water drop, which can be conducive to forming a gap 31, thereby reducing the parasitic capacitance between adjacent bit line structures 40 and preventing electrical connection between adjacent bit line structures 40.

[0075] In addition, the top surface of the first isolation layer 30 is lower than the top surface of the active pillar 13 , so that a space is formed between the first isolation layer 30 and the top surface of the active pillar 13 , so as to form a word line structure in the space.

[0076] In some embodiments, the gap 31 can be located below the first conductive layer 20 or between the first conductive layers 20. When the gap 31 is located below the first conductive layer 20, it can be understood that the first isolation layer 30 has a gap 31 in the portion between the bottom of the first conductive layer 20 and the bottom of the second trench 12, and the gap 31 is at least partially located between adjacent bit line structures 40 to ensure that the parasitic capacitance between adjacent bit line structures 40 can be reduced.

[0077] Correspondingly, when the gap 31 is located between the first conductive layers 20, it can be understood that the first isolation layer 30 has a gap 31 in the portion between the bottom of the first conductive layer 20 and the top of the first conductive layer 20, and the gap 31 is at least partially located between adjacent bit line structures 40 to ensure that the parasitic capacitance between adjacent bit line structures 40 can be reduced.

[0078] In some embodiments, continue to refer to Figure 2 The second groove 12 includes a first sub-groove 121 and a second sub-groove 122 . The first sub-groove 121 is located above the second sub-groove 122 and communicates with the second sub-groove 122 .

[0079] by Figure 2 Taking the orientation shown as an example, from top to bottom, the area between the first dotted line and the second dotted line in the second groove 12 is the first sub-groove 121, and the area between the second dotted line and the third dotted line in the second groove 12 is the second sub-groove 122.

[0080] The cross-sectional area of ​​the first sub-groove 121 is greater than or equal to the cross-sectional area of ​​the second sub-groove 122 , wherein the cross-sectional area in this embodiment refers to the cross-sectional area parallel to the substrate 10 .

[0081] In this embodiment, the second groove 12 has a structure that is larger at the top and smaller at the bottom, so that

[0082] When the first isolation layer 30 is formed in the trench 12 , affected by the cross-sectional areas of the first sub-trench 121 and the second sub-trench 122 , the smaller the cross-sectional area, the easier it is to form the void 31 in the first isolation layer 30 .

[0083] Taking the section perpendicular to the substrate 10 as the longitudinal section, the longitudinal section of the first sub-groove 121 may be rectangular, and the longitudinal section of the second sub-groove 122 may be regular or irregular. For example, the width of the second sub-groove 122 gradually decreases from one end close to the first sub-groove 121 to the end away from the first sub-groove 121, so that Figure 2Taking the orientation shown as an example, the width of the second sub-groove 122 gradually decreases from top to bottom, so that the second sub-groove 122 presents a structure that is larger at the top and smaller at the bottom. For example, the longitudinal cross-section of the second sub-groove 122 is V-shaped. In this way, the closer to the bottom of the substrate 10, the smaller the width of the second sub-groove 122, and the easier it is to form a gap 31 in the second sub-groove 122, so as to reduce the dielectric constant of the first isolation layer 30 located in the second sub-groove 122.

[0084] It should be noted that the longitudinal cross-sectional shape of the second sub-groove 122 is not limited to the above-mentioned V-shape, and the cross-sectional shape of the second sub-groove 122 can also be a trapezoidal structure with a larger upper portion and a smaller lower portion, so that a gap 31 can also be formed in the second groove 12 .

[0085] In some embodiments, the first conductive layer 20 is located on the side wall of the active pillar 13 in the first sub-groove 121. Along the direction perpendicular to the substrate 10, the active pillar 13 includes a channel region and a source region and a drain region located on both sides of the channel region, wherein the drain region is located at the bottom of the active pillar 13 for connecting to the bit line structure, the channel region is located in the middle of the active pillar 13 for connecting to the word line, and the source region is located at the top of the active pillar 13 for contact connection with the capacitor to achieve electrical connection between the capacitor and the source region.

[0086] Based on this, this embodiment sets the first conductive layer 20 on the side wall of the active pillar 13 in the first sub-groove 121. Such a setting can, on the one hand, increase the area of ​​the source region of the active pillar 13, and on the other hand, compared with the technical solution in which the first conductive layer 20 is entirely set on the side wall of the active pillar 13 in the second groove 12, it can reduce the production cost of the first conductive layer 20.

[0087] In some embodiments, continue to refer to Figure 2 and Figure 3 A bit line structure 40 is disposed below the bottom of the first trench 11 , and the bit line structure 40 extends along a first direction.

[0088] The bit line structure 40 is used to connect to the drain of the active pillar 13 , and data in the capacitor is read or written into the capacitor through the bit line structure 40 , wherein the material of the bit line structure 40 may include cobalt silicide or silicon germanium.

[0089] In some embodiments, Figure 3 As shown, the active pillar 13 includes a first dielectric layer 50 and a second conductive layer 60 on the side wall in the first trench 11. The first dielectric layer 50 and the second conductive layer 60 are stacked on the side wall of the active pillar 13 in the first trench 11, and the first dielectric layer 50 is connected to the side wall of the active pillar 13 in the first trench 11. The first dielectric layer 50 serves as a gate oxide layer of a transistor to be formed subsequently, and its material may be silicon oxide or other materials with a high dielectric constant.

[0090] In the second direction cross section, the second conductive layer 60 is arranged on the first dielectric layer 50, and the projection of the second conductive layer 60 on the active pillar 13 at least covers the channel region of the active pillar 13; in the first direction cross section, the second conductive layer 60 is located above the first isolation layer 30 of the second groove 12, and the top surface of the second conductive layer 60 is fixed on the top surface of the active pillar 13, so that the second conductive layer 60 constitutes a word line extending along the second direction, and the word line is used to connect all active pillars located in the same second direction, and a voltage is applied to the channel region of the active pillar 13 through the word line to control the connection or disconnection between the source region and the drain region of the active pillar 13, wherein the material of the second conductive layer 60 may include metal tungsten.

[0091] In some embodiments, the semiconductor structure includes a second isolation layer 70, such as Figure 2 As shown, in the first direction cross section, the second isolation layer 70 is located above the second conductive layer 60 in the second trench 12; Figure 3 As shown, in the second direction cross section, the second isolation layer 70 is located between the side walls of adjacent active pillars 13 in the first trench 11. Such a setting can achieve an insulation setting between adjacent second conductive layers 60, wherein the second isolation layer 70 can include insulating materials such as silicon oxide or silicon nitride.

[0092] like Figure 4 As shown, the embodiment of the present application also provides a method for preparing a semiconductor structure, comprising the following steps:

[0093] Step S100: providing a substrate.

[0094] The substrate 10 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.

[0095] Step S200: forming a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction in the substrate, wherein a plurality of active pillars are included between the first trenches and the second trenches, wherein the first direction intersects with the second direction, and the structure thereof is as follows: Figure 5 and Fig.15 shown.

[0096] It should be noted that in this embodiment, there is no limitation on the order of forming the first groove 11 and the second groove 12. The process of forming the first groove 11 and the second groove 12 can be to first complete the etching of one of the first groove 11 and the second groove 12, and then complete the etching of the other; it can also be any other process that can form the first groove 11 and the second groove 12.

[0097] For the convenience of description, this embodiment takes the process of first forming the second trench 12 as an example to describe the preparation process of the semiconductor structure.

[0098] Illustratively, a first photoresist layer can be formed on the substrate 10 by coating, and then the first photoresist layer can be patterned by exposure, development or etching to form a first mask pattern in the first photoresist layer, wherein the first mask pattern includes a plurality of first mask protrusions and first mask openings located between adjacent first mask protrusions, wherein the plurality of first mask protrusions are spaced apart along a first direction, and each first mask protrusion extends along a second direction, and the first direction and the second direction are perpendicular to each other.

[0099] like Figure 5 As shown, after the first mask opening is formed, an etching solution or an etching gas can be used to remove a portion of the thickness of the substrate 10 exposed in the first mask opening to form a plurality of first sub-grooves 121 in the substrate 10, wherein the plurality of first sub-grooves 121 are spaced apart along the first direction, and each first sub-groove 121 extends along the second direction.

[0100] like Figure 6 As shown, after the first sub-groove 121 is formed, the first sub-groove 121 is further etched so that a second sub-groove 122 is formed at the bottom of the first sub-groove 121. That is, along the vertical direction, a portion of the substrate 10 exposed at the bottom of the first sub-groove 121 is removed to form the second sub-groove 122. The second sub-groove 122 is connected to the first sub-groove 121 to form the second groove 12, wherein the first sub-groove 121 is Figure 6 The area between the dotted line and the top of the second trench 12, the second sub-trench 122 is Figure 6 The area between the dotted line and the bottom of the second trench 12 .

[0101] The cross-sectional area of ​​the first sub-groove 121 is greater than or equal to the cross-sectional area of ​​the second sub-groove 122, so that the second groove 12 presents a structure that is larger at the top and smaller at the bottom. In this way, when the first isolation layer 30 is subsequently formed in the second groove 12, it is easier to form a gap 31 in the first isolation layer 30 due to the influence of the cross-sectional areas of the first sub-groove 121 and the second sub-groove 122.

[0102] Step S300: forming a first conductive layer on a portion of the sidewall of the active pillar along a first direction.

[0103] like Figure 7As shown, in the cross section in the first direction, a third initial isolation layer 81 is formed in the second groove 12. For example, the third initial isolation layer 81 can be formed in the second groove 12 by an atomic layer deposition process. The third initial isolation layer 81 encloses the third groove 82 in the second groove 12, and the third initial isolation layer 81 also covers the top surface of the substrate 10.

[0104] like Figure 8 As shown, the third groove 82 can be etched to remove the third initial isolation layer 81 located on the top surface of the substrate 10 and part of the second groove 12. The retained third initial isolation layer 81 constitutes the third isolation layer 80 at the bottom of the second groove 12, and the third isolation layer 80 and the second groove are enclosed to form a fourth groove 83.

[0105] In this embodiment, the material of the third isolation layer 80 includes silicon oxide. By forming the third isolation layer 80 at the bottom of the second trench 12, such a configuration can ensure that the first conductive layer 20 is only formed on the upper part of the second trench 12, that is, it can ensure that the first conductive layer 20 at least covers part of the side wall of the first sub-trench 121.

[0106] like Fig. 9 As shown, a first initial conductive layer 21 is formed on the fourth groove 83 and the substrate 10 by a deposition process, that is, a first initial conductive layer 21 is formed on a portion of the sidewall of the second groove 12 and the top surface of the third isolation layer 80, and the first initial conductive layer 21 extends outside the second groove 12 and covers the top surface of the substrate 10.

[0107] The deposition process may include any one of chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) and plasma enhanced ALD (PEALD).

[0108] like Fig.10 As shown, the first initial conductive layer 21 located on the top surface of the third isolation layer 80 and the first initial conductive layer 21 located on the top surface of the substrate 10 are removed by using an etching gas or an etching liquid, and the first initial conductive layer 21 located on the side wall of the active column 13 of the second trench 12 is retained to form a first conductive layer 20. In other words, the first initial conductive layer 21 located on the side wall of the fourth trench 83 is retained to form a first conductive layer 20.

[0109] In this embodiment, part of the first initial conductive layer 21 located on the inner wall of the first sub-trench 121 may be retained, or the entire first initial conductive layer 21 located on the inner wall of the first sub-trench 121 may be retained, wherein the material of the first conductive layer 20 includes polysilicon.

[0110] After the first conductive layer 20 is formed, Fig.11 As shown, the third isolation layer 80 is removed.

[0111] In this embodiment, by forming a first conductive layer 20 on the partial side wall of the active pillar 13 located in the second trench 12, the cross-sectional area of ​​the top of the active pillar 13 can be increased, and the contact area between the active pillar and the capacitor can be increased, thereby reducing the contact resistance between the active pillar and the capacitor contact, thereby improving the performance of the semiconductor structure.

[0112] In some embodiments, after the first conductive layer is formed, a first isolation layer 30 and a gap 31 are formed in the second trench 12 , wherein the first isolation layer 30 includes a first sub-isolation layer 32 and a second sub-isolation layer 33 .

[0113] Exemplarily, the preparation process of the first isolation layer 30 is divided into two steps, such as Fig.12 As shown, firstly, a first sub-isolation layer 32 is formed in the second sub-trench 122 by a thermal oxidation process, and the first sub-isolation layer 32 does not completely fill the second sub-trench 122 .

[0114] Afterwards, if Fig.13 As shown, an insulating material with poor filling ability is deposited in the first sub-groove 121 to form an insulating layer 34, and the insulating layer 34 extends outside the first sub-groove 121 and covers the top surface of the substrate 10. In this embodiment, the insulating layer 34 does not fill the area enclosed by the first sub-isolation layer 32 and the first conductive layer 20, so that the insulating layer 34 and the first sub-isolation layer 32 enclose a gap 31 in the second groove 12.

[0115] Afterwards, if Fig.14 As shown, a portion of the insulating layer 34 is removed to expose a portion of the second trench 12 , and the remaining insulating layer 34 forms a second sub-isolating layer 33 , which is connected to the first isolating layer 31 to form the first isolating layer 30 .

[0116] In this embodiment, a gap 31 is formed in the second groove 12, which can reduce the dielectric constant of the first isolation layer 30 on the one hand, and increase the insulation of the first isolation layer 30 on the other hand. In this way, when a bit line structure is subsequently formed in the substrate, the parasitic capacitance between adjacent bit line structures can be reduced, and electrical connection can be prevented between adjacent bit line structures.

[0117] In some embodiments, after the first isolation layer 30 is formed, the substrate 10 may be patterned to form a plurality of first grooves 11 in the substrate 10. Fig.15As shown, the depth of the first trench 11 is less than the depth of the second trench 12, and the plurality of first trenches 11 and the plurality of second trenches 12 separate the substrate into a plurality of initial active pillars, and then each initial active pillar is ion-doped by ion implantation technology to form an active pillar 13.

[0118] Exemplarily, first, the ion implantation energy and the type of implanted doping ions in the ion implantation technology can be controlled to form a drain region at the bottom of the initial active column, and then, the ion implantation energy and the type of implanted doping ions in the ion implantation technology can be controlled to form a channel region in the middle of the initial active column. Finally, the ion implantation energy and the type of implanted doping ions in the ion implantation technology can be controlled to form a source region at the top of the initial active column, wherein the type of doping ions in the drain region can be the same as the type of doping ions in the source region, for example, the doping ions can include N-type ions; and the type of doping ions in the channel region is different from the type of doping ions in the drain region, for example, the doping ions can include P-type ions.

[0119] It should be noted that the formation process of the first groove 11 may be the same as the formation process of the second groove 12 , and will not be further elaborated in this embodiment.

[0120] like Fig.16 As shown, after the first trench 11 is formed, a first initial dielectric layer 51 may be deposited in the first trench 11 by a deposition process. The first initial dielectric layer 51 is formed on the inner wall of the first trench 11 and extends outside the first trench 11 to cover the top surface of the active pillar 13 .

[0121] The deposition process includes but is not limited to atomic layer deposition (ALD) and plasma enhanced ALD (PEALD).

[0122] like Fig.17 As shown, the first initial dielectric layer 51 at the bottom of the first trench 11 and the first initial dielectric layer 51 on the top surface of the active pillar 13 are removed, and the first initial dielectric layer 51 on the sidewall of the first trench 11 is retained to form a first dielectric layer 50 .

[0123] In this step, the first dielectric layer 50 can be provided to protect the active pillar 13 to prevent damage to the active pillar during ion implantation, thereby improving the performance of the semiconductor structure.

[0124] Afterwards, if Fig.18As shown, the bottom of the first trench 11 is doped, and a bit line structure 40 is formed below the bottom of the first trench 11, and the bit line structure 40 extends along the first direction. Each bit line structure 40 is connected to a different active pillar. Those skilled in the art can set the width of the bit line structure by themselves, so that the bit line structure can connect two adjacent active pillars as much as possible and evenly, and the bit line structures are not connected to each other.

[0125] As an optional implementation of the bit line structure 40, metal germanium can be deposited into the first trench 11. Under certain reaction conditions, the germanium reacts with the silicon at the bottom of the active pillar 13 to form silicon germanium. In this way, the bottom of each active pillar 13 located in the same second direction can form a bit line structure 40.

[0126] As an optional implementation of the bit line structure 40, metal cobalt can be deposited at the bottom of the first trench 11. Under certain reaction conditions, the metal cobalt reacts with the silicon at the bottom of the active pillar 13 to form cobalt silicide. In this way, the bottoms of the active pillars 13 located in the same second direction can form a bit line structure 40.

[0127] In some embodiments, continue to refer to Figure 2 and Figure 3 After the bit line structure 40 is formed, a second conductive layer 60 is formed on the side wall of the active pillar 13 in the first trench. In the first direction cross section, the second conductive layer 60 is located above the first isolation layer 30 in the second trench 12. In the second direction cross section, the second conductive layer 60 is arranged on the side of the first dielectric layer 50 away from the active pillar 13.

[0128] In this way, the second conductive layer 60 constitutes a word line extending along the second direction, and the word line is used to connect all active pillars located in the same second direction. A voltage is applied to the channel region of the active pillar 13 through the word line to control the connection or disconnection between the source region and the drain region of the active pillar 13, wherein the material of the second conductive layer 60 may include metal tungsten.

[0129] It should be noted that in the present embodiment, there are multiple options for the process of forming the second conductive layer 60. For example, a second initial conductive layer filling the first groove 11 and the second groove 12 is formed in the first groove 11 and the second groove 12, and then, along the second direction, the second initial conductive layer located in the first groove 11 is removed, and the second initial conductive layer located on the inner wall of the first groove is retained to form the second conductive layer 60.

[0130] In some embodiments, continue to refer to Figure 2 and Figure 3In the cross section in the first direction, a second isolation layer 70 is formed above the second conductive layer 60 in the second trench; in the cross section in the second direction, a second isolation layer 70 is formed between the side walls of adjacent active pillars 13 in the first trench 11 .

[0131] In this step, a second isolation layer 70 may be formed in the first trench 11 and the second trench 12 by a deposition process, and the second isolation layer 70 may be used to achieve insulation between adjacent second conductive layers 60 .

[0132] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0133] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.

[0134] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a plurality of first grooves extending along a first direction and a plurality of second grooves extending along a second direction, wherein a plurality of active pillars are provided between the first grooves and the second grooves, wherein the first direction and the second direction intersect; The second groove includes a first sub-groove and a second sub-groove, the first sub-groove is located above the second sub-groove and communicates with the second sub-groove; a first conductive layer, wherein the first conductive layer is located on a sidewall of the active pillar in the first sub-trench, and the first conductive layer is in direct contact with the active pillar; The second trench includes a first isolation layer and a gap; a second conductive layer, the second conductive layer being located above the first isolation layer and between adjacent first conductive layers along the first direction; The bit line structure is located below the first trench and extends along a first direction, and each of the bit line structures is connected to different active pillars, and the first isolation layer and the gap are located between adjacent bit lines.

2. The semiconductor structure according to claim 1, characterized in that: The gap is located below the first conductive layer.

3. The semiconductor structure according to claim 1, characterized in that: The gap is located between the first conductive layers.

4. The semiconductor structure according to claim 1, characterized in that A cross-sectional area of ​​the first sub-groove is greater than or equal to a cross-sectional area of ​​the second sub-groove.

5. The semiconductor structure according to claim 1, characterized in that: A bit line structure is disposed below the bottom of the first trench, and the bit line structure extends along the first direction.

6. The semiconductor structure according to claim 5, characterized in that: The sidewall of the active pillar in the first trench includes a first dielectric layer and a second conductive layer.

7. The semiconductor structure according to claim 1, characterized in that: It comprises a second isolation layer. In a first direction cross section, the second isolation layer is located above the second conductive layer in the second trench; in a second direction cross section, the second isolation layer is located between side walls of adjacent active pillars in the first trench.

8. The semiconductor structure according to claim 1, characterized in that: The depth of the first trench is smaller than the depth of the second trench.

9. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction in the substrate, wherein a plurality of active pillars are included between the first trenches and the second trenches, wherein the first direction intersects with the second direction; The second groove includes a first sub-groove and a second sub-groove, a plurality of the first sub-grooves extending along the second direction are formed in the substrate, the second sub-groove is formed at the bottom of the first sub-groove, and the first sub-groove is connected to the second sub-groove; forming a first conductive layer on a sidewall of the active pillar in the first sub-trench, wherein the first conductive layer is in direct contact with the active pillar; forming a first isolation layer and a gap in the second trench; forming a second conductive layer on the sidewall of the active pillar located in the first trench, wherein in a cross section in the first direction, the second conductive layer is located above the first isolation layer in the second trench and between adjacent first conductive layers along the first direction; A bit line structure is formed below the first trench, the bit line structure extends along a first direction, and each of the bit line structures is connected to a different active pillar, and the first isolation layer and the gap are located between adjacent bit lines.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: In the first direction cross section, after the third isolation layer is formed at the bottom of the second trench, an initial first conductive layer is deposited on the second trench and the third isolation layer, a portion of the initial first conductive layer is removed, and the initial first conductive layer located on the side wall of the active column located in the second trench is retained to form a first conductive layer.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that: The cross-sectional area of ​​the first sub-groove is greater than or equal to the cross-sectional area of ​​the second sub-groove; and a first isolation layer and a gap are formed in the second groove.

12. The method for preparing a semiconductor structure according to claim 9, characterized in that: A first initial dielectric layer is deposited in the first trench, the first initial dielectric layer at the bottom of the first trench is removed, and the first initial dielectric layer on the sidewall of the first trench is retained to form a first dielectric layer, the bottom of the first trench is doped, and a bit line structure is formed below the bottom of the first trench, wherein the bit line structure extends along the first direction.

13. The method for preparing a semiconductor structure according to claim 9, characterized in that: In the cross section in the first direction, a second isolation layer is formed above the second conductive layer in the second trench; in the cross section in the second direction, the second isolation layer is formed between the side walls of adjacent active pillars in the first trench.

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