Dc-dc converter with adaptive zero tracking

Abstract

A DC-DC converter comprises an output terminal, a reference voltage source (303), an error amplifier (302) and a compensation circuit. The error amplifier (302) is coupled to the output terminal and the reference voltage source (303). The error amplifier (302) is configured to generate an error signal representing a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source (303). The compensation circuit is coupled to the error amplifier. The compensation circuit comprises a resistor (308), a capacitor (306) and a switch control circuit (301). The resistor (308) is coupled to the error amplifier (302). The capacitor (306) is coupled to the resistor. The switch control circuit (301) is configured to modulate a connection of the resistor (308) to the capacitor (306) based on a switching frequency of the DC-DC converter.

Description

Background Technology

[0001] A switch-mode power supply is an electronic circuit that converts an input direct current (DC) power supply voltage into one or more DC output voltages with an amplitude higher or lower than the input DC power supply voltage. A switch-mode power supply that generates an output voltage lower than the input voltage is called a buck or voltage-reducing converter. A switch-mode power supply that generates an output voltage higher than the input voltage is called a boost or voltage-increasing converter. The stability of a switch-mode power supply can be affected by the gain and phase shift introduced in the power supply's control loop. Compensation can be applied to switch-mode power supplies to counteract gain and phase shift. Summary of the Invention

[0002] In one example, the DC-DC converter includes an error amplifier and compensation circuitry. The error amplifier includes an output. The compensation circuitry includes a first resistor, a first switch, a second resistor, a second switch, and a capacitor. The first resistor includes a first terminal and a second terminal. The first terminal is coupled to the output of the error amplifier. The first switch includes a first terminal and a second terminal. The first terminal of the first switch is coupled to the second terminal of the first resistor. The second resistor includes a first terminal and a second terminal. The first terminal of the second resistor is coupled to the output of the error amplifier. The second switch includes a first terminal and a second terminal. The first terminal of the second switch is coupled to the second terminal of the second resistor. The second terminal of the second switch is coupled to the second terminal of the first switch. The capacitor includes a first terminal and a second terminal. The first terminal of the capacitor is coupled to the second terminal of the first switch. The second terminal of the capacitor is coupled to ground.

[0003] In another example, the DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and compensation circuitry. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representing the difference between the voltage at the output terminal and the reference voltage provided by the reference voltage source. Compensation circuitry is coupled to the error amplifier. The compensation circuitry includes a resistor, a capacitor, and switching control circuitry. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switching control circuitry is configured to modulate the resistor-capacitor connection based on the switching frequency of the DC-DC converter.

[0004] In a further example, an inverting buck-boost converter includes an output terminal, a high-side transistor, a low-side transistor, and a controller. The controller is coupled to the output terminal, the high-side transistor, and the low-side transistor. The controller includes a reference voltage source, an error amplifier, and compensation circuitry. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representing the difference between the voltage at the output terminal and a reference voltage provided by the reference voltage source. Compensation circuitry is coupled to the error amplifier. The compensation circuitry includes a first resistor, a capacitor, a first switch, a second resistor, a second switch, and switch control circuitry. The first resistor is coupled to the error amplifier. The capacitor is coupled to the first resistor. The first switch is configured to couple the first resistor to the capacitor. The second resistor is coupled to the error amplifier. The second switch is configured to couple the second resistor to the capacitor. The switch control circuitry is configured to modulate the first and second switches based on the switching frequencies of the high-side and low-side transistors. Attached Figure Description

[0005] Figure 1 This is a signal diagram in a DC-DC converter that presents pulse grouping in Pulse Frequency Mode (PFM) operation.

[0006] Figure 2 This is a block diagram of an example DC-DC converter that includes compensated zero-point tracking based on switching frequency.

[0007] Figure 3 This is a schematic diagram of an example compensation circuit that includes zero-point tracking compensation based on switching frequency.

[0008] Figure 4 yes Figure 3 Bode plot of an example compensation circuit.

[0009] Figure 5 It includes Figure 3 The signal diagram in a DC-DC converter is an example of a compensation circuit.

[0010] Figure 6 This shows the application to Figure 3 A graph showing how the duty cycle in the compensation circuit changes as the load decreases.

[0011] Figure 7 This is a schematic diagram of an example compensation circuit that includes zero-point tracking compensation based on switching frequency.

[0012] Figure 8 yes Figure 7 Bode plot of an example compensation circuit.

[0013] Figure 9 It includes Figure 7 The signal diagram in a DC-DC converter is an example of a compensation circuit.

[0014] Figures 10A-10C yes Figure 9 The chart shows the amplified signal. Detailed Implementation

[0015] Compensation circuits are used to stabilize the control loop in DC-DC converters and other feedback loop control circuits. The type of compensation circuit used (e.g., Type 1, Type 2, or Type 3) is selected based on various parameters of the controlled circuit (e.g., output filter component type and size, switching frequency, bandwidth, etc.). Type 2 compensation is widely used in DC-DC converters. For example, Type 2 compensation can be used in applications where the frequency of the zero point caused by the circuit's output capacitor and its equivalent series resistance is less than the closed-loop bandwidth of the control loop.

[0016] Under light load conditions, pulse-frequency mode (PFM) DC-DC converters based on voltage-controlled oscillators (VCOs) suffer from phase margin degradation due to switching frequency poles. Pulse-width modulation (PWM) based DC-DC converters implementing pulse-skip mode (PSM) operation exhibit similar phase margin degradation. When phase margin degradation leads to a negative phase margin, it results in instability in the pulse grouping pattern.

[0017] Figure 1 The diagram illustrates the signal in a DC-DC converter exhibiting pulse packetization during Pulse Frequency Mode (PFM) operation. In this example, the DC-DC converter is an inverting buck-boost converter with type 2 compensation. The load applied to the DC-DC converter decreases over time. Because the switching frequency of the DC-DC converter decreases as the load decreases, pulse packets or bursts occur during switching (see area 102). Some DC-DC converters attempt to avoid this behavior by using a dummy load to limit the switching frequency, which limits the converter's bandwidth and reduces efficiency under light loads.

[0018] The DC-DC converter described in this paper uses the converter switching frequency to track the zero point of a type 2 compensation circuit to maintain phase margin across the entire switching frequency range of the DC-DC converter. By maintaining phase margin, the DC-DC converter avoids pulse grouping at light loads.

[0019] Figure 2This is a block diagram of an example DC-DC converter 200 including compensated zero-point tracking based on switching frequency. The DC-DC converter 200 includes a high-side transistor 202, a low-side transistor 204, an inductor 206, an output capacitor 208, a voltage divider 210, and a controller 212. The DC-DC converter 200 is configured as an inverting buck-boost converter. Some examples of the DC-DC converter 200 can be configured as a buck converter, boost converter, buck-boost converter, or other types of DC-DC converters.

[0020] Controller 212 controls the switching of high-side transistor 202 and low-side transistor 204 to provide a selected output voltage (VOUT) at output 218. Voltage divider 210 is coupled to controller 212 to provide output voltage feedback 216 to controller 212. Controller 212 controls the switching of high-side transistor 202 and low-side transistor 204 based on the output voltage feedback 216 received from voltage divider 210. Controller 212 includes compensation circuitry 214 to stabilize the control of VOUT generation. Compensation circuitry 214 tracks the zero point of compensation circuitry 214 across the converter switching frequency to maintain phase margin across the entire switching frequency range of DC-DC converter 200.

[0021] Figure 3 This is a schematic level diagram of an example compensation circuit 300 including compensation zero-point tracking based on switching frequency. Compensation circuit 300 is an example of compensation circuit 214. Compensation circuit 300 includes an error amplifier 302, capacitors 304 and 306, resistors 308 and 310, switches 312 and 314, and switch control circuitry 301. Error amplifier 302 includes an input coupled to voltage divider 210 to receive output voltage feedback 216, and an input coupled to voltage reference circuit 303. Error amplifier 302 generates an error signal representing the difference between output voltage feedback 216 and a reference voltage received from voltage reference circuit 303.

[0022] Capacitor 304 is coupled to the output of error amplifier 302. Resistor 308 includes a first terminal coupled to the output of error amplifier 302 and a second terminal coupled to the first terminal of switch 312. The second terminal of switch 312 is coupled to the first terminal of capacitor 306. The second terminal of capacitor 306 is coupled to ground. Resistor 310 includes a first terminal coupled to the output of error amplifier 302 and a second terminal coupled to the first terminal of switch 314. The second terminal of switch 314 is coupled to the first terminal of capacitor 306. In some embodiments of compensation circuit 300, switches 312 and 314 may be implemented using field-effect transistors (FETs). The resistance of resistor 310 may be greater than the resistance of resistor 308 (e.g., 10 times greater).

[0023] Switch control circuit 301 controls the switching of switches 312 and 314 to change the resistance of the output of error amplifier 302 coupled to capacitor 306, and change the position of the zero point corresponding to that resistance. Switch control circuit 301 includes a phase output 301B coupled to the control terminal of switch 312 and a phase output 301C coupled to the control terminal of switch 314. Signal Φ1 (switch control signal) generated by switch control circuit 301 controls the switching of switch 312, and signal Φ2 (switch control signal) generated by switch control circuit 301 controls the switching of switch 314. Signals Φ1 and Φ2 can be complementary. Therefore, signal Φ2 can be inverted relative to signal Φ1 (the inverted version). Thus, when switch 314 is open, switch 312 is closed, and when switch 314 is closed, switch 312 is open, and switch control circuit 301 complementaryly couples resistors 308 and 310 to capacitor 306.

[0024] The switch control circuit 301 includes an input terminal 301A coupled to the control terminal of the high-side transistor 202 or the control terminal of the low-side transistor 204. The switch control circuit 301 includes a logic gate 328, an inverter 330, an inverter 332, and a delay circuit 305. A first input of logic gate 328 is coupled to the input terminal 301A, and a second input of logic gate 328 is coupled to the output of the delay circuit 305. Logic gate 328 combines the signal at the input terminal 301A with a delayed signal output from the delay circuit 305 to generate control signals for controlling switches 312 and 314. The output of logic gate 328 is coupled to the input of inverter 330, and the output of inverter 330 (phase output 301B) is coupled to the input of inverter 332. The output of inverter 332 is coupled to the phase output 301C.

[0025] The delay circuit 305 includes an inverter 316, a switch 318, a resistor 320, a capacitor 322, and a Schmitt trigger 326. The first terminal of resistor 320 is coupled to input terminal 301A and the input of inverter 316. The second terminal of resistor 320 is coupled to the input of Schmitt trigger 326, the first terminal of switch 318, and the first terminal of capacitor 322. The output of inverter 316 is coupled to the control terminal of switch 318. The second terminals of switch 318 and capacitor 322 are coupled to ground. When the signal at input terminal 301A is low, switch 318 discharges capacitor 322. In some embodiments of the delay circuit 305, switch 318 may be implemented using a FET. The duty cycles of signals Φ1 and Φ2 generated by switch control circuit 301 vary with the frequency of the switch control signal received at input terminal 301A. The resistance between the output of error amplifier 302 and capacitor 306 varies with the duty cycles of signals Φ1 and Φ2. The resistance decreases as the switching frequency increases, and increases as the switching frequency decreases.

[0026] Figure 4 This is a Bode plot of an example of the compensation circuit 300. Curves 402 and 404 represent the amplitude and phase when signal Φ2 is always on (lower switching frequency), and show the phase boost in the lower frequency region (e.g., 2–100 kHz). Curves 406 and 408 represent the amplitude and phase when signal Φ1 is always on (higher switching frequency), and show the phase boost in the higher frequency region (20 kHz to 1 MHz). By modulating the duty cycles of signals Φ1 and Φ2 at the switching frequency, the effective resistance applied to the compensation circuit 300 changes, causing the effective phase curve to lie between curves 404 and 408.

[0027] Figure 5 This is a signal diagram of one embodiment of a DC-DC converter 200, including a compensation circuit 300. Figure 5 In the process, the load applied to the DC-DC converter 200 decreases linearly with time. The output voltage and current in the inductor 206 and the output of the error amplifier 302 are... Figure 5 As shown in the diagram, the reduction in load causes a decrease in the switching frequency of the DC-DC converter 200. As the switching frequency of the DC-DC converter 200 decreases, the compensation circuit 300 changes the compensation resistor to avoid... Figure 1 The pulse groups shown.

[0028] Figure 6This is a graph showing how the duty cycle applied to the compensation circuit 300 changes as the load decreases. As the load decreases, the inductor current and switching frequency of the DC-DC converter 200 also decrease, and the duty cycle of signal Φ2 increases smoothly (interval 602). There are no unwanted disturbances in the output voltage.

[0029] Figure 7 This is a schematic diagram of an example compensation circuit 700 including zero-point tracking compensation based on switching frequency. Compensation circuit 700 is similar to compensation circuit 300, but with the addition of a capacitance multiplier circuit system. As described with respect to compensation circuit 300, compensation circuit 700 includes an error amplifier 302, a capacitor 306, a resistor 308, a resistor 310, a switch 312, a switch 314, and a switch control circuit 301 (not shown).

[0030] The compensation circuit 700 also includes an amplifier 702 and a switch 704. Amplifier 702 is a buffer amplifier (e.g., a unity-gain buffer). Terminals of amplifier 702 are coupled to the first terminal of capacitor 306. The output of amplifier 702 is coupled to the second input of amplifier 702 and to the first terminal of switch 704. The second terminal of switch 704 is coupled to the first terminal of switch 312. The control terminal of switch 704 is coupled to the control terminal of switch 312. When switches 314 and 704 are closed, amplifier 702 forms a capacitance multiplier circuit. Switch 704 can be implemented using a FET.

[0031] Figure 8 This is a Bode plot of an example of the compensation circuit 700. Curves 802 and 804 represent the amplitude and phase when signal Φ2 is always on (lower switching frequency), and show the phase boost in the lower frequency region (e.g., 20 kHz to 1 MHz). Curves 806 and 808 represent the amplitude and phase when signal Φ1 is always on (higher switching frequency), and show the phase boost in the higher frequency region (20 kHz to 1 MHz). By modulating the duty cycles of signals Φ1 and Φ2 at the switching frequency, the effective capacitance of the compensation circuit is controlled, and the region of phase boost 810 expands with the switching frequency. The gain in the region of phase boost 810 remains relatively constant.

[0032] Figure 9 This is a signal diagram in an example DC-DC converter, including compensation circuitry 700. Figure 9 During the test, the load current increased from approximately 100 microamps (at time A) to approximately 4 milliamps (at time C) over time. The load variation had little effect on the output voltage, and the inductor current and output voltage indicated that no pulse packets were present.

[0033] Figures 10A-10C It comes from Figure 9 A chart that magnifies the signal. Figure 10A The load current at time A (approximately 100 microamps) was amplified. Figure 9 The signal in the graph. The switching frequency of the DC-DC converter is approximately 2kHz. Signal Φ2 is activated with a delay after each switching operation. Due to the low switching frequency, signal Φ2 is relatively high, and the capacitor multiplier of the compensation circuit 700 is active most of the time to provide phase boost.

[0034] Figure 10B The load current at time B (approximately 1.8 mA) was amplified. Figure 9 The signal in the graph. The switching frequency of the DC-DC converter is approximately 33kHz. Signal Φ2 is activated with a delay after each switching operation. Signal Φ2 is high and the capacitor multiplier of the compensation circuit 700 is activated for approximately half the time.

[0035] Figure 10C The load current at time C (approximately 4 mA) was amplified. Figure 9 The signal in the graph. The switching frequency of the DC-DC converter is approximately 77kHz. Signal Φ2 is not activated (signal Φ1 is always activated), and the capacitor multiplier of the compensation circuit 700 is off. Due to the high switching frequency, phase boosting in the lower frequency range is not required.

[0036] In this specification, the term "coupled" may cover a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first example, device A is directly coupled to device B; or (b) in the second example, if intermediate component C does not substantially change the functional relationship between device A and device B, then device A is indirectly coupled to device B through intermediate component C, and therefore the control signal generated by device B via device A is controlled by device A.

[0037] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A DC-DC converter, comprising: An error amplifier that has an error output; The compensation circuit includes: A first resistor having a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the error output; A first switch has a first switch terminal, a second switch terminal, and a first control terminal, wherein the first switch terminal is coupled to the second resistor terminal; A second resistor has a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the error output; A second switch is coupled between the fourth resistor terminal and the second switch terminal, and has a second control terminal; A capacitor, coupled between the second switch terminal and the ground terminal; and A switch control circuit, which includes input terminals and is configured to: A first switch control signal is generated to control the switching of the first switch, and a second switch control signal is generated to control the switching of the second switch, wherein the duty cycle of the first switch control signal and the second switch control signal is configured to change with the switching frequency of the DC-DC converter received at the input terminal, wherein the switch control circuit is configured to close the first switch when the second switch is open and open the first switch when the second switch is closed by means of the first switch control signal and the second switch control signal, and the switch control circuit is configured to complementaryly couple the first resistor and the second resistor to the capacitor by means of the first switch control signal and the second switch control signal.

2. The DC-DC converter of claim 1, wherein the compensation circuit includes a buffer amplifier having a buffer input and a buffer output, wherein the buffer input is coupled to the capacitor and the buffer output is coupled to the first switch terminal.

3. The DC-DC converter of claim 2, wherein the compensation circuit includes a third switch having a fifth switch terminal, a sixth switch terminal, and a third control terminal, wherein the fifth switch terminal is coupled to the buffer output, and the sixth switch terminal is coupled to the first switch terminal.

4. The DC-DC converter of claim 1, wherein the switching control circuit has a first phase output and a second phase output, wherein the first phase output is coupled to the first control terminal and the second phase output is coupled to the second control terminal.

5. The DC-DC converter according to claim 4, wherein the switching control circuit comprises: A logic gate having a first logic input, a second logic input, and a logic output, wherein the first logic input is coupled to an input terminal; A delay circuit having a delay input and a delay output, wherein the delay input is coupled to the input terminal and the delay output is coupled to the second logic input; A first inverter has a first inverter input and a first inverter output, wherein the first inverter input is coupled to the logic output; as well as A second inverter has a second inverter input and a second inverter output, wherein the second inverter input is coupled to the first inverter output and the second inverter output is coupled to the second phase output.

6. The DC-DC converter of claim 5, wherein the delay circuit comprises: A third resistor has a fifth resistor terminal and a sixth resistor terminal, wherein the fifth resistor terminal is coupled to the first logic input; A Schmitt trigger having a trigger input and a trigger output, wherein the trigger input is coupled to the sixth resistor terminal; as well as A third capacitor is coupled between the sixth resistor terminal and the ground terminal.

7. The DC-DC converter of claim 6, wherein the delay circuit comprises: A third switch is coupled between the sixth resistor terminal and the ground terminal and has a third control terminal; as well as A third inverter has a third inverter input and a third inverter output, wherein the third inverter input is coupled to the fifth resistor terminal and the third inverter output is coupled to the third control terminal.

8. A DC-DC converter comprising: An error amplifier is coupled to an output terminal and a reference voltage source and is configured to provide an error signal representing the difference between the voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit includes: A first resistor is coupled to the error amplifier; A first switch is coupled between the first resistor and the capacitor and has a first control terminal; A second resistor, which is coupled to the error amplifier; and A second switch, coupled between the second resistor and the capacitor, and having a second control terminal; and A switching control circuit, coupled to the first control terminal and the second control terminal, is configured to modulate the connection of the first resistor to the capacitor and the connection of the second resistor to the capacitor in response to the switching frequency of the DC-DC converter.

9. The DC-DC converter according to claim 8, wherein: The switch control circuit is configured to complementaryly couple the first resistor and the second resistor to the capacitor; and The connection time between the first resistor and the capacitor increases with the increase of the switching frequency of the DC-DC converter.

10. The DC-DC converter of claim 8, wherein the resistance of the second resistor is greater than the resistance of the first resistor.

11. The DC-DC converter according to claim 8, wherein: The switch control circuit is configured as follows: Provide a first switch control signal to modulate the first switch; and Provide a second switch control signal to modulate the second switch; and The second switch control signal is the inverted version of the first switch control signal.

12. The DC-DC converter of claim 11, wherein the compensation circuit includes a capacitance multiplier circuit, the capacitance multiplier circuit comprising: A buffer amplifier having a buffered input and a buffered output, wherein the buffered input is coupled to the capacitor; as well as A third switch is coupled between the buffer output and the first switch and has a third control terminal, wherein the third control terminal is coupled to the switch control circuit and the second switch control signal controls the third switch.

13. An inverting buck-boost converter, comprising: High-side transistor; Low-side transistor; A controller, coupled to the output terminal, the high-side transistor, and the low-side transistor, wherein the controller includes: A reference voltage source provides a reference voltage; An error amplifier, coupled to the output terminal and the reference voltage source, is configured to provide an error signal proportional to the difference between the voltage at the output terminal and the reference voltage; and A compensation circuit, coupled to the error amplifier, includes: A first resistor is coupled to the error amplifier; A capacitor, which is coupled to the first resistor; A first switch is coupled between the first resistor and the capacitor; A second resistor, which is coupled to the error amplifier; and A second switch, coupled between the second resistor and the capacitor; and A switch control circuit is configured to control the connection of the first resistor to the capacitor via the first switch and the connection of the second resistor to the capacitor via the second switch in response to the switching frequency of the high-side transistor and the low-side transistor.

14. The inverting buck-boost converter of claim 13, wherein the switching control circuit is configured to: The connection time between the first resistor and the capacitor increases with the increase of the switching frequency; and The connection time between the second resistor and the capacitor increases as the switching frequency decreases.

15. The inverting buck-boost converter according to claim 13, wherein the resistance of the second resistor is greater than the resistance of the first resistor.

16. The inverting buck-boost converter according to claim 13, wherein the compensation circuit includes a capacitance multiplier circuit, the capacitance multiplier circuit comprising: A buffer amplifier having a buffered input and a buffered output, wherein the buffered input is coupled to a first terminal of the first switch and the buffered output is coupled to a second terminal of the first switch.

17. The inverting buck-boost converter according to claim 16, wherein: The switch control circuit is configured as follows: Provide a first switch control signal to control the first switch; and Provide a second switch control signal to control the second switch; and The second switch control signal is the inverted version of the first switch control signal.

18. The inverting buck-boost converter according to claim 17, wherein the capacitor multiplier circuit comprises: A third switch is coupled between the buffer output and the second terminal of the first switch, wherein the second switch control signal controls the third switch.

Images