Voltage detection device with trimming mechanism and voltage detection method

Abstract

Embodiments of the present application provide a voltage detection device with trimming mechanism and a voltage detection method. The voltage detection method includes: outputting a corresponding voltage from a plurality of voltages as an input voltage according to a clock signal, a first detection signal, a reset signal and a plurality of first bits; generating the reset signal according to the clock signal and a plurality of currents, wherein the voltage and the current are generated based on a power supply voltage; comparing the input voltage with a reference voltage to generate a second detection signal, and generating the first detection signal according to the second detection signal and an enable signal; and adjusting the first bits according to the second detection signal by a digital circuit during trimming to determine the first bits, and outputting the first bits and resetting according to the first detection signal during voltage detection. The present application compares the input voltage with the reference voltage through trimming, without using a high-precision bias circuit or an additional correction circuit, thereby reducing the overall circuit cost.

Description

Technical Field

[0001] This application relates to the field of voltage detection technology, specifically to a voltage detection device and voltage detection method with an adjustment mechanism. Background Technology

[0002] In existing electronic devices, if the power supply voltage or its internal voltage experiences a momentary voltage drop due to sudden power-on or power-off events, it can cause circuit malfunctions or operational errors in the electronic device.

[0003] In existing technologies, voltage detection devices determine whether there is an excessive voltage drop in the power supply voltage by comparing a reference voltage with the power supply voltage (or a voltage generated based on the power supply voltage). Since the reference voltage may shift due to process variations, existing voltage detection devices typically use high-precision bias circuits to generate the reference voltage or additional correction circuits to correct it, resulting in a significant increase in circuit cost. Summary of the Invention

[0004] This application provides a voltage detection device and a voltage detection method with a calibration mechanism, aiming to solve the technical problem that existing voltage detection devices rely on high-precision bias circuits or additional calibration circuits for detection, which increases circuit costs.

[0005] In a first aspect, embodiments of this application provide a voltage detection device, including a reference voltage selection circuit, a reset signal generation circuit, a voltage detector, and a digital circuit. The reference voltage selection circuit outputs a corresponding voltage from a plurality of first voltages as an input voltage based on a clock signal, a first detection signal, a reset signal, and a plurality of first bits, wherein the first voltages are generated based on a power supply voltage. The reset signal generation circuit generates the reset signal based on the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage. The voltage detector compares the input voltage with a reference voltage to generate a second detection signal, and generates the first detection signal based on the second detection signal and a signal strength signal. The digital circuit adjusts the first bit according to the second detection signal during an adjustment period to determine the value of the first bit, and outputs the first bit during a voltage detection period and selectively resets it according to the first detection signal.

[0006] On the other hand, embodiments of this application also provide a voltage detection method, comprising: outputting a corresponding voltage from a plurality of first voltages as an input voltage based on a clock signal, a first detection signal, a reset signal and a plurality of first bits, wherein the first voltages are generated based on a power supply voltage; generating the reset signal based on the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage; comparing the input voltage with a reference voltage to generate a second detection signal, and generating the first detection signal based on the second detection signal and a reference voltage signal; and adjusting the first bit according to the second detection signal during a trimming period using a digital circuit to determine the value of the first bit, and outputting the first bit during a voltage detection period and selectively resetting it according to the first detection signal.

[0007] This application reduces the overall circuit cost by adjusting the input voltage compared with the reference voltage, eliminating the need for high-precision bias circuits or additional correction circuits. Attached Figure Description

[0008] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments.

[0009] Figure 1 This is a schematic diagram of a chip system according to some embodiments of this application;

[0010] Figure 2 Drawings based on some embodiments of this application Figure 1 A schematic diagram of the voltage detection device in the diagram;

[0011] Figure 3 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the reference voltage selection circuit in the diagram;

[0012] Figure 4A Drawings based on some embodiments of this application Figure 2 A schematic diagram of the reset signal generation circuit in the diagram;

[0013] Figure 4B Drawings based on some embodiments of this application Figure 4A A schematic diagram of the clock flag generator in the diagram;

[0014] Figure 4C Drawings based on some embodiments of this application Figure 4A A schematic diagram of the power-on flag generator in the diagram;

[0015] Figure 5 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the voltage detector in the image;

[0016] Figure 6 Drawings based on some embodiments of this application Figure 2 A flowchart of the multiple operations performed by the voltage detection device during adjustment;

[0017] Figure 7 Drawings based on some embodiments of this application Figure 2 A flowchart of the multiple operations performed by the voltage detection device during voltage detection; and

[0018] Figure 8 A flowchart of a voltage detection method is provided based on some embodiments of this application. Detailed Implementation

[0019] All terms used in this application have their ordinary meanings. The definitions of the above terms in commonly used dictionaries, and the examples of the use of any term discussed in this application, are merely illustrative and should not be construed as limiting the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in the specification.

[0020] The term "coupling" or "connection" as used in this application can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used in this application, the term "circuit" can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0021] Figure 1 This is a schematic diagram of a chip system 100 according to some embodiments of this application. In some embodiments, the chip system 100 can be used in applications such as real-time clock (RTC) generators and / or power enable control, but this application is not limited thereto. The chip system 100 may include a voltage detection device 110, a low-dropout output regulator (LDO) 120, a clock generator 130, and a bias generator 140.

[0022] The low-dropout regulator 120, clock generator 130, and bias generator 140 can be powered by the power supply voltage VDD to provide corresponding signals. For example, the low-dropout regulator 120 can be powered by the power supply voltage VDD to provide currents I1 and I2 to the voltage detection device 110. In some embodiments, the low-dropout regulator 120 can generate a voltage (not shown) based on the power supply voltage VDD and provide this voltage to power the voltage detection device 110, clock generator 130, and / or bias generator 140. The clock generator 130 can be powered by the power supply voltage VDD (or the voltage generated by the low-dropout regulator 120 based on the power supply voltage VDD) to provide a clock signal CLK. The bias generator 140 can generate a reference voltage VREF by being powered by the power supply voltage VDD (or the voltage generated by the low dropout regulator 120 based on the power supply voltage VDD), and divide the power supply voltage VDD to generate multiple voltages VDD[0] to VDD[N-1], where the value N can be a positive integer greater than 1.

[0023] The voltage detection device 110 can receive current I1, current I2, clock signal CLK, reference voltage VREF, multiple voltages VDD[0] to VDD[N-1], and enable signal EN. In some embodiments, when the enable signal EN has a first logic value (e.g., but not limited to, logic value 1), the voltage detection device 110 operates during trimming to use multiple bits [0] to B1[M-1] (e.g., ...). Figure 2 The voltage detection device 110 selects a voltage from multiple voltages VDD[0] to VDD[N-1], where the value M can be a positive integer greater than 1. After selecting the voltage, the voltage detection device 110 stores the values ​​of multiple bits B1[0] to B1[M-1] of the selected voltage. When the enable signal EN has a second logic value different from the first logic value (for example, but not limited to, logic value 0), the voltage detection device 110 operates during voltage detection to generate the corresponding voltage using the previously stored multiple bits B1[0] to B1[M-1], thereby detecting whether the power supply voltage VDD is abnormal based on this corresponding voltage and the reference voltage VREF. The related operations during the adjustment period and the voltage detection period will be explained sequentially with reference to the figures below.

[0024] Figure 2 Drawings based on some embodiments of this application Figure 1A schematic diagram of the voltage detection device 110 is shown. The voltage detection device 110 includes a reference voltage selection circuit 111, a reset signal generation circuit 112, a voltage detector 113, and a digital circuit 114. The reference voltage selection circuit 111 outputs an output voltage VIN based on the clock signal CLK, the detection signal SP1, the reset signal SD1, and multiple bits B1[0] to B1[M-1]. For example, the reference voltage selection circuit 111 can output a corresponding voltage from multiple voltages VDD[0] to VDD[N-1] as the output voltage VDD, or output a preset voltage VD as the output voltage VDD, based on the above multiple signals. The configuration method of the reference voltage selection circuit 111 will be referred to later. Figure 3 illustrate.

[0025] The reset signal generation circuit 112 generates a reset signal SD1 based on the clock signal CLK and multiple currents I1 and I2, wherein the multiple currents I1 and I2 are Figure 1 The low-dropout regulator 120 is generated based on the power supply voltage VDD. The configuration of the reset signal generation circuit 112 will be discussed later. Figures 4A to 4C illustrate.

[0026] Voltage detector 113 compares the input voltage VIN with the reference voltage VREF to generate a detection signal SPT, and generates a detection signal SP1 based on the detection signal SPT and the enable signal EN. During voltage detection, voltage detector 113 compares the input voltage VIN with the reference voltage VREF to confirm whether the power supply voltage VDD has stabilized at the target level, thereby detecting whether there is an abnormal voltage drop in the power supply voltage VDD. The setup method for voltage detector 113 will be described later. Figure 5 illustrate.

[0027] During the adjustment period, digital circuit 114 can adjust multiple bits B1[0] to B1[M-1] according to the detection signal SPT to determine the values ​​of multiple bits B1[0] to B1[M-1], and output multiple bits B1[0] to B1[M-1] during the voltage detection period and selectively reset them according to the detection signal SP1. For example, during the adjustment period, digital circuit 114 can perform a binary search algorithm according to the detection signal SPT and sequentially adjust multiple bits B1[0] to B1[M-1] to determine the values ​​of multiple bits B1[0] to B1[M-1]. During the voltage detection period, digital circuit 114 can output multiple bits B1[0] to B1[M-1] determined during the adjustment period so that reference voltage selection circuit 111 can output the corresponding input voltage VIN to voltage detector 113. Thus, voltage detector 113 can use this input voltage VIN to compare with the reference voltage VREF, thereby detecting whether the power supply voltage VDD has reached the target level. If an abnormal voltage drop occurs in the power supply voltage VDD, causing the input voltage VIN to be too low, the detection signal SP1 will change state to instruct digital circuit 114 to reset. Under this condition, digital circuit 114 can be reset (e.g., clear internal circuit settings) to avoid errors in the internal circuit due to abnormal voltage drops. In some embodiments, digital circuit 114 may be controlled by software and / or hardware in the system to perform the aforementioned operations. In some embodiments, digital circuit 114 may be located in the system's control circuitry, central processing unit, etc. The operation of digital circuit 114 will be described later. Figure 6 and Figure 7 Explain each separately.

[0028] By employing the above-described configuration, the voltage detection device 110 can select a suitable input voltage VIN for comparison with the reference voltage VREF during the adjustment period. This ensures that the voltage detection device 110 has more accurate detection results during voltage detection, thereby improving the overall system's operational reliability. Since the reference voltage can be affected by process variations and other factors, some related technologies utilize high-precision bias circuits to generate the reference voltage and / or employ additional correction mechanisms to correct the reference voltage level, thereby improving the accuracy of voltage detection. In other words, in these technologies, the voltage detection device requires additional correction circuits and / or high-precision bias circuits, significantly increasing the overall cost. Unlike the techniques described above, in some embodiments of this application, the voltage detection device 110 does not calibrate the reference voltage VREF. Instead, it adjusts the input voltage VIN, which is compared with the reference voltage VREF. The circuit portion that adjusts the input voltage VIN and the circuit portion that detects the power supply voltage VDD are common circuits (e.g., the reference voltage selection circuit 111 and the voltage detector 113). Therefore, it is not necessary to use a high-precision bias circuit or an additional calibration circuit. This reduces the overall circuit cost.

[0029] Figure 3 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the reference voltage selection circuit 111 is shown. The reference voltage selection circuit 111 includes a flip-flop 301, multiple flip-flops 302[0] to 302[M-1], a multiplexer 303, and a multiplexer 304. The flip-flop 301 generates a trigger signal ST based on the clock signal CLK and the detection signal SP1. Specifically, in some embodiments, the flip-flop 301 includes a logic gate 301A and an inverter 301B. In some embodiments, the logic gate 301A may be, but is not limited to, a NOT gate, which can generate signal S1 based on the clock signal CLK and the detection signal SP1. The inverter 301B can generate the trigger signal ST based on signal S1.

[0030] Multiple flip-flops 302[0] to 302[M-1] can be, but are not limited to, D-type flip-flops. Multiple flip-flops 302[0] to 302[M-1] can output multiple bits B1[0] to B1[M-1] as multiple bits B2[0] to B2[M-1] respectively according to the trigger signal ST, and can reset multiple bits B2[0] to B2[M-1] according to the reset signal SD1. Taking flip-flop 302[0] as an example, flip-flop 302[0] can output bit B1[0] as bit B2[0] according to the trigger signal ST. Alternatively, when the reset signal SD1 has a preset value (for example, but not limited to, logic value 0), flip-flop 302[0] can reset bit B2[0] to logic value 0. The correspondence and operation between the remaining flip-flops 302[1]~302[M-1], the remaining bits B1[1]~B1[M-1] and the remaining bits B2[1]~B2[M-1] can be referred to flip-flops 302[0], so they will not be repeated here.

[0031] The multiplexer 303 selects a corresponding voltage VDD[i] from multiple voltages VDD[0] to VDD[N-1] based on a portion of the bits in multiple bits B2[0] to B2[M-1] (e.g., multiple bits B2[0] to B2[M-2], but not limited to), where the value i can be any positive integer between the values ​​0 and N-1. The multiplexer 304 selects to output the corresponding voltage VDD[i] or a preset voltage VD as the input voltage VIN based on the remaining bits in the multiple bits B2[0] to B2[M-1] (e.g., multiple bits B2[M-2], but not limited to).

[0032] Figure 4A Drawings based on some embodiments of this application Figure 2 A schematic diagram of the reset signal generation circuit 112 is shown below. In some embodiments, the reset signal generation circuit 112 may include a clock flag generator 401, a power-on flag generator 402, and a logic gate 403. The clock flag generator 401 generates a clock flag signal CKF based on the clock signal CLK and the current I1. The power-on flag generator 402 generates a power-on flag signal PSF based on the current I2. The logic gate 403 can generate a reset signal SD1 based on the clock flag signal CKF and the power-on flag signal PSF. In some embodiments, the logic gate 403 may be, but is not limited to, an AND gate. In some embodiments, the reset signal SD1 can be used to indicate... Figure 1The clock generator 130 is checked to ensure it is operating in a stable state after power-on (i.e., stably generating a clock signal CLK with a preset period). The clock generator 130 begins oscillating and generating the clock signal CLK after the power supply voltage VDD is powered on. The clock signal CLK may be unstable for a short period after the power supply voltage VDD is powered on, causing the clock flag signal CKF to also be unstable during this period. Therefore, by using logic gate 403 to generate the reset signal SD1 based on the clock flag signal CKF and the power-on flag signal PSF, the reset signal SD1 can be prevented from being incorrectly and continuously holding the same logic value due to the unstable clock flag signal CKF during a period after the power supply voltage VDD is powered on.

[0033] Figure 4B Drawings based on some embodiments of this application Figure 4A A schematic diagram of a clock flag generator 401 is shown. The clock flag generator 401 includes a delay circuit 411, a logic gate 412, and a switched capacitor circuit 413. The delay circuit 411 delays the clock signal CLK to generate a signal CKD (which is equivalent to a delay of the clock signal CLK). In some embodiments, the delay circuit 411 may be implemented by several series-coupled digital circuits. The logic gate 412 generates a switching signal SS based on the clock signal CLK and the signal CKD. In some embodiments, the logic gate 412 may be, but is not limited to, a mutex OR gate. The switched capacitor circuit 413 adjusts the level of node N1 based on the current I1 and the switching signal SS, and generates the clock flag signal CKF based on the level of node N1. For example, the switched capacitor circuit 413 includes a capacitor C1, a switch SW1, and an inverter 413A. The capacitor C1 is coupled between node N1 and ground and is charged via the current I1 to increase the level of node N1. Switch SW1 is coupled between node N1 and ground, and is selectively turned on according to the switching signal SS, bypassing current I1 to ground and causing capacitor C to discharge through switch SW1, thereby lowering the level of node N1. Inverter 413A is coupled to node N1 and generates clock flag signal CKF according to the level of node N1.

[0034] In detail, after the power supply voltage VDD is powered on, the low-dropout regulator 120 begins to generate a current I1, which charges capacitor C1 and raises the level of node N1. Under this condition, inverter 413A outputs a low-level clock flag signal CKF. Then, when logic gate 412 outputs a high-level switching signal SS, switch SW1 is turned on, lowering the level of node N1. As the number of times switch SW1 is turned on increases, the level of node N1 becomes increasingly lower. When the level of node N1 falls below a critical value, the output of inverter 413A changes state to generate a high-level clock flag signal CKF.

[0035] Figure 4C Drawings based on some embodiments of this application Figure 4A A schematic diagram of a power-on flag generator 402 is shown. In some embodiments, the power-on flag generator 402 includes a capacitor C2 and a buffer 402A. The capacitor C2 is coupled between node N2 and ground and is charged by a current I2 to raise the level of node N2. The buffer 402A is coupled to node N2 and generates a power-on flag signal PSF based on the level of node N2. In some embodiments, the buffer 402A may be implemented by, but is not limited to, an even number of inverters connected in series. When the power supply voltage VDD is powered on, the low-dropout regulator 120 begins to generate a current I2, causing the capacitor C2 to be charged by the current I2 to raise the level of node N2. When the level of node N2 is still below a threshold value, the buffer 402A will generate a power-on flag signal PSF with a low level. Alternatively, when the level of node N2 begins to rise above the threshold value, the buffer 402A will instead continuously generate a power-on flag signal PSF with a high level.

[0036] Figure 5 Drawings based on some embodiments of this application Figure 2 A schematic diagram of voltage detector 113 is shown. In some embodiments, voltage detector 113 includes comparator 501 and logic gate 502. Comparator 501 compares input voltage VIN with reference voltage VREF to generate detection signal SPT. Logic gate 502 can generate detection signal SP1 based on detection signal SPT and enable signal. In some embodiments, logic gate 502 can be, but is not limited to, an OR gate, which can output detection signal SP1 that continuously has a logic value of 1 when enable signal EN has a logic value of 1 (i.e., during adjustment period), thereby avoiding reset of digital circuit 114. On the other hand, when enable signal EN has a logic value of 0 (i.e., during voltage detection period), logic gate 502 can output detection signal SPT as detection signal SP1 in response to this enable signal EN.

[0037] Figure 6 Drawings based on some embodiments of this application Figure 2 The flowchart illustrates the multiple operations performed by the voltage detection device 110 during adjustment. In operation S610, an enable signal EN with a first logic value is received to generate a detection signal SP1 with the first logic value. As previously described, during adjustment, the enable signal EN has a logic value of 1 (equivalent to the aforementioned first logic value). Under this condition, the voltage detector 113 responds to this enable signal EN and generates a detection signal SP1 with a logic value of 1, thereby preventing the digital circuit 114 from being reset.

[0038] In operation S620, the power supply voltage VDD is adjusted to a target level. For example, if the normal operating level of the power supply voltage VDD is approximately 1.6 volts to 3.63 volts, the target level can be set to approximately 1.5 volts. In some embodiments, this target level is sufficient to allow... Figure 1 The clock generator 130 oscillates to begin generating a single bit of the clock signal CLK. In some embodiments, the digital circuit 114 may send at least one signal to other circuits (e.g., the low-dropout regulator 120) or the power management circuitry in the system (not shown) to perform operation S620.

[0039] In operation S630, multiple bits B1[0] to B1[M-1] are output as multiple bits B2[0] to B2[M-1] according to the trigger signal ST. As mentioned earlier, the clock generator 130 can generate a clock signal CLK starting from the power supply voltage VDD with the target level. Therefore, Figure 3 The flip-flop 301 can generate a trigger signal ST that switches with the clock signal CLK. Under this condition, multiple flip-flops 302[0] to 302[M-1] will output multiple bits B1[0] to B1[M-1] as multiple bits B2[0] to B2[M-1] according to the trigger signal ST.

[0040] In operation S640, a binary search algorithm is executed based on the detection signal SPT to determine the values ​​of multiple bits B1[0] to B1[M-1]. For example, digital circuit 114 can first generate a first set of bits B1[0] to B1[M-1] (which corresponds to one of the multiple voltages VDD[0] to VDD[N-1] with an intermediate level), and reference voltage selection circuit 111 can select the one with an intermediate level (i.e., the corresponding voltage VDD[i]) from the multiple voltages VDD[0] to VDD[N-1] based on this set of bits B1[0] to B1[M-1] as the input voltage VIN. Reference voltage selection circuit 111 can compare this input voltage VIN with the reference voltage VREF. If the input voltage VIN is higher than the reference voltage VREF, the detection signal SPT has a logic value of 1. Next, the digital circuit 114 can be modified to output a second set of bits B1[0] to B1[M-1], so that the reference voltage selection circuit 111 can select a secondary voltage with a lower than the aforementioned intermediate level from multiple voltages VDD[0] to VDD[N-1], and output this secondary voltage as the input voltage VIN. If the input voltage VIN becomes lower than the reference voltage VREF, the detection signal SPT will switch to have a logic value of 0. In this way, the digital circuit 114 can determine that the value of a set of bits B1[0] to B1[M-1] suitable for this reference voltage VREF may be the aforementioned first set of bits or the second set of bits.

[0041] Alternatively, if the input voltage VIN corresponding to the first set of bits B1[0] to B1[M-1] is lower than the reference voltage VREF, the detection signal SPT has a logic value of 0. Then, the digital circuit 114 can output the third set of bits B1[0] to B1[M-1], so that the reference voltage selection circuit 111 can select a next-lower voltage from multiple voltages VDD[0] to VDD[N-1] that has a higher value than the aforementioned intermediate level, and output this next-lower voltage as the input voltage VIN. If the input voltage VIN becomes higher than the reference voltage VREF, the detection signal SPT will switch to have a logic value of 1. Thus, the digital circuit 114 can determine that the value of a set of bits B1[0] to B1[M-1] suitable for this reference voltage VREF may be either the first set of bits or the third set of bits. By repeatedly executing the above process, the digital circuit 114 can determine the value of multiple bits B1[0] to B1[M-1] based on the detection signal SPT. It should be understood that the above-described adjustment method is a simplified binary search algorithm, but this application is not limited to it. Various suitable adjustments to binary search algorithms are also within the scope of this application.

[0042] In operation S650, the values ​​of multiple bits B1[0] to B1[M-1] are stored. In some embodiments, the digital circuit 114 may include at least one storage circuit (e.g., a buffer, but not limited to, a register) that can store the values ​​of the multiple bits B1[0] to B1[M-1] determined in operation S640.

[0043] Figure 7 Drawings based on some embodiments of this application Figure 2 A flowchart of multiple operations performed by the voltage detection device 110 during voltage detection. In operation S710, during the first period immediately after the power supply voltage VDD is powered on, multiple bits B2[0] to B2[M-2] are reset to logic value 0, so that the output preset voltage VD is used as the input voltage VIN. For example, during an initial period of the power supply voltage VDD power-on process, the reset signal SD1 is set to logic value 0 (because...). Figure 3 (The bit level of node N2 in the middle is not high enough), so that multiple flip-flops 302[0]~302[M-1] reset multiple bits B2[0]~B2[M-2] to logic value 0. Since bit B2[M-2] has logic value 0, the multiplexer 304 outputs the preset voltage VD as the input voltage VIN.

[0044] During operation of S720, in the second period after the power supply voltage VDD is powered on, multiple flip-flops 302[0] to 302[M-1] output multiple bits B1[0] to B1[M-1] as multiple bits B2[0] to B2[M-1]. For example, during a period after the power supply voltage VDD is powered on, when... Figure 3When the bit level of node N2 is high enough, the reset signal SD1 will switch to logic value 1, so that multiple flip-flops 302[0]~302[M-1] will not be reset but will start to output multiple bits B1[0]~B1[M-1] as multiple bits B2[0]~B2[M-1] according to the trigger signal ST.

[0045] In operation S730, digital circuit 114 outputs multiple previously stored bits B1[0] to B1[M-1], using the corresponding output voltage VDD[i] as the input voltage VIN. In operation S740, the input voltage VIN is compared with the reference voltage VREF to detect whether an abnormal voltage drop occurs in the power supply voltage VDD. For example, digital circuit 114 can output... Figure 6 The operation S650 stores multiple bits B1[0]~B1[M-1], which enables the reference voltage selection circuit 111 to output an input voltage VIN suitable for the reference voltage VREF, thereby allowing the power supply voltage VDD to be checked for abnormal voltage drop by comparing the reference voltage VREF with the input voltage VIN.

[0046] Figure 8 A flowchart of a voltage detection method 800 is provided according to some embodiments of this application. In operation S810, a corresponding voltage from a plurality of first voltages is output as an input voltage based on a clock signal, a first detection signal, a reset signal, and a plurality of first bits, wherein the first voltage is generated based on a power supply voltage. In operation S820, the reset signal is generated based on the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage. In operation S830, the input voltage is compared with a reference voltage to generate a second detection signal, and the first detection signal is generated based on the second detection signal and a reference voltage signal. In operation S840, the first bit is adjusted according to the second detection signal during an adjustment period by a digital circuit to determine the value of the first bit, and the first bit is output during a voltage detection period and selectively reset according to the first detection signal.

[0047] The various operations of the voltage detection method 800 described above can be referred to the descriptions of the foregoing embodiments, and therefore will not be repeated here. The various operations of the voltage detection method 800 described above are merely examples and are not limited to being performed in the order shown in this example. Without departing from the operation mode and scope of the various embodiments of this application, the various operations in the voltage detection method 800 may be appropriately added, replaced, omitted, or performed in a different order (for example, they may be performed simultaneously or partially simultaneously).

[0048] In summary, the voltage detection device and method in some embodiments of this application can utilize a voltage adjustment mechanism to find a suitable voltage for the current reference voltage, and use this voltage and the reference voltage to detect whether the power supply voltage is abnormal. Thus, voltage detection can be performed more accurately without using a high-precision reference voltage generator or a reference voltage correction mechanism, thereby improving system reliability and reducing overall circuit cost.

[0049] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make variations to the technical features of this application based on the express or implied content of this application. All such variations may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

[0050] [Symbol Explanation]

[0051] 100: Chip system;

[0052] 110: Voltage detection device;

[0053] 111: Reference voltage selection circuit;

[0054] 112: Reset signal generation circuit;

[0055] 113: Voltage detector;

[0056] 114: Digital circuits;

[0057] 120: Low dropout voltage regulator;

[0058] 130: Clock generator;

[0059] 140: Bias generator;

[0060] 301: Trigger;

[0061] 301A: Logic gates;

[0062] 301B: Inverter;

[0063] 302[0]~302[M-1]: flip-flop;

[0064] 303, 304: Multitasking;

[0065] 401: Clock Flag Generator;

[0066] 402: Power-on flag generator;

[0067] 402A: Buffer;

[0068] 403: Logic gate;

[0069] 411: Delay circuit;

[0070] 412: Logic gates;

[0071] 413: Switching capacitor circuit;

[0072] 413A: Inverter;

[0073] 501: Comparator;

[0074] 502: Logic gate;

[0075] 800: Voltage detection method;

[0076] B1[0]~B1[M-1],B2[0]~B2[M-1]: bits;

[0077] C1, C2: Capacitors;

[0078] CKD: Signal;

[0079] CKF: Clock signal;

[0080] CLK: Clock signal;

[0081] EN: Enable signal;

[0082] I1, I2: Current;

[0083] N1, N2: Nodes;

[0084] PSF: Power-on indicator signal;

[0085] S1: Signal;

[0086] S610, S620, S630, S640, S650: Operation;

[0087] S710, S720, S730, S740: Operation;

[0088] S810, S820, S830, S840: Operation;

[0089] SD1: Reset signal;

[0090] SP1, SPT: Detection signals;

[0091] SS: Switching signal;

[0092] ST: Trigger signal;

[0093] SW1: Switch;

[0094] VD: Preset voltage;

[0095] VDD: Power supply voltage;

[0096] VDD[0]~VDD[N-1],VDD[i]: Voltage;

[0097] VIN: Input voltage;

[0098] VREF: Reference voltage.

Claims

1. A voltage detection device with an adjustment mechanism, characterized in that, include: A reference voltage selection circuit outputs a corresponding voltage from a plurality of first voltages as an input voltage based on a clock signal, a first detection signal, a reset signal and a plurality of first bits, wherein the first voltage is generated based on a power supply voltage; A reset signal generation circuit generates the reset signal based on the clock signal and multiple currents, wherein the currents are generated based on the power supply voltage; A voltage detector compares the input voltage with a reference voltage to generate a second detection signal, and generates the first detection signal based on the second detection signal and a coherent energy signal; as well as A digital circuit adjusts the first bit according to a second detection signal during an adjustment period to determine the value of the first bit, and outputs the first bit during a voltage detection period and selectively resets it according to the first detection signal.

2. The voltage detection device according to claim 1, characterized in that, The reset signal generation circuit includes: A clock flag generator generates a clock flag signal based on the clock signal and a first current in the current; A power-on flag generator generates a power-on flag signal based on a second current in the current; and A first logic gate generates the reset signal based on the clock flag signal and the power-on flag signal.

3. The voltage detection device according to claim 2, characterized in that, The clock flag generator includes: A delay circuit delays the clock signal to generate a first signal; A second logic gate generates a switching signal based on the clock signal and the first signal; and A switching capacitor circuit adjusts the level of a node according to the first current and the switching signal, and generates the clock flag signal according to the level of the node.

4. The voltage detection device according to claim 3, characterized in that, The switching capacitor circuit includes: A capacitor is coupled to the node and charged via the first current to raise the level of the node; A switch, coupled between the node and ground, and selectively turned on according to the switching signal to lower the level of the node; and An inverter generates the clock flag signal based on the level of the node.

5. The voltage detection device according to claim 2, characterized in that, The power-on flag generator includes: A capacitor, coupled to a node, and charged via a second current to raise the level of the node; and A buffer generates the power-on flag signal based on the level of the node.

6. The voltage detection device according to claim 1, characterized in that, The reference voltage selection circuit includes: A trigger, which generates a trigger signal based on the clock signal and the first detection signal; Multiple flip-flops output the first bit as multiple second bits according to the trigger signal, and reset the second bits according to the reset signal; A first multiplexer selects the corresponding voltage from the first voltage based on a subset of bits from the second bit; and A second multiplexer outputs the corresponding voltage or a preset voltage as the input voltage based on a remaining bit in the second bit.

7. The voltage detection device according to claim 6, characterized in that, The trigger includes: A logic gate that generates a first signal based on the clock signal and the first detection signal; and An inverter generates the trigger signal based on the first signal.

8. The voltage detection device according to claim 1, characterized in that, The enable signal has a first logic value during the tuning period, and the voltage detector generates a first detection signal having the first logic value in response to the enable signal during the tuning period, so as to avoid the digital circuit being reset during the tuning period.

9. The voltage detection device according to claim 8, characterized in that, The enable signal has a second logic value different from the first logic value during the voltage detection period, and the voltage detector responds to the enable signal during the voltage detection period by outputting the second detection signal as the first detection signal.

10. The voltage detection device according to claim 1, characterized in that, The voltage detector includes: A comparator compares the input voltage with the reference voltage to generate the second detection signal; and A logic gate generates the first detection signal based on the second detection signal and the enable signal.

11. The voltage detection device according to claim 1, characterized in that, The digital circuit performs a binary search algorithm based on the second detection signal during the adjustment period to determine the value of the first bit.

12. A voltage detection method with a trimming mechanism, characterized in that, include: Based on a clock signal, a first detection signal, a reset signal and a plurality of first bits, a corresponding voltage from a plurality of first voltages is output as an input voltage, wherein the first voltage is generated based on a power supply voltage; The reset signal is generated based on the clock signal and multiple currents, wherein the currents are generated based on the power supply voltage. The input voltage is compared with a reference voltage to generate a second detection signal, and the first detection signal is generated based on the second detection signal and a coherent energy signal. as well as The first bit is adjusted by a digital circuit according to the second detection signal during an adjustment period to determine the value of the first bit, and the first bit is output during a voltage detection period and selectively reset according to the first detection signal.

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