Data serializer, latching data device using the same, and control method thereof

Abstract

The present disclosure provides a data serializer, a latch data device using the same and a control method thereof. The data serializer includes at least a data buffer and a deskew buffer. The data buffer receives at least an input data and a control signal. When the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal. The complementary output signal is opposite to the output signal. The deskew buffer is used to receive the complementary output signal to speed up or slow down the formation of the output signal.

Description

Technical Field

[0001] This disclosure relates to an electronic component, an electronic device using the same, and a method for controlling the same, and more particularly to a data serializer, a data latching device using the same, and a method for controlling the same. Background Technology

[0002] With the development of semiconductor technology, various electronic components are constantly being innovated. For example, data buffers are widely used in latch data devices. When a "1" control signal is applied to the enable terminal of the data buffer, the data buffer outputs "0" or "1". When a "0" control signal is applied to the enable terminal of the data buffer, the data buffer disables its output (or outputs "Hi-Z").

[0003] In the data buffer, the output signal can rise to "1" or fall to "0". Data cannot be read correctly when the output signal is rising or falling. If the rise time is longer than the fall time and the control signal has a fixed period, the duration of "1" will be shorter than the duration of "0". Conversely, if the rise time is shorter than the fall time and the control signal has a fixed period, the duration of "1" will be longer than the duration of "0".

[0004] To accurately read "0" or "1" from the output signal, a data valid window can be used. The data valid window excludes the union of rise and fall times. Only the "0" or "1" read from the data valid window is accurate. The difference between rise and fall times significantly affects the size of the data valid window. Summary of the Invention

[0005] This disclosure relates to a data serializer, a data latching device using the same, and a control method thereof, which utilizes a de-skew buffer to receive a complementary output signal to accelerate or decelerate the formation of an output signal. Therefore, the rise time and fall time of the output signal become substantially the same. Since the difference between the rise time and fall time is significantly reduced, the data valid window can be greatly expanded.

[0006] According to one aspect of this disclosure, a data serializer is proposed. The data serializer includes at least a data buffer and a de-skew buffer. The data buffer receives at least one input data and a control signal. When the control signal is at a predetermined level, the data buffer generates an output signal and a complementary output signal. The complementary output signal is opposite to the output signal. The de-skew buffer is used to receive the complementary output signal to accelerate or decelerate the generation of the output signal.

[0007] According to another aspect of this disclosure, a latch data device is proposed. The latch data device includes a latch circuit and an output transmitter. The output transmitter is connected to the latch circuit. The output transmitter includes a data serializer. The data serializer includes at least a data buffer and a de-skew buffer. The data buffer receives at least one input data and a control signal. When the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal. The complementary output signal is opposite to the output signal. The de-skew buffer is used to receive the complementary output signal to accelerate or decelerate the formation of the output signal.

[0008] According to another aspect of this disclosure, a control method for a data serializer is proposed, wherein the data serializer includes at least a data buffer and a de-skew buffer. The control method includes the following steps: The data buffer receives an input data and a control signal. When the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal. The complementary output signal is opposite to the output signal. The de-skew buffer receives the complementary output signal to accelerate or decelerate the formation of the output signal.

[0009] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a data buffer according to one embodiment.

[0011] Figure 2 This is a logical table for the data buffer.

[0012] Figure 3This is a circuit diagram of a data buffer according to one embodiment.

[0013] Figure 4A This is a schematic diagram of the voltage curves of the control signal, input data, and output signal of the data buffer when the PMOS transistor operates slower than the NMOS transistor.

[0014] Figure 4B This is a schematic diagram of the voltage curves of the control signal, input data, and output signal of the data buffer when the PMOS transistor operates faster than the NMOS transistor.

[0015] Figure 5 This is a schematic diagram of a data serializer according to one embodiment.

[0016] Figure 6 This is the logical table for the data serializer.

[0017] Figure 7 This is a circuit diagram of a data serializer according to one embodiment.

[0018] Figure 8A The voltage curves of the control signal, input data, output signal, and complementary output signal of the data serializer are shown when the PMOS transistor operates slower than the NMOS transistor.

[0019] Figure 8B The voltage curves of the control signal, input data, output signal, and complementary output signal of the data serializer are shown when the PMOS transistor operates faster than the NMOS transistor.

[0020] Figure 9 This is a schematic diagram of a data serializer according to one embodiment.

[0021] Figure 10 This is a circuit diagram of a data serializer according to one embodiment.

[0022] Figure 11 This is a schematic diagram of a latching data device according to an embodiment.

[0023] Figure 12 This is a schematic diagram of a data serializer according to another embodiment.

[0024] Figure 13 illustrate Figure 12 The output signal.

[0025] Figure 14 This is a schematic diagram of a data serializer according to another embodiment.

[0026] Figure 15This is a schematic diagram of a data serializer according to another embodiment.

[0027] Figure 16 illustrate Figure 15 The output signal.

[0028] Figure 17 This is a schematic diagram of a data serializer according to another embodiment.

[0029] Explanation of reference numerals in the attached figures

[0030] 100: Data latching device

[0031] 110: Latch circuit

[0032] 120: Output transmitter

[0033] C, CA, CB, CC, CD: Control signals

[0034] C#: Complementary Control Signals

[0035] DA, DB, DC, DD: Input data

[0036] DAB, DBB, DCB, DDB: Complementary Input Data

[0037] Dout: Output signal

[0038] Doutb: Complementary output signal

[0039] DB2: Deskip buffer

[0040] DS2, DS3, DS4, DS5, DS6, DS7: Data serializers

[0041] EN: Enable terminal

[0042] I, IB: Input terminals

[0043] Ip1, Ip2, Ip3, Ip4, In1, In2, In3, In4: Current

[0044] IV11, IV12, IV21, IV22, IV23, IV24, IV25: Inverters

[0045] L211, L212, L215, L216, L221, L222, L225, L226: Dashed lines

[0046] L213, L214, L217, L218, L223, L224, L227, L228: Solid lines

[0047] NM11, NM12, NM21, NM22, NM23, NM24, NM25, NM26: NMOS transistors

[0048] O, OB: Output terminals

[0049] PM11, PM12, PM21, PM22, PM23, PM24, PM25, PM26: PMOS transistors

[0050] t0, t1: Time intervals

[0051] T21, T22, T23, T24: Time points

[0052] TB1, TB2, TB3, TB4, TB5, TB6, TB7, TB8, TB9, TB10, TB11, TB12, TB13, TB14: Data buffers

[0053] tDV, tDV1, tDV3: Data Validation Windows

[0054] tF, tF1, tF2, tF3, tF4: descent time

[0055] tR, tR1, tR2, tR3, tR4: Rise time

[0056] V1: First voltage

[0057] V2: Second voltage Detailed Implementation

[0058] Please refer to Figure 1 The diagram illustrates a data buffer TB1 according to one embodiment. The data buffer TB1 is, for example, a tri-state buffer. The data buffer TB1 has an input terminal I, an enable terminal EN, and an output terminal O. A control signal C is input to the enable terminal EN. Input data DA is input to the input terminal I. An output signal Dout is output from the output terminal O.

[0059] Please refer to Figure 2 This shows the logic table of data buffer TB1. The control signal C input to the enable terminal EN is "1" when it is at a predetermined level; when the control signal C input to the enable terminal EN is below the predetermined level, its value is "0". When the control signal C input to the enable terminal EN is "1", the output terminal O of data buffer TB1 outputs an output signal Dout of either "0" or "1" according to the content of the input data DA input from input terminal I. When the control signal C input to the enable terminal EN is "0", data buffer TB1 does not output (or outputs "Hi-Z").

[0060] Please refer to Figure 3 The diagram illustrates a circuit diagram of a data buffer TB1 according to one embodiment. The data buffer TB1 includes a PMOS transistor PM11, a PMOS transistor PM12, an NMOS transistor NM11, an NMOS transistor NM12, an inverter IV11, and an inverter IV12. PMOS transistors PM11, PM12, NM11, and NM12 are connected in series. A first voltage V1 is applied to the drain (or source) of PMOS transistor PM11. The first voltage V1 is, for example, a drain voltage or a source voltage. A second voltage V2 is applied to the source of NMOS transistor NM12. Inverter IV11 is connected to input terminal I. The gate of PMOS transistor PM12 and the gate of NMOS transistor NM11 are connected to inverter IV11. Inverter IV12 is connected between the enable terminal EN and the gate of PMOS transistor PM11. The source (or drain) of PMOS transistor PM12 is connected to the drain of NMOS transistor NM11 at the output terminal O.

[0061] When the control signal C input to the enable terminal EN is "0", the PMOS transistor PM11 and NMOS transistor NM12 are turned off, so the current Ip1 or current In1 will not be formed, and the data buffer TB1 will not output (or output "Hi-Z").

[0062] When the control signal C input to the enable terminal EN is "1" and the input data DA input to the input terminal I is "1", PMOS transistors PM11 and PM12 will be turned on, and NMOS transistor NM11 will be turned off. Therefore, current Ip1 will be formed, and the output signal Dout output from the output terminal O will rise to "1", with the same value as the input data DA.

[0063] When the control signal input to the enable terminal EN is "1" and the input data DA input to the input terminal I is "0", NMOS transistors NM11 and NM12 will be turned on and PMOS transistor PM12 will be turned off. Therefore, current In1 will be generated, and the output signal Dout output from the output terminal O will drop to "0", which is the same as the input data DA.

[0064] Please refer to Figure 4A This diagram illustrates the voltage curves of the control signal C, input data DA, and output signal Dout of the data buffer TB1 when PMOS transistors PM11 and PM12 operate slower than NMOS transistors NM11 and NM12. Figure 4AAs shown, the rise time tR of the output signal Dout is longer than the fall time tF of the output signal Dout. Therefore, the time interval t1 of "1" will be shorter than the time interval t0 of "0".

[0065] To accurately read the "0" or "1" of the output signal Dout, a valid data window tDV can be used. The valid data window tDV excludes the union of the rise time tR and fall time tF. Only the "0" or "1" read from the valid data window tDV is accurate. The difference between the rise time tR and the fall time tF will significantly affect the size of the valid data window tDV.

[0066] Please refer to Figure 4B This diagram illustrates the voltage curves of the control signal C, input data DA, and output signal Dout of the data buffer TB1 when PMOS transistors PM11 and PM12 operate faster than NMOS transistors NM11 and NM12. Figure 4B As shown, the rise time tR of the output signal Dout is shorter than the fall time tF of the output signal Dout. Therefore, the time interval t1 of "1" will be longer than the time interval t0 of "0".

[0067] To accurately read the "0" or "1" of the output signal Dout, a valid data window tDV can be used. The valid data window tDV excludes the union of rise time tR and fall time tF. Only the "0" or "1" read from the valid data window tDV2 is the accurate content. The difference between rise time tR and fall time tF will significantly affect the size of the valid data window tDV.

[0068] Data buffers TB1 are widely used in electronic devices and data latching devices. For example, one or more data buffers can be used in a data serializer.

[0069] Please refer to Figure 5 The diagram illustrates a data serializer DS2 according to one embodiment. The data serializer DS2 includes a data buffer and a de-skew buffer DB2. The operation and control method of the data serializer DS2 are described below. The data buffer TB2 receives at least input data DA and a control signal C. When the control signal C is at a predetermined level (i.e., "1"), the data buffer TB2 forms an output signal Dout and a complementary output signal Doutb (whose value is opposite to the output signal Dout). The de-skew buffer DB2 receives the complementary output signal Doutb to accelerate or decelerate the formation of the output signal Dout.

[0070] Please refer to Figure 6This shows the logic table of the data serializer DS2. When the control signal C input to the enable terminal EN is at a predetermined level, its value is "1"; when the control signal C input to the enable terminal EN is below the predetermined level, its value is "0". When the control signal C input to the enable terminal EN is "1", the output terminal O of the data buffer TB2 outputs an output signal Dout of either "0" or "1" according to the input data DA input to the input terminal I. When the control signal C input to the enable terminal EN is "1", the output terminal OB of the data buffer TB2 outputs a complementary output signal Doutb of either "1" or "0" according to the input data DA input to the input terminal I. When the control signal C input to the enable terminal EN is "0", the data buffer TB2 does not output (or outputs "Hi-Z").

[0071] Please refer to Figure 7 The diagram illustrates a circuit diagram of a data serializer DS2 according to one embodiment. The data buffer TB2 includes a PMOS transistor PM21, a PMOS transistor PM22, an NMOS transistor NM21, an NMOS transistor NM22, an inverter IV21, a buffer gate, an inverter IV22, a PMOS transistor PM23, a PMOS transistor PM24, an NMOS transistor NM23, an NMOS transistor NM24, an inverter IV23, an inverter IV24, and an inverter IV25. PMOS transistors PM21, PM22, NMOS transistor NM21, and NMOS transistor NM22 are connected in series. A first voltage V1 is applied to the drain (or source) of PMOS transistor PM21. The first voltage V1 is, for example, a drain voltage or a source voltage. A second voltage V2 is applied to the source of NMOS transistor NM22. Inverter IV21 is connected to input terminal I. A buffer gate PG is connected to inverter IV21. PG compensates for the delay in inverter IV23. The main function of PG is to ensure that the input data DA enters the gates of PMOS transistor PM22 / NMOS transistor NM21 at the same time as the gates of PMOS transistor PM24 / NMOS transistor NM23. The gates of PMOS transistor PM22 and NMOS transistor NM21 are connected to the buffer gate PG. Inverter IV22 is connected to the enable terminal EN and the gate of PMOS transistor PM21. The source (or drain) of PMOS transistor PM22 and the drain of NMOS transistor NM21 are connected to the output terminal O.

[0072] PMOS transistors PM23 and PM24, and NMOS transistors NM23 and NM24 are connected in series. A first voltage V1 is applied to the drain (or source) of PMOS transistor PM23. The first voltage V1 is, for example, the drain voltage or the source voltage. A second voltage V2 is applied to the source of NMOS transistor NM24. Inverter IV25 is connected to input terminal I. Inverter IV23 is connected to inverter IV25. The gates of PMOS transistor PM24 and NMOS transistor NM23 are connected to inverter IV23. Inverter IV24 is connected to the enable terminal EN and the gate of PMOS transistor PM23. The source (or drain) of PMOS transistor PM24 and the drain of NMOS transistor NM23 are connected to output terminal OB.

[0073] When the control signal C input to the enable terminal EN is “0”, the PMOS transistor PM21 and NMOS transistor NM22 will be turned off, so no current Ip1 or current In1 will be generated.

[0074] When the control signal C input to the enable terminal EN is “0”, the PMOS transistor PM23 and the NMOS transistor NM24 will be turned off, so no current Ip2 or current In2 will be generated.

[0075] When the control signal C input to the enable terminal EN is "1" and the input data DA input to the input terminal I is "1", PMOS transistors PM21 and PM22 will be turned on and NMOS transistor NM21 will be turned off, thus generating a current Ip1, and the output signal Dout output from the output terminal O will rise to "1", with the same value as the input data DA.

[0076] When the control signal C input to the enable terminal EN is "1" and the input data DA input to the input terminal I is "1", NMOS transistors NM23 and NM24 will be turned on, and PMOS transistor PM24 will be turned off. Therefore, a current In2 will be generated, and the complementary output signal Doub output from the output terminal OB will drop to "0", which is opposite to the value of the input data DA.

[0077] When the control signal C input to the enable terminal EN is "1" and the input data DA input to the input terminal I is "0", NMOS transistors NM21 and NM22 will be turned on and PMOS transistor PM22 will be turned off, thus forming a current In1, and the output signal Dout output from the output terminal O will drop to "0", which is the same as the input data DA.

[0078] When the control signal C input to the enable terminal EN is "1" and the input data DA input to the input terminal I is "0", PMOS transistors PM23 and PM24 will be turned on, and NMOS transistor NM23 will be turned off. As a result, a current Ip2 will be generated, and the complementary output signal Doutb output from the output terminal OB will rise to "1", with its value being opposite to the input data DA.

[0079] The deskip buffer DB2 includes a PMOS transistor PM25, an NMOS transistor NM25, a PMOS transistor PM26, and an NMOS transistor NM26. PMOS transistor PM25 and NMOS transistor NM25 are connected in series. A first voltage V1 is applied to the drain (or source) of PMOS transistor PM25. The first voltage V1 is, for example, the drain voltage or the source voltage. A second voltage V2 is applied to the source of NMOS transistor NM25. The gates of PMOS transistor PM25 and NMOS transistor NM25 are connected to the output terminal OB. The source (or drain) of PMOS transistor PM25 and the drain of NMOS transistor NM25 are connected to the output terminal O.

[0080] PMOS transistor PM26 and NMOS transistor NM26 are connected in series. A first voltage V1 is applied to the drain (or source) of PMOS transistor PM26. The first voltage V1 is, for example, the drain voltage or the source voltage. A second voltage V2 is applied to the source of NMOS transistor NM26. The source (or drain) of PMOS transistor PM26 and the drain of NMOS transistor NM26 are connected to the output terminal OB. The gates of PMOS transistor PM26 and NMOS transistor NM26 are connected to the output terminal O.

[0081] Please refer to Figure 8A It shows the voltage curves of the control signal C, input data DA, output signal Dout, and complementary output signal Doutb of the data serializer DS2 when the PMOS transistors PM21, PM22, PM23, PM24, PM25, and PM26 operate slower than the NMOS transistors NM21, NM22, NM23, NM24, NM25, and NM26.

[0082] Please refer to Figure 8AAs shown by the dashed lines L211 and L215, the rise of the output signal Dout is slower than its fall. The output signal Dout rises slowly, while the complementary output signal Doutb falls rapidly. At time T21, the complementary output signal Doutb reaches "0" first, thus the PMOS transistor PM25 of the deskew buffer DB2 is turned on through the complementary output signal Doutb. Furthermore, at time T21, the output signal Dout is still "0", so the PMOS transistor PM26 of the deskew buffer DB2 is turned on through the output signal Dout. After PMOS transistor PM25 is turned on, a current Ip3 is generated to boost the output signal Dout; after PMOS transistor PM26 is turned on, a current Ip4 is generated to suppress the complementary output signal Doutb (boosting the complementary output signal Doutb). Therefore, referring to the solid lines L213 and L214, the formation of the output signal Dout is accelerated, while the formation of the complementary output signal is slowed down.

[0083] Please refer to Figure 8A As shown by the dashed lines L215 and L216, the output signal Dout decreases rapidly, while the complementary output signal Doutb increases slowly. At time T22, the complementary output signal Doutb is still at "0", so the PMOS transistor PM25 of the deskew buffer DB2 will be turned on through the complementary output signal Doutb. Furthermore, at time T22, the output signal Dout reaches "0" first, so the PMOS transistor PM26 of the deskew buffer DB2 will be turned on through the output signal Dout. After PMOS transistor PM25 is turned on, a current Ip3 will be generated to boost the output signal Dout; after PMOS transistor PM26 is turned on, a current Ip4 will be generated to suppress the complementary output signal Doutb (boosting the complementary output signal Doutb). Therefore, referring to the solid lines L217 and L218, the formation of the output signal Dout is slowed down, and the formation of the complementary output signal Doutb is accelerated.

[0084] In this way, the rise time tR1 and fall time tF1 of the output signal Dout become substantially equal to the rise time tR2 and fall time tF2 of the complementary output signal Doutb. Since the difference between the rise time tR1 and the fall time tF1 is greatly reduced, the effective data window tDV1 can be greatly enlarged.

[0085] Please refer to Figure 8BIt shows the voltage curves of the control signal C, input data DA, output signal Dout, and complementary output signal Doutb of the data serializer DS2 when PMOS transistors PM21, PM22, PM23, PM24, PM25, and PM26 operate faster than NMOS transistors NM21, NM22, NM23, NM24, NM25, and NM26.

[0086] Please refer to Figure 8B As shown by the dashed lines L221 and L225, the rise of the output signal Dout is faster than the fall of the output signal Dout. The output signal Dout rises rapidly, while the complementary output signal Doutb falls slowly. At time T23, the complementary output signal Doutb is still at "1", so the NMOS transistor NM25 of the deskew buffer DB2 will be turned on through the complementary output signal Doutb. Furthermore, at time T23, the output signal Dout reaches "1" first, so the NMOS transistor NM26 of the deskew buffer DB2 will be turned on through the output signal Dout. After the NMOS transistor NM25 is turned on, a current In3 will be generated to pull the output signal Dout low; after the NMOS transistor NM26 is turned on, a current In4 will be generated to suppress the complementary output signal Doutb (pull the complementary output signal Doutb low). Therefore, referring to the solid lines L223 and L224, the formation of the output signal Dout is slowed down, and the formation of the complementary output signal Doutb is accelerated.

[0087] Please refer to Figure 8B As shown by the dashed lines L225 and L226, the output signal Dout decreases slowly, while the complementary output signal Doutb increases rapidly. At time T24, the complementary output signal Doutb reaches "1" first, thus turning on the NMOS transistor NM25 of the deskew buffer DB2 through the complementary output signal Doutb. Furthermore, at time T24, the output signal Dout is still "1", so the NMOS transistor NM26 of the deskew buffer DB25 is turned on through the output signal Dout. After NMOS transistor NM25 turns on, a current In3 is generated to pull the output signal Dout low; after NMOS transistor NM26 turns on, a current In4 is generated to suppress the complementary output signal Doutb (pulling the complementary output signal Doutb low). Therefore, referring to the solid lines L227 and L228, the formation of the output signal Dout is accelerated, while the formation of the complementary output signal Doutb is slowed down.

[0088] In this way, the rise time tR3 and fall time tF3 of the output signal Dout become substantially the same as the rise time tR4 and fall time tF4 of the complementary output signal Doutb. Since the difference between the rise time tR3 and the fall time tF3 is greatly reduced, the effective data window tDV3 can be greatly enlarged.

[0089] Please refer to Figure 9 The diagram illustrates a data serializer DS3 according to one embodiment. In this embodiment, the data serializer DS3 includes a data buffer TB3 and a deskip buffer DB2. The structure of the data buffer TB3 is similar to that of the data buffer TB2, and the similarities will not be repeated. Compared to the data buffer TB2, the data buffer TB3 also includes an input terminal IB. Input data DA is input to input terminal IB, while complementary input data DAB is input to input terminal IB. The complementary input data DAB is opposite to the input data DA.

[0090] Please refer to Figure 10 This shows a circuit diagram of a data serializer DS3 according to one embodiment. In this embodiment, it is not necessary to... Figure 7 The inverter IV25 can provide the complementary output signal Doutb.

[0091] The aforementioned data serializers DS2 and DS3 are widely used in electronic devices and data latching devices. For example, please refer to... Figure 11 The diagram illustrates a latching data device 100 according to one embodiment. The latching data device 100 includes a latching circuit 110 and an output transmitter 120. The output transmitter 120 is connected to the latching circuit 110. Data stored in the latching circuit 110 is transmitted through the output transmitter 120. The output transmitter 120 includes a data serializer DS2 or a data serializer DS3.

[0092] In other embodiments, the data serializer may include two, four, or more data buffers. These embodiments are described below.

[0093] Please refer to Figure 12 This illustrates a schematic diagram of a data serializer DS4 according to another embodiment. Figure 12 In this configuration, the data serializer DS4 includes two data buffers TB3 and TB4, and a deskip buffer DB2. The structures of data buffers TB3 and TB4 are similar to those of data buffer TB2. The similarities will not be repeated here. Data buffer TB3 receives input data DA and a control signal C. Data buffer TB4 receives input data DB and a complementary control signal C#. The complementary control signal C# is opposite to the control signal C.

[0094] When the control signal C is at a predetermined level (i.e., "1"), the data buffer TB3 forms the output signal Dout and the complementary output signal Doutb (whose value is opposite to the output signal Dout). When the complementary control signal C is at a predetermined level (i.e., "1"), the data buffer TB4 forms the output signal Dout and the complementary output signal Doutb (whose value is opposite to the output signal Dout). The deskew buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

[0095] Please refer to Figure 13 Its explanation Figure 12 The output signal is Dout. The input data DA contains "DA0", "DA1", "DA2", etc. The input data DB contains "DB0", "DB1", etc. First, when the control signal C is "1" and the complementary control signal C# is "0", the output signal Dout contains "DA0". Next, when the control signal C is "0" and the complementary control signal C# is "1", the output signal Dout contains "DB0". Then, when the control signal C is "1" and the complementary control signal C# is "0", the output signal Dout contains "DA1". Since PMOS transistors operate slower than NMOS transistors, without using a deskew buffer DB2 to accelerate or slow down the formation of the output signal Dout, the fall time tF of the output signal Dout will be much shorter than the rise time tR of the output signal Dout.

[0096] In this example, the deskip buffer DB2 receives the complementary output signal Doutb to accelerate the rise of the output signal Dout and slow down its fall. Therefore, the rise time tR is shortened to a rise time tR1, and the fall time tF is lengthened to a fall time tF1. This allows the data validity window tDV1 to be significantly enlarged.

[0097] Please refer to Figure 14 This illustrates a schematic diagram of a data serializer DS5 according to another embodiment. Figure 14 In this configuration, the data serializer DS5 includes two data buffers TB5 and TB6, and a deskip buffer DB2. The structures of data buffers TB5 and TB6 are similar to those of data buffer TB3. These similarities will not be repeated here. Data buffer TB5 receives input data DA, complementary input data DAB, and control signal C. Data buffer TB6 receives input data DB, complementary input data DBB, and complementary control signal C#. The complementary control signal C# is opposite to the control signal C.

[0098] When the control signal C is at a predetermined level (i.e., "1"), the data buffer TB5 forms the output signal Dout and the complementary output signal Doutb (whose value is opposite to the output signal Dout). When the complementary control signal C# is at a predetermined level (i.e., "1"), the data buffer TB6 forms the output signal Dout and the complementary output signal Doutb. The deskip buffer DB2 receives the complementary output signal Doutb to speed up or slow down the formation of the output signal Dout.

[0099] Please refer to Figure 15 This illustrates a schematic diagram of a data serializer DS6 according to another embodiment. Figure 15 In this configuration, the data serializer DS6 includes four data buffers TB7, TB8, TB9, and TB10, and one deskip buffer DB2. The structures of data buffers TB7, TB8, TB9, and TB10 are similar to those of data buffer TB2. The similarities will not be repeated here. Data buffer TB7 receives input data DA and control signal CA. Data buffer TB8 receives input data DB and control signal CB. Data buffer TB9 receives input data DC and control signal CC. Data buffer TB10 receives input data DD and control signal CD. Control signals CA, CB, CC, and CD alternately set to "1" within one cycle.

[0100] When control signal CA is "1", data buffer TB7 generates the output signal Dout and the complementary output signal Doutb. When control signal CB is "1", data buffer TB8 generates the output signal Dout and the complementary output signal Doutb. When control signal CC is "1", data buffer TB9 generates the output signal Dout and the complementary output signal Doutb. When control signal CD is "1", data buffer TB10 generates the output signal Dout and the complementary output signal Doutb. Deskip buffer DB2 receives the complementary output signal Doutb to accelerate or decelerate the formation of the output signal Dout.

[0101] Please refer to Figure 16 Its explanation Figure 15The output signal is Dout. The input data DA contains "DA0", "DA1", "DA2", etc. The input data DB contains "DB0", "DB1", "DB2", etc. The input data DC contains "DC0", "DC1", etc. The input data DD contains "DD0", "DD1", etc. First, when control signal CA is "1" and control signals CB, CC, and CD are "0", the output signal Dout contains "DA0". Next, when control signal CB is "1" and control signals CA, CC, and CD are "0", the output signal Dout contains "DB0". Then, when control signal CC is "1" and control signals CA, CB, and CD are "0", the output signal Dout contains "DC0". Finally, when control signal CD is "1" and control signals CA, CB, and CC are "0", the output signal Dout contains "DD0". When PMOS transistors operate faster than NMOS transistors, without using a deskip buffer DB2 to accelerate or slow down the formation of the output signal Dout, the fall time Tf of the output signal Dout is much shorter than the rise time tR of the output signal Dout.

[0102] In this embodiment, the deskip buffer DB2 receives the complementary output signal Doutb to accelerate and slow down the output signal Dout. Therefore, the rise time tR is shortened to a rise time tR1, and the fall time tF is lengthened to a fall time tF1. Consequently, the data validity window tDV1 can be significantly lengthened.

[0103] Please refer to Figure 17 This illustrates a schematic diagram of a data serializer DS7 according to another embodiment. Figure 17 In this configuration, the data serializer DS7 includes four data buffers TB11, TB12, TB13, and TB14, and one deskip buffer DB2. The structures of data buffers TB11, TB12, TB13, and TB14 are similar to those of data buffer TB3. The similarities will not be described again. Data buffer TB11 receives input data DA, complementary input data DAB, and control signal CA. Data buffer TB12 receives input data DB, complementary input data DBB, and control signal CB. Data buffer TB13 receives input data DC, complementary input data DCB, and control signal CC. Data buffer TB14 receives input data DD, complementary input data DDB, and control signal CD.

[0104] When control signal CA is "1", data buffer TB11 generates the output signal Dout and the complementary output signal Doutb. When control signal CB is "1", data buffer TB12 generates the output signal Dout and the complementary output signal Doutb. When control signal CC is "1", data buffer TB13 generates the output signal Dout and the complementary output signal Doutb. When control signal CD is "1", data buffer TB14 generates the output signal Dout and the complementary output signal Doutb. Deskip buffer DB2 receives the complementary output signal Doutb to accelerate or decelerate the formation of the output signal Dout.

[0105] As described above, this disclosure utilizes a deskipation buffer DB2 to receive the complementary output signal Doutb, thereby accelerating or decelerating the formation of the output signal Dout. Therefore, the rise time tR1 and fall time tF1 of the output signal Dout become substantially equal to the rise time tR2 and fall time tF2 of the complementary output signal Doutb. Since the difference between the rise time tR1 and the fall time tF1 is significantly reduced, the data validity window tDV1 can be significantly enlarged.

[0106] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A data serializer, comprising: At least one data buffer receives at least one input data and a control signal, wherein when the control signal is at a predetermined level, the data buffer forms an output signal and a complementary output signal, the complementary output signal being opposite to the output signal; as well as A deskip buffer is used to receive the complementary output signal and accelerate or decelerate the formation of the output signal by accelerating the rise of the output signal or decelerating the fall of the output signal. The deskip buffer includes a PMOS transistor, which is coupled to the output node of the data buffer. The rise of the output signal is slower than the fall of the output signal. The PMOS transistor of the deskip buffer is turned on to accelerate the rise of the output signal and correct the timing skew.

2. The data serializer of claim 1, wherein the PMOS transistor of the deskip buffer is turned on by the complementary output signal.

3. The data serializer according to claim 1, wherein the data buffer includes a PMOS transistor, the PMOS transistor of the data buffer is connected to the deskip buffer, and the output signal rises when the PMOS transistor of the data buffer is turned on.

4. The data serializer according to claim 1, wherein the data buffer includes an NMOS transistor, the NMOS transistor of the data buffer is connected to the deskip buffer, and the output signal decreases when the NMOS transistor of the data buffer is turned on.

5. The data serializer of claim 1, wherein the data buffer further receives complementary input data, the output signal is formed based on the input data, and the complementary output signal is formed based on the complementary input data.

6. A data latching device, comprising: A latch circuit; as well as An output transmitter is connected to the latch circuit, wherein the output transmitter includes: A data serializer, comprising: At least one data buffer receives at least one input data and a control signal, wherein when the control signal is at a predetermined level, the data buffer generates an output signal and a complementary output signal, the complementary output signal being opposite to the output signal; and A deskip buffer is used to receive the complementary output signal and accelerate or decelerate the formation of the output signal by accelerating the rise of the output signal or decelerating the fall of the output signal. The deskip buffer includes a PMOS transistor, which is coupled to the output node of the data buffer. The rise of the output signal is slower than the fall of the output signal. The PMOS transistor of the deskip buffer is turned on to accelerate the rise of the output signal and correct the timing skew.

7. The latching data device according to claim 6, wherein the data buffer further receives complementary input data, the output signal is formed based on the input data, and the complementary output signal is formed based on the complementary input data.

8. A control method for a data serializer, wherein the data serializer includes at least one data buffer and a deskip buffer, the control method comprising: The data buffer receives an input data and a control signal; When the control signal is at a predetermined level, the data buffer generates an output signal and a complementary output signal, the complementary output signal being opposite to the output signal; as well as The deskip buffer receives the complementary output signal and accelerates or slows down the formation of the output signal by accelerating the rise of the output signal or slowing down the fall of the output signal. The deskip buffer includes a PMOS transistor, which is coupled to the output node of the data buffer. The rise of the output signal is slower than the fall of the output signal. The PMOS transistor of the deskip buffer is turned on to accelerate the rise of the output signal and correct the timing skew.

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