Memory device and operating method thereof

Abstract

The present disclosure provides a memory device and an operating method thereof. The memory device includes a memory array for storing a plurality of vector data. Each vector data has a most significant bit (MSB) vector and a least significant bit (LSB) vector. The memory array includes a plurality of memory cells, each memory cell having a first bit and a second bit. The first bit is used for storing the MSB vector of each vector data, and the second bit is used for storing the LSB vector of each vector data. A bit line corresponding to each vector data is set once, and the MSB vector and the LSB vector of each vector data are read according to the bit line. A threshold voltage distribution of each memory cell is divided into N states, N is a positive integer and N is less than 2 raised to the power of 2, and the equivalent number of bits stored by each memory cell is less than 2.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and its operation method, and more particularly to a memory device and a method for operation within the memory. Background Technology

[0002] With the rapid development of artificial intelligence algorithms, researchers are seeking hardware devices suitable for executing these algorithms. Semiconductor memory devices, such as NAND flash memory arrays, can perform AI calculations through in-memory computing (IMC). When performing multiply-and-accumulate (MAC) operations commonly used in AI, each memory cell in the memory array can output current to a bit line based on the product result, and the current is accumulated on the same bit line to obtain the accumulation result.

[0003] In memory arrays, performing MAC operations in an analog manner can achieve faster instruction cycles. However, the overlap of current distributions can lead to misinterpretation of the operation results, thus reducing the accuracy of the operation.

[0004] On the other hand, when reading data stored in the memory array, multiple bitline setups may be required, which consumes setup time and reduces instruction cycles.

[0005] Furthermore, when the memory array uses multi-level cells (MLC) (or "second-order cells") to store data, the threshold voltage distribution of the memory cells has a large number of states, which will lead to a reduction in the voltage interval of the read voltage, potentially causing errors in the read operation.

[0006] Based on the above-mentioned technical problems, those skilled in the art are dedicated to optimizing the storage mechanism of memory cells and the operation method of IMC operations in order to improve the accuracy of operations and instruction cycle. Summary of the Invention

[0007] The technical solution disclosed herein provides a way to perform digital MAC operations using a memory array, reduce the number of states of threshold voltage distribution in memory cells, and reduce the number of bit line settings, thereby improving operational accuracy and instruction cycle.

[0008] According to one aspect of this disclosure, a memory device is provided, including a memory array for storing a plurality of vector data, each vector data having a significant most significant bit (MSB) vector and a significant least significant bit (LSB) vector. The memory array includes a plurality of memory cells, each memory cell having a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, and the second bit is used to store the LSB vector of each vector data. A bit line setting is performed once for each vector data, and the MSB vector and LSB vector of each vector data are read according to the bit line. The threshold voltage distribution of each memory cell is divided into N states, where N is a positive integer and N is less than 2^2. The effective number of bits stored in each memory cell is less than 2.

[0009] According to another aspect of this disclosure, a method for operating a memory device is provided, wherein the memory device includes a memory array, the memory array includes a plurality of memory cells, each memory cell having a first bit and a second bit, and the method includes the following steps: Storing a plurality of vector data in the memory array, each vector data having a significant high bit (MSB) vector and a significant low bit (LSB) vector. Storing the MSB vector of each vector data in the first bit. Storing the LSB vector of each vector data in the second bit. Performing a bit line setting once for each bit line corresponding to each vector data. Reading the MSB vector and LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory cell is divided into N states, where N is a positive integer and N is less than 2^2, and the effective number of bits stored in each memory cell is less than 2.

[0010] Other aspects and advantages of this disclosure will become apparent from the following figures, detailed description, and scope of protection of this patent. Attached Figure Description

[0011] Figure 1A This is a schematic diagram of a memory device according to an embodiment of the present disclosure;

[0012] Figure 1B A flowchart of the MAC operation performed by the memory device of this disclosure;

[0013] Figure 2A This is a schematic diagram showing the threshold voltage distribution of a typical 2-bit MLC memory cell.

[0014] Figure 2B This is a schematic diagram of the threshold voltage distribution of a 1.5-bit MLC memory cell according to an embodiment of the present disclosure;

[0015] Figure 3 A flowchart of another embodiment of MAC operations performed by the memory device of this disclosure;

[0016] Figures 4A-4DThis is a schematic diagram showing the threshold voltage distribution of a 1.5-bit MLC memory cell in different embodiments of this disclosure;

[0017] Figure 5A This is a schematic diagram of the threshold voltage distribution of a conventional 3-bit TLC memory cell.

[0018] Figure 5B This is a schematic diagram of the threshold voltage distribution of a TLC memory cell according to an embodiment of the present disclosure;

[0019] Figures 5C-5I This is a schematic diagram showing the state of the threshold voltage distribution of a TLC in different embodiments of this disclosure;

[0020] Explanation of reference numerals in the attached figures:

[0021] 1000: Memory device;

[0022] 100: Memory array;

[0023] 210: First data latch;

[0024] 220: Second data latch;

[0025] 230: Shared data latch;

[0026] WL1~WLN: Word lines;

[0027] p0, q1', q1~qN: eigenvectors;

[0028] S1~S5, S1'~S8': State;

[0029] V R1 ~V R7 Read voltage;

[0030] V Pass Through voltage;

[0031] W1~W3: Voltage interval;

[0032] W1'~W4': Voltage interval;

[0033] DP_1: First data pattern;

[0034] DP_2: Second data style;

[0035] DP_3: Third data style;

[0036] DP_4: Fourth data style;

[0037] DP_1': First data pattern;

[0038] DP_2': Second data style;

[0039] DP_3': Third data style;

[0040] DP_4': Fourth data style;

[0041] DP_5': Fifth data style;

[0042] DP_6': Sixth data style;

[0043] DP_7': Seventh data style;

[0044] DP_8': Eighth data style;

[0045] Vt: Threshold voltage;

[0046] S102~S110: Steps;

[0047] S202~S210: Steps. Detailed Implementation

[0048] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0049] Figure 1A This is a schematic diagram of a memory device 1000 according to an embodiment of the present disclosure. Please refer to... Figure 1A The memory device 1000 includes a memory array 100 and multiple data latches 210, 220, and 230. The memory device 1000 can be used to perform in-memory computation (IMC), such as performing multiply-and-accumulate (MAC) operations. The memory device 1000 of this disclosure is used to perform MAC operations on numbers to improve computational accuracy. Data latch 210 may be referred to as a "first data latch," and data latch 220 may be referred to as a "second data latch." Furthermore, data latch 230 may be referred to as a "common data latch (CDL)" and can serve as an input / output interface for the memory device 1000.

[0050] The memory array 100 includes multiple word lines WL1 to WLN, each of which can store one vector of data. When the memory device 1000 is used to perform the MAC operation of the face recognition algorithm, the feature vectors q1 to qN of N faces F1 to FN can be pre-stored in the word lines WL1 to WLN of the memory array 100. For example, the feature vector q1 of the first face F1 is 20 bits of binary data "00110011001100001111" and is stored in word line WL1, the feature vector q2 of the second face F2 is 20 bits of data "11001100110000001111" and is stored in word line WL2, and so on.

[0051] Furthermore, the memory array 100 of this disclosure uses 1.5-bit multi-level cells (MLCs). Compared to a conventional 2-bit MLC (hereinafter referred to as "2-bit MLC"), the 1.5-bit MLC (hereinafter referred to as "1.5-bit MLC") of this disclosure stores less data, with an equivalent bit width of 1.5 bits. The mechanism of the 1.5-bit MLC will be described in detail later.

[0052] Data latch 230 (i.e., shared data latch (CDL)) can temporarily store vector data input from outside the memory device 1000. When performing face recognition or face search, the feature vector p0 of the face F0 to be recognized can be input from outside to the memory device 1000 and temporarily stored in data latch 230. The feature vector p0 is, for example, a 20-bit string "11111111000000001111". Then, the feature vector p0 is transferred from data latch 230 to data latch 210.

[0053] A "selective bit-line read" operation can be performed in the memory array 100 to read feature vectors q1 to qN from word lines WL1 to WLN respectively. The selective bit-line read operation can perform a product operation. The feature vector p0 to be identified can also be called the "input feature vector p0", and the pre-stored feature vectors q1 to qN can also be called the "weight feature vectors qi", i = 1 to N. The selective bit-line read operation can achieve the product operation of the input feature vector p0 and the weight feature vector qi. When the corresponding bit of feature vector p0 and feature vector qi are both "1", the selective bit-line read operation can read that bit of feature vector qi as "1". When the bit of feature vector p0 is "0" or the corresponding bit of feature vector qi is "0", the selective bit-line read operation can read that bit of feature vector qi as "0". Accordingly, the output result qi' = p0 * qi obtained by the selective bit-line read operation. The output result qi' can also be called the "output feature vector qi'". For example, the feature vector p0 = "11111111000000001111", the feature vector q1 of the first face F1 = "00110011001100001111", and the output feature vector q1' obtained by the bit line read operation = "00110011000000001111". Then, the output feature vector q1' can be written to the data latch 220.

[0054] Then, an accumulation operation can be performed on the output feature vector q1' temporarily stored in the data latch 220 to accumulate the "1" bits in the output feature vector q1'. In one example of the accumulation operation, the memory device 1000 can execute a fail-bit-count instruction to perform a counting operation on the output feature vector q1'. Taking the output feature vector q1' = "00110011000000001111" as an example, where 8 bits B0-B3, B12, B13, B16, and B17 are "1", the counting result C1 of the output feature vector q1' is decimal "8", and the counting result C1 is the accumulated result MAC1 of the product of feature vector p0 and feature vector q1. Then, the counting result C1 can be transferred to the data latch 230, and the counting result C1 can be output to the outside of the memory device 1000.

[0055] In face recognition algorithms, the similarity between a pre-stored face F1 and the face F0 to be identified can be represented as the inner product of feature vectors p0 and q1, denoted as "||q1||||p0||cosθ". The higher the similarity between face F1 and face F0, the closer the angle "θ" is to zero, and the closer the inner product of feature vectors p0 and q1 is to "||q1||||p0||". Therefore, the similarity between face F1 and the face F0 to be identified can be evaluated based on the sum of the products of feature vectors p0 and q1, MAC1.

[0056] Figure 1B A flowchart illustrating the MAC operation performed by the memory device 1000 of this disclosure. See also... Figure 1B (and see also) Figure 1A In step S102, the feature vector p0 of the face F0 to be identified is input or fed into the memory device 1000. The feature vector p0 may be temporarily stored in the data latch 230.

[0057] Then, in step S104, the feature vector p0 is transferred from data latch 230 (i.e., the shared data latch (CDL)) to data latch 210 (i.e., the first data latch). Next, in step S106, a bit-line read operation is performed to read feature vectors q1 to qN from word lines WL1 to WLN of the memory array 100, and a product operation is performed on them. The output feature vectors q1' to qN' obtained from the bit-line read operation are the products of feature vectors q1 to qN and feature vector p0. The output feature vectors q1' to qN' can be temporarily stored sequentially in data latch 220.

[0058] Then, in step S108, a counting operation is performed on the output feature vectors q1' to qN' temporarily stored in the data latch 220 respectively to obtain the counting result C1. Then, in step S110, the counting result C1 can be transferred to the data latch 230, and the counting result C1 can be output through the data latch 230.

[0059] On the other hand, please refer to Tables 1 and 2. Table 1 shows a typical 2-bit MLC data allocation DA_1 for a comparative example. A physical page of the memory array may include multiple logical pages, such as high pages and low pages. Taking a typical 2-bit MLC as an example, the high page corresponds to the first bit CB1 of the MLC memory cell, and the low page corresponds to the second bit CB2 of the MLC memory cell. In the comparative example's data allocation DA_1, the feature vectors of different faces can be stored in the high page or the low page respectively. For example, the feature vector q1 of the first face F1 among faces F1 to FN is stored in the high page, and the feature vector q2 of the second face F2 is stored in the low page.

[0060] Table 1 (Data Configuration DA_1)

[0061]

[0062] Table 2 shows the data configuration DA_2 of the 1.5-bit MLC of this disclosure. The feature vector of a face can be divided into vectors of most significant bits (MSB) and least significant bits (LSB). For example, the feature vector q1 of face F1 can be divided into an MSB vector and an LSB vector, each with 4 bits. The MSB vector, being of higher importance, is stored in a higher page, and the LSB vector, being of lower importance, is stored in a lower page. Similarly, the MSB vector of the feature vector q2 of the next face F2 is stored in a higher page, and the LSB vector of feature vector q2 is stored in a lower page. Furthermore, the higher page corresponds to the first bit CB1 of the 1.5-bit MLC of this disclosure, and the lower page corresponds to the second bit CB2 of the 1.5-bit MLC.

[0063] Table 2 (Data Configuration DA_2)

[0064]

[0065] Figure 2A This is a schematic diagram of the threshold voltage distribution of a typical 2-bit MLC. Figure 2B This is a schematic diagram of the threshold voltage distribution of a 1.5-bit MLC according to an embodiment of the present disclosure, which illustrates the mechanism of the 1.5-bit MLC.

[0066] Please refer to [the website / information] first. Figure 2AThe threshold voltage Vt of the memory cell can be programmed to different voltage levels. Based on the distribution of the programmed threshold voltage Vt, a conventional 2-bit MLC can have four states S1' to S4'. The number of states S1' to S4', "4", is equal to 2 to the power of 2.

[0067] Among them, state S1' is between 0V (zero potential) and the read voltage V. R1 Between, state S2' is between the read voltage V R1 With reading voltage V R2 Between, state S3' is between the read voltage V R2 With reading voltage V R3 Between, state S4' is between the read voltage V R3 With voltage V Pass A typical 2-bit MLC can store 2 bits of data (CB1, CB2). State S1' corresponds to data (CB1=1, CB2=1), state S2' corresponds to data (CB1=1, CB2=0), state S3' corresponds to data (CB1=0, CB2=0), and state S4' corresponds to data (CB1=0, CB2=1). The narrow voltage intervals W1' to W4' between states S1' and S4' in a typical 2-bit MLC can lead to errors in reading data (CB1, CB2), thus reducing the accuracy of in-memory operations (such as MAC operations).

[0068] Please see Figure 2B In the case of the 1.5-bit MLC disclosed herein, the distribution of the threshold voltage Vt is divided into only N states, where N is less than 2 to the power of 2. For example, if N = 3, then the 1.5-bit MLC has 3 states S1 to S3. Among them, state S1 is between 0V (zero potential) and the read voltage Vt. R1 Between, state S2 is between the read voltage V R1 With reading voltage V R2 Between, state S3 is between the read voltage V R2 With voltage V Pass The equivalent number of bits of data that a 1.5-bit MLC can store is 1.5 bits. State S1 corresponds to data (CB1=1, CB2=1), state S2 corresponds to data (CB1=1, CB2=0), and state S3 corresponds to data (CB1=0, CB2=0). In other words, a 1.5-bit MLC does not include data (CB1=0, CB2=1), and the states S3' and S4' of a conventional 2-bit MLC can be considered as a single state S3 of the 1.5-bit MLC. The voltage spacing W1 to W3 corresponding to states S1 to S3 of the 1.5-bit MLC is larger than the voltage spacing W1' to W4' of a conventional 2-bit MLC, thus improving the accuracy of reading data (CB1, CB2) from the 1.5-bit MLC.

[0069] Table 3 shows an example of the contents of the first CB1 and the second CB2, which can show the difference between the data (CB1, CB2) of a 1.5-bit MLC and a regular 2-bit MLC.

[0070] Table 3

[0071]

[0072] In addition to employing a 1.5-bit MLC to improve data read accuracy, the memory device 1000 disclosed herein can reduce redundant bit line setup operations during operation, thereby reducing the time required for data read operations.

[0073] For a typical 2-bit MLC, reading the second bit CB2 on the lower page requires performing a bit line setup and applying a read voltage V. R2 The bit line setup time t_BL_S is, for example, 60 μs, and the read voltage V is applied once. R2 The corresponding read time t_Vread is, for example, 15μs. That is, the execution time of the read operation of the second bit CB2 is approximately 60μs + 15μs = 75μs. On the other hand, the read operation of the first bit CB1 of the high page requires one bit line setup and the application of two read voltages V. R1 V R3 That is, the execution time of the first CB1 read operation is approximately 60μs + 2 * 15μs = 90μs. Therefore, the read time for the high and low pages (CB1, CB2) of a typical 2-bit MLC is approximately 75μs + 90μs = 165μs.

[0074] Furthermore, for a conventional 1-bit single-level cell (SLC), since a conventional 1-bit SLC only stores 1 bit of data, reading 2 bits of data requires two read operations. Each read operation requires one bit line setup and one application of the read voltage V. R1 The execution time is approximately 60μs + 15μs = 75μs. Therefore, the reading time for a typical 1-bit SLC to read 2 bits of data is approximately 2 * 75μs = 150μs.

[0075] In contrast, the memory device 1000 of this disclosure performs only one bit line setup when reading the first bit CB1 and the second bit CB2, thus requiring only one bit line setup time t_BL_S = 60μs. Furthermore, the 1.5-bit MLC used in the memory device 1000 of this disclosure operates only on two read voltages V. R1 VR2 Therefore, only two read operations (t_Vread) are required, totaling 2 * 15 μs = 30 μs. Thus, the read time for the high and low pages (CB1, CB2) of a 1.5-bit MLC is approximately 60 μs + 30 μs = 90 μs. Accordingly, compared to the read time of 165 μs for a conventional 2-bit MLC and 150 μs for a conventional 1-bit SLC, the memory device 1000 of this disclosure performs a bitline setup only once and utilizes the 1.5-bit MLC mechanism, resulting in a significant improvement in read latency.

[0076] Figure 3 A flowchart of another embodiment of the MAC operation performed by the memory device 1000 of this disclosure. See also... Figure 3 In step S202, the condition of the memory device 1000 is determined. When it is determined that the memory device 1000 will perform a MAC operation, step S204 is then performed: the feature vector qi is read from the memory array 100 composed of 1.5-bit MLCs. For example, an instruction to select a bit line read operation is executed, a bit line setting is performed once, and two read voltages V are applied. R1 V R2 Each data point (CB1, CB2) of the 1.5-bit MLC is read. The first bit CB1 stored in the high page of the memory array 100 corresponds to the MSB vector of the feature vector qi, and the second bit CB2 stored in the low page corresponds to the LSB vector of the feature vector qi. Counting operations of different data amounts can be performed on the MSB vector and the LSB vector respectively for accumulation operations.

[0077] On the other hand, in step S202, when it is determined that the memory device 1000 will remove data, step S210 is then performed: data deletion. For example, N feature vectors q1 to qN stored in the memory array 100 are deleted.

[0078] On the other hand, in step S202, when it is determined that the memory device 1000 will create, insert, or update data, step S206 is then performed: quantizing and calculating the revised feature vector qi. Next, step S208 is performed: the revised feature vector qi is programmed and written into the memory array 100. The writing operation of the feature vector qi can be based on... Figure 2B The data pattern of the 1.5-bit MLC shown is executed according to the data configuration shown in Table 2.

[0079] Figures 4A-4DThis diagram illustrates the threshold voltage distribution of a 1.5-bit MLC according to different embodiments of this disclosure, explaining different data styles of the 1.5-bit MLC. Please refer to [link to previous text]. Figure 4A In the first data pattern DP_1 of a 1.5-bit MLC, state S1 of the threshold voltage Vt distribution corresponds to data (CB1=1, CB2=1), state S2 corresponds to data (CB1=1, CB2=0), and state S3 corresponds to data (CB1=0, CB2=0). The states S3' and S4' of a conventional 2-bit MLC can be considered as a single state S3 of the 1.5-bit MLC. Furthermore, the first data pattern DP_1 of the 1.5-bit MLC does not include data (CB1=0, CB2=1), but instead treats the second bit CB2 = "1" of the data (CB1=0, CB2=1) as "0". Since the second bit CB2 corresponds to a lower page to store the LSB vector with lower data importance, treating the second bit CB2 = "1" as "0" does not affect data accuracy.

[0080] Please see Figure 4B In the second data pattern DP_2 of a 1.5-bit MLC, state S1 of the threshold voltage Vt distribution corresponds to data (CB1=1, CB2=1), state S2 corresponds to data (CB1=1, CB2=0), and state S3 corresponds to data (CB1=0, CB2=1). The states S3' and S4' of a conventional 2-bit MLC can be considered as a single state S3 of the 1.5-bit MLC. Furthermore, the second data pattern DP_2 of the 1.5-bit MLC does not include data (CB1=0, CB2=0), but instead treats the second bit CB2=0 of the data (CB1=0, CB2=0) as the second bit CB2=1.

[0081] Please see Figure 4C In the third data pattern DP_3 of a 1.5-bit MLC, state S1 of the threshold voltage Vt distribution corresponds to the data (CB1=1, CB2=0), state S2 corresponds to the data (CB1=0, CB2=0), and state S3 corresponds to the data (CB1=0, CB2=1). The states S1' and S2' of a conventional 2-bit MLC can be considered as a single state S1 of the 1.5-bit MLC. Furthermore, the third data pattern DP_3 of the 1.5-bit MLC does not include the data (CB1=1, CB2=1), but instead treats the second bit CB2=1 of the data (CB1=1, CB2=1) as the second bit CB2=0.

[0082] Please see Figure 4DIn the fourth data pattern DP_4 of a 1.5-bit MLC, state S1 of the threshold voltage Vt distribution corresponds to data (CB1=1, CB2=1), state S2 corresponds to data (CB1=0, CB2=0), and state S3 corresponds to data (CB1=0, CB2=1). The states S1' and S2' of a conventional 2-bit MLC can be considered as a single state S1 of a 1.5-bit MLC. Furthermore, the fourth data pattern DP_4 of the 1.5-bit MLC does not include data (CB1=1, CB2=0), but instead treats the second bit CB2 = "0" in the data (CB1=1, CB2=0) as "1".

[0083] Figures 4A-4D The first data patterns DP_1 to the fourth data patterns DP_4 of the 1.5-bit MLC shown can be implemented in the memory device 1000 of this disclosure in conjunction with the data configuration DA_2 shown in Table 2, for storing the MSB vector and LSB vector of the feature vector qi to perform MAC operations. In the first data patterns DP_1 to the fourth data patterns DP_4, the second bit CB2 = "0" is regarded as "1". Since the second bit CB2 corresponds to the lower page to store the LSB vector with lower data importance, the impact of the second bit CB2 = "0" being regarded as "1" is not significant.

[0084] In other examples, the memory cells of the memory device 1000 of this disclosure may also be triple-level cells (TLC), and a TLC memory cell may have a first bit CB1, a second bit CB2, and a third bit CB3. Please refer to [link to previous document]. Figure 5A This is a schematic diagram of the threshold voltage distribution of a conventional 3-bit TLC memory cell. A conventional 3-bit TLC can have 8 states S1' to S8', corresponding to 3 bits of data (CB1, CB2, CB3). The number of states S1' to S8', "8", is equal to 2 to the power of 3. In this diagram, state S1' corresponds to data (CB1=1, CB2=1, CB3=1), state S2' corresponds to data (CB1=1, CB2=1, CB3=0), state S3' corresponds to data (CB1=1, CB2=0, CB3=0), state S4' corresponds to data (CB1=0, CB2=0, CB3=0), state S5' corresponds to data (CB1=0, CB2=1, CB3=0), state S6' corresponds to data (CB1=0, CB2=1, CB3=1), state S7' corresponds to data (CB1=0, CB2=0, CB3=1), and state S8' corresponds to data (CB1=1, CB2=0, CB3=1). States S1' to S8' correspond to narrower voltage gaps W1' to W8', which may lead to errors in reading data (CB1, CB2, CB3).

[0085] Please see Figure 5B A schematic diagram illustrating the state distribution of the threshold voltage of a TLC memory cell according to an embodiment of this disclosure is shown. The threshold voltage Vt distribution of the TLC in this embodiment is divided into only M states, where M is less than 2 to the power of 3. For example, if M = 5, then the TLC in this embodiment has 5 states S1 to S5. State S1 corresponds to data (CB1 = 1, CB2 = 1, CB3 = 1), state S2 corresponds to data (CB1 = 1, CB2 = 0, CB3 = 0), state S3 corresponds to data (CB1 = 0, CB2 = 0, CB3 = 0), state S4 corresponds to data (CB1 = 0, CB2 = 1, CB3 = 1), and state S5 corresponds to data (CB1 = 0, CB2 = 0, CB3 = 1). The data stored in the TLC of this embodiment does not include the data (CB1 = 1, CB2 = 1, CB3 = 0). The states S1' and S2' of a conventional 3-bit TLC can be considered as a single state S1 of the TLC in this embodiment. Similarly, the states S4' and S5' of a conventional 3-bit TLC are considered as a single state S3 of the TLC in this embodiment, and data (CB1=0, CB2=1, CB3=0) is excluded. The states S7' and S8' of a conventional 3-bit TLC are also considered as a single state S5 of the TLC in this embodiment, and data (CB1=1, CB2=0, CB3=1) is excluded. Although the equivalent number of bits of data stored by the TLC in this embodiment is less than 3 bits, the voltage intervals corresponding to states S1 to S5 of the TLC in this embodiment are relatively large, which can improve the accuracy of reading data (CB1, CB2, CB3). Figure 5B The patterns of states S1 to S5 and their corresponding data (CB1, CB2, CB3) shown can be called the first data pattern DP_1' of TLC.

[0086] Figures 5C-5I This is a schematic diagram illustrating the threshold voltage distribution of a TLC in different embodiments of the present disclosure, and it explains different data styles of the TLC.

[0087] first, Figure 5C The second data style DP_2' shown is similar to the first data style DP_1', except that the conventional 3-bit TLC states S7' and S8' are treated as a single state S5 of the TLC in this embodiment and the data is excluded (CB1=0, CB2=0, CB3=1).

[0088] Other data styles of TLC can be obtained by different data arrangements. Figure 5D The third data pattern DP_3' shown is similar to the first data pattern DP_1', except that it excludes data (CB1=0, CB2=0, CB3=0). Figure 5EThe fourth data pattern DP_4' shown is similar to the first data pattern DP_1', except that it excludes data (CB1=0, CB2=1, CB3=1). Figure 5F The fifth data pattern DP_5' shown is similar to the third data pattern DP_3', except that it excludes data (CB1=0, CB2=0, CB3=1). Figure 5G The sixth data pattern DP_6' shown is similar to the fourth data pattern DP_4', except that it excludes data (CB1=0, CB2=0, CB3=1). Figure 5H The seventh data pattern DP_7' shown is similar to the fourth data pattern DP_4', except that it excludes data (CB1=0, CB2=0, CB3=0). Figure 5I The eighth data pattern DP_8' shown is similar to the seventh data pattern DP_7', except that it excludes data (CB1=0, CB2=0, CB3=1).

[0089] On the other hand, please refer to Tables 4 and 5. Table 4 shows the data configuration DA_3 of a conventional 3-bit TLC for another comparative example. A physical page of the memory array may include a high page, a middle page, and a low page, corresponding to the first bit CB1, the second bit CB2, and the third bit CB3 of the TLC memory cell, respectively. The feature vector q1 of the first face F1 among faces F1 to FN is stored in the high page, the feature vector q2 of the second face F2 is stored in the middle page, and the feature vector q3 of the third face F3 is stored in the low page.

[0090] Table 4 (Data Configuration DA_3)

[0091]

[0092]

[0093] Table 5 shows the data configuration DA_4 for the TLC of this disclosure. The data of each feature vector can be divided into a first part P1, a second part P2, and a third part P3, and stored in high-page, medium-page, and low-page locations respectively according to the importance of the data in each part.

[0094] Table 5 (Data Configuration DA_4)

[0095]

[0096] The above embodiments illustrate various data styles and configurations for MLC and TLC with fewer equivalent bits. A similar mechanism can also be applied to quad-level cells (QLC).

[0097] While this disclosure has been described in detail above with reference to preferred embodiments and examples, it is understood that these examples are for illustrative purposes and not for limiting purposes. It is anticipated that various modifications and combinations will arise in the hands of those skilled in the art, and such modifications and combinations fall within the spirit of this disclosure and the scope of the appended claims.

Claims

1. A memory device, characterized in that, include: A memory array for storing multiple vector data, the multiple vector data including at least an input feature vector and an output feature vector, each of the vector data having a most significant bit (MSB) vector and a least significant bit (LSB) vector, the memory array comprising: Multiple storage units, each storage unit having a first bit and a second bit, the first bit being used to store the MSB vector of each vector data, and the second bit being used to store the LSB vector of each vector data; Multiple data latches, including: a common data latch, a first data latch, and a second data latch; In this process, each bit line corresponding to the vector data performs a bit line setting once, and reads the MSB vector and LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory cell is divided into N states, where N is a positive integer and N is less than 2 to the power of 2. The equivalent number of bits stored in each memory cell is less than 2. The shared data latch is used to receive the input feature vector from the outside, then transfer the input feature vector from the shared data latch and temporarily store it in the first data latch. The memory device performs a selective bit line read operation based on the input feature vector in the first data latch to read the MSB vector and LSB vector of the input feature vector according to the corresponding bit line that has been set, thereby obtaining the output feature vector, and then temporarily stores the output feature vector in the second data latch.

2. The memory device of claim 1, wherein a physical page of the memory array has a plurality of logical pages, the plurality of logical pages including a high page and a low page, the high page corresponding to the first bit to store the MSB vector, and the low page corresponding to the second bit to store the LSB vector.

3. The memory device according to claim 1, wherein each memory cell is a multi-level memory cell, and the threshold voltage distribution of each memory cell is divided into a first state, a second state and a third state. in, The first state corresponds only to data where the first bit is "1" and the second bit is "0", or the first state corresponds only to data where the first bit is "1" and the second bit is "1".

4. The memory device according to claim 1, wherein each memory cell is a second-order memory cell, and the threshold voltage distribution of each memory cell is divided into a first state, a second state and a third state. in, The third state corresponds only to data where the first bit is "0" and the second bit is "0", or the third state corresponds only to data where the first bit is "0" and the second bit is "1".

5. The memory device according to claim 1, wherein each of the memory cells is a third-order memory cell, each of the memory cells further having a third bit, the first bit being used to store a first portion of each of the vector data, the second bit being used to store a second portion of each of the vector data, and the third bit being used to store a third portion of each of the vector data. in, The threshold voltage distribution of each memory cell is divided into N states, where N is a positive integer and less than 2 to the power of 3, and the equivalent number of bits stored in each memory cell is less than 3.

6. The memory device of claim 1, wherein the plurality of vector data comprises a plurality of weighted feature vectors, and the memory array comprises: Multiple word lines are used to store the multiple weighted feature vectors; The memory device performs a selected bit line read operation to read the plurality of weighted feature vectors from the plurality of word lines respectively.

7. The memory device of claim 6, wherein the memory device performs a product operation based on the input feature vector and one of the plurality of weight feature vectors.

8. The memory device according to claim 7, wherein the second data latch is used to temporarily store the result of the product operation; Furthermore, the memory device performs an accumulation operation based on the result of the product operation.

9. A method of operating a memory device, wherein the memory device includes a memory array and a plurality of data latches, the memory array including a plurality of memory cells, each memory cell having a first bit and a second bit, and the data latches including: It uses a common data latch, a first data latch, and a second data latch; The operation method includes: Multiple vector data are stored in the memory array. The multiple vector data include at least an input feature vector and an output feature vector. Each vector data has a significant most significant bit (MSB) vector and a significant least significant bit (LSB) vector. The MSB vector storing each vector data is located in the first position; The LSB vector for storing each vector data is located in the second bit; Perform a bit line setting once for each bit line corresponding to the vector data; and read the MSB vector and LSB vector of each vector data according to the bit line; The shared data latch receives the input feature vector from the outside, then transmits the input feature vector from the shared data latch and temporarily stores it in the first data latch; In the first data latch, a selective bit-line read operation based on the input feature vector is performed to read the MSB and LSB vectors of the input feature vector according to the corresponding bit lines that have been set, thereby obtaining the output feature vector; and The output feature vector is temporarily stored in the second data latch; The threshold voltage distribution of each memory cell is divided into N states, where N is a positive integer and less than 2 to the power of 2, and the equivalent number of bits stored in each memory cell is less than 2.

10. The operation method according to claim 9, wherein a physical page of the memory array has a plurality of logical pages, the plurality of logical pages including a high page and a low page, the high page corresponding to the first bit to store the MSB vector, and the low page corresponding to the second bit to store the LSB vector.

Images