Semiconductor devices and semiconductor systems

Abstract

Semiconductor devices and semiconductor systems are disclosed. A semiconductor device includes an address input circuit configured to raise a voltage level of at least one bit of a row address to generate a boosted address, and to drive a signal of a first node based on other bits of the row address and the boosted address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node, and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0004839, filed on January 12, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor device and a semiconductor system including the semiconductor device. Background Technology

[0004] Semiconductor devices perform row or column operations to store data in or output data stored in a memory cell array. A row operation can be performed by decoding a row address and selecting at least one word line included in the memory cell array. A column operation can be performed by decoding a column address and selecting at least one bit line included in the memory cell array. Summary of the Invention

[0005] According to embodiments of this disclosure, a semiconductor device includes: an address input circuit configured to raise the voltage level of at least one bit of a row address to generate a boost address, and a signal for driving a first node based on other bits of the row address and the boost address. The semiconductor device further includes: a word line select signal generation circuit configured to drive a signal for a second node based on the signal of the first node, and to generate a word line select signal for selecting a word line based on the signal of the second node.

[0006] According to another embodiment of this disclosure, a semiconductor device includes: an address input circuit configured to generate a first boost address and a second boost address based on at least one bit of a row address, to drive a signal of a first node based on other bits of the row address and the first boost address, and to drive a signal of a second node based on the row address and the second boost address. The semiconductor device further includes: a first word line select signal generation circuit configured to drive a signal of a third node based on the signal of the first node, and to generate a first word line select signal for selecting a first word line based on the signal of the third node. The semiconductor device further includes: a second word line select signal generation circuit configured to drive a signal of a fourth node based on the signal of the second node, and to generate a second word line select signal for selecting a second word line based on the signal of the fourth node.

[0007] According to another embodiment of this disclosure, a semiconductor system includes a controller configured to output external control signals. The semiconductor system also includes semiconductor devices. The semiconductor devices are configured to raise the voltage level of at least one bit of a row address generated based on the external control signals to generate a boost address, drive signals for a first node based on other bits of the row address and the boost address, drive signals for a second node based on the signals for the first node, and generate word line select signals for selecting word lines based on the signals for the second node. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of a semiconductor system according to an embodiment of the present disclosure.

[0009] Figure 2 This is a block diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a diagram illustrating the configuration of a line decoder according to an embodiment of the present disclosure.

[0011] Figure 4 This is a diagram illustrating the configuration of a line decoder according to another embodiment of the present disclosure.

[0012] Figure 5 This is a diagram illustrating the configuration of a line decoder according to yet another embodiment of the present disclosure.

[0013] Figure 6 This is a circuit diagram of a source power generation circuit according to an embodiment of the present disclosure.

[0014] Figure 7 and Figure 8 It is a diagram. Figure 6 The circuit diagram shown illustrates the operation of the power generation circuit.

[0015] Figure 9 This is a diagram illustrating the configuration of a line decoder according to yet another embodiment of the present disclosure.

[0016] Figure 10 This is a block diagram illustrating the configuration of an electronic system according to an embodiment of the present disclosure.

[0017] Figure 11 This is a block diagram illustrating the configuration of an electronic system according to another embodiment of the present disclosure. Detailed Implementation

[0018] In the following description of the embodiments, when a parameter is referred to as “predetermined,” it may mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during the execution of the process or algorithm.

[0019] It should be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply the order or number of elements. Therefore, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this disclosure.

[0020] Furthermore, it should be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0021] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. A signal with a logic "high" level can be distinguished from a signal with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage corresponds to a signal with a logic "low" level. In one embodiment, a logic "high" level can be set to a voltage level higher than that of a logic "low" level. Furthermore, according to embodiments, the logic levels of signals can be set to different or opposite levels. For example, a signal with a logic "high" level in one embodiment can be set to a logic "low" level in another embodiment.

[0022] The term "logic bit group" refers to a combination of logic levels of the bits included in a signal. The logic bit group of a signal can be set differently when the logic level of each bit in the signal changes. For example, in the case of a signal consisting of two bits, if the logic level of each of the two bits is "logic low, logic low", the logic bit group of the signal can be set as the first logic bit group; if the logic level of both bits in the signal is "logic low, logic high", the logic bit group of the signal can be set as the second logic bit group.

[0023] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0024] Figure 1 This is a block diagram illustrating the configuration of a semiconductor system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor system 1 may include a controller 11 and a semiconductor device 13.

[0025] The controller 11 may include a first control pin 11_1 and a second control pin 11_3. The semiconductor device 13 may include a first device pin 13_1 and a second device pin 13_3. The controller 11 may transmit an external control signal CA to the semiconductor device 13 via a first transmission line 12_1 connected between the first control pin 11_1 and the first device pin 13_1. In this embodiment, the external control signal CA may include commands and addresses, but this is merely an example and the disclosure is not limited thereto. Each of the first control pin 11_1, the first transmission line 12_1, and the first device pin 13_1 may be implemented as multiple depending on the number of bits of the external control signal CA. The controller 11 may transmit data DATA to the semiconductor device 13 via a second transmission line 12_3 connected between the second control pin 11_3 and the second device pin 13_3. The controller 11 may receive data DATA via the second transmission line 12_3 connected between the second control pin 11_3 and the second device pin 13_3.

[0026] Semiconductor device 13 may include address decoder (ADD DEC) 113, which decodes external control signal CA to generate a row address for row operations. Figure 2 RADD) and column addresses used for column operations ( Figure 2 (CADD). Row operations may include activation operations, and column operations may include read and write operations. Semiconductor device 13 may include a row decoder (ROW DEC) 115, which is based on row address ( Figure 2 RADD) to control the selection of memory cell arrays ( Figure 2 The row operation of at least one of the word lines included in 117).

[0027] Figure 2 This is a block diagram illustrating the configuration of a semiconductor device 13A according to an embodiment of the present disclosure. Figure 2 As shown, the semiconductor device 13A may include a command decoder (COM DEC) 111, an address decoder (ADD DEC) 113, a row decoder (ROWDEC) 115, a memory cell array (MA) 117, a column decoder (COL DEC) 119, an input / output buffer (I / O BUF) 121, and an input / output control circuit (I / O CNT) 123.

[0028] Command decoder 111 can generate an activation signal ACT, a read signal RD, and a write signal WT. Command decoder 111 can decode a command included in an external control signal CA to generate the activation signal ACT, read signal RD, and write signal WT. When the bits included in the external control signal CA have a first logical bit group, command decoder 111 can generate the activation signal ACT, which is activated in an activation operation. When the bits included in the external control signal CA have a second logical bit group, command decoder 111 can generate the read signal RD, which is activated in a read operation. When the bits included in the external control signal CA have a third logical bit group, command decoder 111 can generate the write signal WT, which is activated in a write operation. Each of the first, second, and third logical bit groups of the external control signal CA can be configured in various ways according to embodiments.

[0029] Address decoder 113 can decode external control signal CA to generate row address RADD for row operations and column address CADD for column operations. Row operations may include activation operations, and column operations may include read operations and write operations.

[0030] Row decoder 115 can select at least one word line included in memory cell array 117 based on row address RADD. Column decoder 119 can select at least one bit line included in memory cell array 117 based on column address CADD.

[0031] When a write operation is performed, input / output buffer 121 can buffer data DATA to generate global data GDQ. When a write operation is performed, input / output control circuit 123 can receive global data GDQ from input / output buffer 121. When a write operation is performed, input / output control circuit 123 can generate local data LDQ to be stored in memory cell array 117 from global data GDQ. When a read operation is performed, input / output control circuit 123 can generate global data GDQ from local data LDQ output from memory cell array 117. When a read operation is performed, input / output buffer 121 can receive global data GDQ from input / output control circuit 123. When a read operation is performed, input / output buffer 121 can buffer global data GDQ to output data DATA.

[0032] Figure 3 This is a diagram illustrating the configuration of a line decoder 115A according to an embodiment of the present disclosure. Figure 3 As shown, the line decoder 115A may include a voltage setting circuit 211, a word line selection signal generation circuit 213, and an address input circuit 215.

[0033] The voltage setting circuit 211 may include a first PMOS transistor 21_1 and a second PMOS transistor 21_2. The first PMOS transistor 21_1 may be connected between the supply terminal of the source power VP and the first node n11, and may be turned on based on the signal from the second node n12. The source power VP may be pumped from the controller ( Figure 1 The power applied by 11) is used to generate the second PMOS transistor 21_2. The second PMOS transistor 21_2 can be connected between the supply terminal of the source power VP and the second node n12, and can be turned on based on the signal of the first node n11. The voltage setting circuit 211 can initialize the signal of the second node n12 to a logic "low" level by the word line select signal WLSB initialized to a logic "high" level, and can initialize the signal of the first node n11 to a logic "high" level by the signal of the second node n12 at a logic "low" level. When the first to third bits of the row address with a preset logic bit group RADD<1:3> are input via the address input circuit 215, the voltage setting circuit 211 can drive the second node n12 to a logic "high" level by the first node n11 being driven to a logic "low" level.

[0034] The word line select signal generation circuit 213 may include a third PMOS transistor 21_3, a fourth NMOS transistor 23_1, and a fifth NMOS transistor 23_2. The third PMOS transistor 21_3 may be connected between the supply terminal of the source power VP and the fifth node n13, and may be turned on based on the signal from the second node n12. The fourth NMOS transistor 23_1 may be connected between the fifth node n13 and the supply terminal of the ground voltage VSS, and may be turned on based on the signal from the second node n12. The fifth NMOS transistor 23_2 may be connected between the second node n12 and the supply terminal of the ground voltage VSS, and may be turned on based on the signal from the fifth node n13. The word line select signal generation circuit 213 may drive the second node n12 to a logic "low" level via a word line select signal WLSB initialized to a logic "high" level. During initialization, the word line select signal WLSB may be driven to a logic "high" level via a reset signal (not shown). When the second node n12 is at a logic "low" level, the word line selection signal generation circuit 213 can drive the word line selection signal WLSB to a logic "high" level. When the first to third bits of the row address with a preset logic bit group RADD<1:3> are input via the address input circuit 215, the first node n11 is driven to a logic "low" level, and the second node n12 is driven to a logic "high" level, the word line selection signal generation circuit 213 can drive the word line selection signal WLSB to a logic "low" level. The word line selection signal WLSB driven to a logic "low" level can be used to select the row in the memory cell array ( Figure 2 At least one of the word lines included in (117). The word lines selected in the word line selection signal generation circuit 213 may include main word lines and sub-word lines. The word line selection signal generation circuit 213 can be used as a circuit for driving word lines.

[0035] Address input circuit 215 may include boost circuit (BST CIR) 217, first NMOS transistor 23_3, second NMOS transistor 23_4, and third NMOS transistor 23_5. Boost circuit 217 can boost the first bit RADD of the row address. <1> This generates the boost address BSTA. The boost address BSTA can be generated as RADD with the first bit of the row address higher than the row address. <1> A high voltage level. For example, boost circuit 217 can generate a voltage level that corresponds to the first bit of the row address. <1> The boost address BSTA has the same logic level. According to an embodiment, the boost circuit 217 can be implemented from the first bit RADD of the row address. <1> A boost address BSTA with inverted logic levels is generated. The first NMOS transistor 23_3 can be connected between the first node n11 and the third node n14, and can be turned on based on the boost address BSTA. For example, the first NMOS transistor 23_3 can be RADD at the first bit of the row address. <1> It is turned on when at a logic "high" level. The second NMOS transistor 23_4 can be connected between the third node n14 and the fourth node n15, and can be RADDed based on the second bit of the row address. <2> And it is turned on. For example, the second NMOS transistor 23_4 can be RADDed at the second bit of the row address. <2> It is turned on when at a logic "high" level. The third NMOS transistor 23_5 can be connected between the fourth node n15 and the supply terminal of ground voltage VSS, and can be RADDed based on the third bit of the row address. <3> And it is turned on. For example, the third NMOS transistor 23_5 can be RADD in the third bit of the row address. <3> It is turned on when it is at a logic "high" level.

[0036] The first NMOS transistor 23_3 can be formed to include a gate oxide layer thicker than that of the second NMOS transistor 23_4 and the third NMOS transistor 23_5, or to include a gate oxide layer having a higher dielectric constant than them. Because the threshold voltage of the first NMOS transistor 23_3 is set to be greater than the threshold voltage of each of the second NMOS transistor 23_4 and the third NMOS transistor 23_5, the leakage current generated in the turned-off first NMOS transistor 23_3 can be reduced. This is because the first NMOS transistor 23_3 is formed with a first bit RADD of the row address... <1> A high voltage level boost address BSTA enables conduction, ensuring sufficient gate voltage even in low-speed operation. Therefore, turn-on timing delays are prevented, and the timing difference between row and column operations is adequately ensured, preventing degradation of row and column operations. Low-speed operation states can include slow processing conditions, slave controller ( Figure 1 11) The voltage level of the supplied power is low and the temperature is low.

[0037] When the first to third bits of the row address, RADD<1:3>, have a preset logic bit group, the address input circuit 215 can drive the first node n11 to a logic "low" level. For example, in the preset logic bit group of the first to third bits of the row address, RADD<1:3>, the first bit of the row address... <1> The second bit of the row address (RADD) <2> The third bit of the row address (RADD) <3> All of them can be set to logic "high" level, but this is just an example and this disclosure is not limited thereto.

[0038] Figure 4 This is a diagram illustrating the configuration of a line decoder 115B according to another embodiment of the present disclosure. Figure 4 As shown, the line decoder 115B may include a first voltage setting circuit 221, a first word line selection signal generation circuit 223, a second voltage setting circuit 225, a second word line selection signal generation circuit 227, and an address input circuit 229.

[0039] The first voltage setting circuit 221 may include a first PMOS transistor 25_1 and a second PMOS transistor 25_2. The first PMOS transistor 25_1 may be connected between the supply terminal of the source power VP and the first node n21, and may be turned on based on the signal of the third node n22. The second PMOS transistor 25_2 may be connected between the supply terminal of the source power VP and the third node n22, and may be turned on based on the signal of the first node n21. The first voltage setting circuit 221 may initialize the signal of the third node n22 to a logic "low" level through the first word line select signal WLSB1, which is initialized to a logic "high" level, and may initialize the signal of the first node n21 to a logic "high" level through the logic "low" level signal of the third node n22. When the first to third bits of the row address having a preset first logic bit group RADD<1:3> are input via the address input circuit 229, the first voltage setting circuit 221 may drive the third node n22 to a logic "high" level through the first node n21, which is driven to a logic "low" level.

[0040] The first word line select signal generation circuit 223 may include a third PMOS transistor 25_3, a fifth NMOS transistor 27_1, and a sixth NMOS transistor 27_2. The third PMOS transistor 25_3 may be connected between the supply terminal of the source power VP and the seventh node n23, and may be turned on based on the signal from the third node n22. The fifth NMOS transistor 27_1 may be connected between the seventh node n23 and the supply terminal of the ground voltage VSS, and may be turned on by the signal from the third node n22. The sixth NMOS transistor 27_2 may be connected between the third node n22 and the supply terminal of the ground voltage VSS, and may be turned on based on the signal from the seventh node n23. The first word line select signal generation circuit 223 may drive the third node n22 to a logic "low" level via a first word line select signal WLSB1 initialized to a logic "high" level. During initialization, the first word line select signal WLSB1 may be driven to a logic "high" level by a reset signal (not shown). When the third node n22 is at a logic "low" level, the first word line selection signal generation circuit 223 can drive the first word line selection signal WLSB1 to a logic "high" level. When the first to third bits of the row address with a preset first logic bit group RADD<1:3> are input via the address input circuit 229, the first node n21 is driven to a logic "low" level, and the third node n22 is driven to a logic "high" level, the first word line selection signal generation circuit 223 can drive the first word line selection signal WLSB1 to a logic "low" level. The memory cell array can be selected by the first word line selection signal WLSB1 driven to a logic "low" level. Figure 2 At least one of the word lines included in 117).

[0041] The second voltage setting circuit 225 may include a fourth PMOS transistor 25_4 and a fifth PMOS transistor 25_5. The fourth PMOS transistor 25_4 may be connected between the supply terminal of the source power VP and the second node n24, and may be turned on based on the signal of the fourth node n25. The fifth PMOS transistor 25_5 may be connected between the supply terminal of the source power VP and the fourth node n25, and may be turned on based on the signal of the second node n24. The second voltage setting circuit 225 can initialize the signal of the fourth node n25 to a logic "low" level via the second word line select signal WLSB2, which is initialized to a logic "high" level, and can initialize the signal of the second node n24 to a logic "high" level via the logic "low" level signal of the fourth node n25. When the first to third bits of the row address having a preset second logic bit group RADD<1:3> are input via the address input circuit 229, the second voltage setting circuit 225 can drive the fourth node n25 to a logic "high" level via the second node n24, which is driven to a logic "low" level.

[0042] The second word line select signal generation circuit 227 may include a sixth PMOS transistor 25_6, a seventh NMOS transistor 27_3, and an eighth NMOS transistor 27_4. The sixth PMOS transistor 25_6 may be connected between the supply terminal of the source power VP and the eighth node n26, and may be turned on based on the signal from the fourth node n25. The seventh NMOS transistor 27_3 may be connected between the eighth node n26 and the supply terminal of the ground voltage VSS, and may be turned on based on the signal from the fourth node n25. The eighth NMOS transistor 27_4 may be connected between the fourth node n25 and the supply terminal of the ground voltage VSS, and may be turned on based on the signal from the eighth node n26. The second word line select signal generation circuit 227 may drive the fourth node n25 to a logic "low" level via a second word line select signal WLSB2 initialized to a logic "high" level. During initialization, the second word line select signal WLSB2 may be driven to a logic "high" level by a reset signal (not shown). When the fourth node n25 is at a logic "low" level, the second word line selection signal generation circuit 227 can drive the second word line selection signal WLSB2 to a logic "high" level. When the first to third bits of the row address with a preset second logic bit group RADD<1:3> are input via the address input circuit 229, the second node n24 is driven to a logic "low" level, and the fourth node n25 is driven to a logic "high" level, the second word line selection signal generation circuit 227 can drive the second word line selection signal WLSB2 to a logic "low" level. The memory cell array can be selected by the second word line selection signal WLSB2 driven to a logic "low" level. Figure 2At least one of the word lines included in 117).

[0043] Address input circuit 229 may include a first boost circuit (BST CIR(1)) 231, a second boost circuit (BSTCIR(2)) 233, a first NMOS transistor 27_5, a fourth NMOS transistor 27_6, a second NMOS transistor 27_7, and a third NMOS transistor 27_8.

[0044] The first boost circuit 231 can boost the first bit of the row address, RADD. <1> This generates the first boost address BSTA1. The first boost address BSTA1 can be generated as RADD with the first bit of the row address. <1> A high voltage level. For example, the first boost circuit 231 can generate a first bit RADD with the row address. <1> The first boost address BSTA1 with the same logic level.

[0045] The second boost circuit 233 can boost the first bit RADB of the inverted row address. <1> This generates the second boost address BSTA2. The first bit of the inverted row address RADB is then used. <1> This can be achieved by RADDing the first bit of the row address. <1> This is generated by inverting the row address. The second boost address BSTA2 can be generated as RADB, which has a higher first bit than the inverted row address. <1> A high voltage level. For example, the second boost circuit 233 can generate a first bit RADB with the inverted row address. <1> The second boost address BSTA2 has the same logic level.

[0046] The first NMOS transistor 27_5 can be connected between the first node n21 and the fifth node n27, and can be turned on based on the first boost address BSTA1. For example, when the first bit of the row address RADD <1> When at a logic "high" level, the first NMOS transistor 27_5 can be turned on by generating a first boost address BSTA1 with a logic "high" level. The fourth NMOS transistor 27_6 can be connected between the second node n24 and the fifth node n27, and can be turned on based on the second boost address BSTA2. For example, when the first bit of the inverted row address RADB... <1> When at a logic "high" level, the fourth NMOS transistor 27_6 can be turned on by generating a second boost address BSTA2 with a logic "high" level. The second NMOS transistor 27_7 can be connected between the fifth node n27 and the sixth node n28, and can be RADDed based on the second bit of the row address. <2> And it is turned on. For example, the second NMOS transistor 27_7 can be RADDed at the second bit of the row address. <2> It is turned on when at a logic "high" level. The third NMOS transistor 27_8 can be connected between the sixth node n28 and the supply terminal of ground voltage VSS, and can be RADDed based on the third bit of the row address. <3> And it is turned on. For example, the third NMOS transistor 27_8 can be RADD in the third bit of the row address. <3> It is turned on when it is at a logic "high" level.

[0047] Each of the first NMOS transistor 27_5 and the fourth NMOS transistor 27_6 can be formed to include a gate oxide layer thicker than each of the second NMOS transistor 27_7 and the third NMOS transistor 27_8, or can be formed to include a gate oxide layer having a higher dielectric constant than them. Because the threshold voltage of each of the first NMOS transistor 27_5 and the fourth NMOS transistor 27_6 can be set to be greater than the threshold voltage of each of the second NMOS transistor 27_7 and the third NMOS transistor 27_8, the leakage current generated in each of the turned-off first NMOS transistor 27_5 and the fourth NMOS transistor 27_6 can be reduced. The first NMOS transistor 27_5 can be generated to have a first bit RADD of the row address. <1> The first boost address BSTA1 is turned on by a high voltage level, and the fourth NMOS transistor 27_6 can be generated as the first bit RADB with a higher inverted row address. <1> The second boost address BSTA2 is turned on when the voltage level is high. Therefore, sufficient gate voltage can be ensured even in low-speed operation, thereby preventing turn-on timing delay and ensuring sufficient timing difference between row and column operations to prevent degradation of row and column operations.

[0048] When the first to third bits of the row address RADD<1:3> have a preset first logic bit group, the address input circuit 229 can drive the first node n21 to a logic "low" level. For example, in the preset first logic bit group of the first to third bits of the row address RADD<1:3>, the first bit of the row address RADD <1> The second bit of the row address (RADD) <2> The third bit of the row address (RADD) <3> All bits can be set to logic "high" level, but this is only an example and this disclosure is not limited thereto. When the first to third bits of the row address RADD<1:3> have a preset second logic bit group, the address input circuit 229 can drive the second node n24 to logic "low" level. For example, in the preset second logic bit group of the first to third bits of the row address RADD<1:3>, the first bit of the row address RADD <1> It can be set to a logic "low" level, and the second bit of the row address is RADD. <2> The third bit of the row address (RADD) <3> They can all be set to logic "high" level, but this is just an example and this disclosure is not limited thereto.

[0049] Figure 5 This is a diagram illustrating the configuration of a line decoder 115C according to yet another embodiment of the present disclosure. Figure 5 As shown, the line decoder 115C may include a source power generation circuit (VP GEN) 210, a voltage setting circuit 211A, a word line selection signal generation circuit 213A, and an address input circuit 215A.

[0050] The source power generation circuit 210 can generate source power VP based on a temperature voltage VTEMP and a reference voltage VREF. The temperature voltage VTEMP can be configured to have a voltage level that varies with temperature. For example, the temperature voltage VTEMP can be configured to have a voltage level that increases as the temperature decreases and a voltage level that decreases as the temperature increases. The reference voltage VREF can be configured to have a voltage level that divides the temperature voltage VTEMP into low-temperature and high-temperature states. For example, in the low-temperature state, the temperature voltage VTEMP can be configured to have a voltage level higher than the reference voltage VREF, and in the high-temperature state, the temperature voltage VTEMP can be configured to have a voltage level lower than or equal to the reference voltage VREF. The source power generation circuit 210 can generate source power VP with a higher voltage level in the low-temperature state than in the high-temperature state. (See below for further details.) Figures 6 to 8 A more detailed description of the configuration and operation of the source power generation circuit 210 is provided.

[0051] Because the voltage setting circuit 211A, the word line selection signal generation circuit 213A, and the address input circuit 215A can be respectively connected to... Figure 3 The voltage setting circuit 211, word line selection signal generation circuit 213, and address input circuit 215 shown are implemented in the same manner, so a detailed description of their configuration and operation will be omitted here.

[0052] The row decoder 115C may include a source power generation circuit 210 to drive word lines at low temperatures based on a source power level that is higher than the voltage level at high temperatures. Therefore, it also has the effect of preventing degradation of row and column operations at low temperatures by adequately ensuring the timing difference between row and column operations.

[0053] Figure 6 This is a diagram illustrating a source power generation circuit 210A according to an embodiment of the present disclosure. Figure 6 As shown, the source power generation circuit 210A may include a comparator 311, inverters 313 and 315, and PMOS transistors 317 and 319.

[0054] Comparator 311 compares the temperature voltage VTEMP with the reference voltage VREF to generate a comparison signal COM. When the temperature voltage VTEMP is higher than the reference voltage VREF at a low temperature, comparator 311 generates a logic "high" comparison signal COM. When the temperature voltage VTEMP is equal to or less than the reference voltage VREF at a high temperature, comparator 311 generates a logic "low" comparison signal COM.

[0055] Inverter 313 can invert and buffer the comparator signal COM to generate a first switching signal SW1. Inverter 315 can invert and buffer the first switching signal SW1 to generate a second switching signal SW2. PMOS transistor 317 can be turned on based on the first switching signal SW1 to drive the source power VP to the first source power VP1. PMOS transistor 319 can be turned on based on the second switching signal SW2 to drive the source power VP to the second source power VP2. The first source power VP1 can be set to have a higher voltage level than the second source power VP2. For example, the second source power VP2 can be set to be driven from the controller (…). Figure 1 11) The power supply voltage (not shown) is supplied, and the first source power VP1 can be set to a voltage level higher than the power supply voltage (not shown) and lower than the temperature voltage VTEMP. Because PMOS transistor 317 is turned on at a low temperature to drive the source power VP to the first source power VP1, while PMOS transistor 319 is turned on at a high temperature to drive the source power VP to the second source power VP2, the source power VP can be driven to a higher voltage level at a low temperature compared to at a high temperature.

[0056] Figure 7 and Figure 8 It is a diagram. Figure 6 The circuit diagram shown illustrates the operation of the power source generating circuit 210A. The operation of the power source generating circuit 210A is divided into operation at low temperature and operation at high temperature, and reference will be used... Figure 7 and Figure 8 The description is as follows.

[0057] like Figure 7 As shown, because the temperature voltage VTEMP has a higher voltage level than the reference voltage VREF at low temperatures, the comparator signal COM can be generated as a logic "high" level 'H', the first switch signal SW1 can be generated as a logic "low" level 'L', and the second switch signal SW2 can be generated as a logic "high" level 'H'. Because the PMOS transistor 317 is turned on by the logic "low" level first switch signal SW1, the source power VP can be driven to the first source power VP1.

[0058] like Figure 8 As shown, because the temperature voltage VTEMP has a voltage level equal to or less than the reference voltage VREF at high temperatures, the comparator signal COM can be generated as a logic "low" level 'L', the first switch signal SW1 can be generated as a logic "high" level 'H', and the second switch signal SW2 can be generated as a logic "low" level 'L'. Because the PMOS transistor 319 is turned on by the logic "low" level second switch signal SW2, the source power VP can be driven to the second source power VP2.

[0059] Figure 9 This is a diagram illustrating the configuration of a line decoder 115D according to yet another embodiment of the present disclosure. Figure 9 As shown, the line decoder 115D may include a source power generation circuit (VP GEN) 220, a first voltage setting circuit 221A, a first word line selection signal generation circuit 223A, a second voltage setting circuit 225A, a second word line selection signal generation circuit 227A, and an address input circuit 229A.

[0060] The source power generation circuit 220 can generate source power VP based on a temperature voltage VTEMP and a reference voltage VREF. The temperature voltage VTEMP can be configured to have a voltage level that varies with temperature. For example, the temperature voltage VTEMP can be configured to have a voltage level that increases as the temperature decreases and a voltage level that decreases as the temperature increases. The reference voltage VREF can be configured to have a voltage level that divides the temperature voltage VTEMP into low-temperature and high-temperature states. For example, in the low-temperature state, the temperature voltage VTEMP can be configured to have a voltage level higher than the reference voltage VREF, and in the high-temperature state, the temperature voltage VTEMP can be configured to have a voltage level lower than or equal to the reference voltage VREF. Compared to the high-temperature state, the source power generation circuit 210 can generate source power VP with a higher voltage level in the low-temperature state.

[0061] Because the first voltage setting circuit 221A, the first word line selection signal generation circuit 223A, the second voltage setting circuit 225A, the second word line selection signal generation circuit 227A, and the address input circuit 229A can be respectively connected to... Figure 3 The voltage setting circuit 211, the first word line selection signal generation circuit 223, the second voltage setting circuit 225, the second word line selection signal generation circuit 227, and the address input circuit 229 shown are implemented in the same way, so a detailed description of the configuration and operation will be omitted here.

[0062] The row decoder 115D may include a source power generation circuit 220 to drive word lines based on a source power that has a higher voltage level at low temperatures than at high temperatures. Therefore, it also has the effect of preventing degradation of row and column operations by adequately ensuring the timing difference between row and column operations at low temperatures.

[0063] The above is for reference only. Figure 1 Semiconductor devices described 13 and above reference Figure 2 The described semiconductor device 13A can be applied to electronic systems including storage systems, graphics systems, computing systems, or mobile systems. For example, see reference... Figure 10 The electronic system 1000 according to the embodiments of the present disclosure may include a data storage unit 1001, a memory controller 1002, a buffer memory 1003, and an input / output interface 1004.

[0064] Data storage unit 1001 can store data applied from memory controller 1002 according to control signals from memory controller 1002, and read the stored data to output the data to memory controller 1002. Data storage unit 1001 may include the above-mentioned references. Figure 1The semiconductor device described in 13 or the above reference Figure 2 The semiconductor device 13A is described. Furthermore, the data storage unit 1001 may include non-volatile memory that can continuously store data without data loss even when power is off. The non-volatile memory can be implemented using flash memory devices such as NOR flash memory and NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-torque random access memory (STTRAM), and magnetic random access memory (MRAM).

[0065] The memory controller 1002 can decode commands issued from an external device (host device) via the input / output interface 1004, and control the data input / output of the data storage unit 1001 and the buffer memory 1003 based on the decoding result. Although the memory controller 1002... Figure 10 While shown as a single block, the memory controller 1002 may independently include a controller for controlling the data storage unit 1001 and a controller for controlling the buffer memory 1003 (which is volatile memory). The memory controller 1002 may include the components referenced above. Figure 1 The controller 11 is described.

[0066] Buffer memory 1003 can temporarily store data to be processed by memory controller 1002, that is, data input / output to / from data storage unit 1001. Buffer memory 1003 can store data DATA applied from memory controller 1002 according to control signals. Buffer memory 1003 can read the stored data and output it to memory controller 1002. Buffer memory 1003 may include volatile memory, such as dynamic random access memory (DRAM), mobile DRAM, or static random access memory (SRAM).

[0067] The input / output interface 1004 provides a physical connection between the memory controller 1002 and an external device (host), enabling the memory controller 1002 to receive control signals for data input / output from the external device and exchange data with the external device. The input / output interface 1004 may include one of various interface protocols, such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, or IDE.

[0068] Electronic system 1000 can be used as an auxiliary storage device or external storage device for host devices. Electronic system 1000 may include solid-state drives (SSDs), universal serial bus memory, secure digital cards (SDs), mini secure digital cards (mSDs), micro secure digital cards (microSDs), secure digital high capacity (SDHC) cards, memory sticks, smart media cards (SMs), multimedia cards (MMCs), embedded MMCs (eMMCs), or compact flash memory (CFs), etc.

[0069] Figure 11 This is a block diagram illustrating the configuration of an electronic system 2000 according to another embodiment of the present disclosure. Figure 11 As shown, the electronic system 2000 may include a host 2100 and a semiconductor system 2200.

[0070] The host 2100 and the semiconductor system 2200 can send signals to each other using an interface protocol. The interface protocol used between the host 2100 and the semiconductor system 2200 may include Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect (PCI-E), Advanced Technology Accessories (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), or Universal Serial Bus (USB), etc.

[0071] Semiconductor system 2200 may include controller 2300 and semiconductor devices 2400 (1:K). Controller 2300 can control semiconductor devices 2400 (1:K) to perform activation, read, and write operations. Each of semiconductor devices 2400 (1:K) can be boosted via a boost circuit ( Figure 3 217, Figure 4 The boost address generated by 231 and 233) Figure 3 BSTA, Figure 4 BSTA1 and BSTA2) are applied to the address input circuit ( Figure 3 215, and Figure 4 229) NMOS transistor ( Figure 3 23_3、 Figure 4 (27_5 and 27_6), so that even MOS transistors ( Figure 3 23_3, Figure 4 The threshold voltages of 27_5 and 27_6) increase due to the boost address ( Figure 3 BSTA, Figure 4 Even with BSTA1 and BSTA2, the turn-on timing of the MOS transistor can still be prevented from being delayed, and the timing difference between row operations and column operations can be fully guaranteed to prevent the degradation of row operations and column operations.

[0072] Controller 2300 can be implemented as described above. Figure 1 The controller 11 is described. Each of the semiconductor devices 2400 (1:K) can be implemented as described above. Figure 1 The semiconductor device described in 13 or the above reference Figure 2 Semiconductor device 13A is described. Each of the semiconductor devices 2400 (1:K) can be implemented using one of dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).

[0073] The concept has been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictively but rather illustratively. The scope of the concept is not limited to the foregoing description but is defined by the appended claims, and all distinguishing features within the equivalent scope should be interpreted as being included in the concept.

Claims

1. A semiconductor device, comprising: An address input circuit that raises the voltage level of at least one bit of a row address to generate a boost address, and a signal that drives the first node based on the other bits of the row address and the boost address; and A word line selection signal generation circuit drives a signal of a second node based on a signal of the first node, and generates a word line selection signal for selecting a word line based on a signal of the second node. It also includes a voltage setting circuit, wherein the voltage setting circuit: The signal of the second node is driven based on the signal of the first node; as well as The signal of the first node is driven by the signal of the second node.

2. The semiconductor device according to claim 1, wherein, The address input circuit generates the boost address as a voltage level that is at least one bit higher than the row address.

3. The semiconductor device according to claim 1, wherein, The row address includes the first bit, the second bit, and the third bit, and The address input circuit includes: A boost circuit that raises the first bit of the row address to generate the boost address; and The first NMOS transistor is turned on based on the boost address.

4. The semiconductor device according to claim 3, wherein, The first NMOS transistor is connected between the first node and the third node. The address input circuit further includes a second NMOS transistor and a third NMOS transistor connected in series between the third node and the ground voltage supply terminal. The second NMOS transistor is turned on based on the second bit of the row address, and The third NMOS transistor is turned on based on the third bit of the row address.

5. The semiconductor device according to claim 4, wherein, The first NMOS transistor includes at least one of the following: The gate oxide layer is thicker than that of each of the second and third NMOS transistors; and A gate oxide layer having a higher dielectric constant than each of the second and third NMOS transistors.

6. The semiconductor device according to claim 1, wherein, The word line selection signal generation circuit: The word line selection signal is driven based on the signal from the second node; and The second node is initialized based on the word line selection signal.

7. The semiconductor device according to claim 1, further comprising: A source power generating circuit generates source power, which has a higher voltage level at low temperatures compared to at high temperatures.

8. The semiconductor device according to claim 7, wherein, The word line selection signal generation circuit drives the word line selection signal to the source power based on the signal from the second node.

9. A semiconductor device, comprising: An address input circuit generates a first boost address and a second boost address based on at least one bit of a row address, drives a signal for a first node based on other bits of the row address and the first boost address, and drives a signal for a second node based on other bits of the row address and the second boost address. The first word line selection signal generation circuit drives the signal of the third node based on the signal of the first node, and generates a first word line selection signal for selecting the first word line based on the signal of the third node. and The second word line selection signal generation circuit drives the signal of the fourth node based on the signal of the second node, and generates a second word line selection signal for selecting the second word line based on the signal of the fourth node.

10. The semiconductor device according to claim 9, wherein, The address input circuit generates the first boost address and the second boost address as voltage levels that are each higher than at least one bit of the row address.

11. The semiconductor device according to claim 9, wherein, The row address includes the first bit, the second bit, and the third bit, and The address input circuit includes: A first boost circuit increases the first bit of the row address to generate the first boost address; and The first NMOS transistor is turned on based on the first boost address.

12. The semiconductor device according to claim 11, in, The first NMOS transistor is connected between the first node and the fifth node. The address input circuit further includes a second NMOS transistor and a third NMOS transistor connected in series between the fifth node and the ground voltage supply terminal. The second NMOS transistor is turned on based on the second bit of the row address, and The third NMOS transistor is turned on based on the third bit of the row address.

13. The semiconductor device according to claim 12, wherein, The first NMOS transistor includes at least one of the following: The gate oxide layer is thicker than that of each of the second and third NMOS transistors; and A gate oxide layer having a higher dielectric constant than each of the second and third NMOS transistors.

14. The semiconductor device according to claim 9, wherein, The row address includes the first bit, the second bit, and the third bit, and The address input circuit includes: A second boost circuit generates a second boost address by boosting the first bit of an inverted row address obtained by inverting and buffering the first bit of the row address; and The fourth NMOS transistor is turned on based on the second boost address.

15. The semiconductor device according to claim 14, wherein, The fourth NMOS transistor is connected between the second node and the fifth node, and The address input circuit further includes a second NMOS transistor and a third NMOS transistor connected in series between the fifth node and the ground voltage supply terminal. The second NMOS transistor is turned on based on the second bit of the row address, and The third NMOS transistor is turned on based on the third bit of the row address.

16. The semiconductor device of claim 9, further comprising a first voltage setting circuit, wherein the first voltage setting circuit: The signal of the third node is driven based on the signal of the first node; and The signal of the first node is driven by the signal of the third node.

17. The semiconductor device of claim 9, further comprising a second voltage setting circuit, wherein the second voltage setting circuit: The signal of the fourth node is driven based on the signal of the second node; and The signal of the second node is driven based on the signal of the fourth node.

18. The semiconductor device according to claim 9, wherein, First word line selection signal generation circuit: The first word line selection signal is driven based on the signal from the third node; and The third node is initialized based on the first word line selection signal.

19. The semiconductor device according to claim 9, wherein, Second word line selection signal generation circuit: The second word line selection signal is driven based on the signal from the fourth node; and The fourth node is initialized based on the second word line selection signal.

20. The semiconductor device of claim 9 further includes a source power generating circuit that generates source power having a higher voltage level at a low temperature compared to at a high temperature.

21. The semiconductor device according to claim 20, wherein, The first word line selection signal generation circuit drives the first word line selection signal to the source power based on the signal of the third node.

22. A semiconductor system, comprising: The controller outputs external control signals; and Semiconductor device, the semiconductor device: Increase the voltage level of at least one bit of the row address generated based on the external control signal to generate a boost address. The signal that drives the first node is based on the other bits of the row address and the boost address. The signal of the second node is driven by the signal of the first node. The signal of the first node is driven based on the signal of the second node, and The word line selection signal for selecting word lines is generated based on the signal from the second node.

23. The semiconductor system of claim 22, wherein, The controller applies the external control signal to the semiconductor device, and The semiconductor device decodes the external control signal to generate an activation signal for row operation and the row address.

Images