Self-refresh 10t-sram cell, array structure, and in-memory operation full-array activation circuit

Abstract

The present application relates to the technical field of dynamic random access memory, more particularly, to a self-back 10T-SRAM unit, an array structure constructed based on the self-back 10T-SRAM unit, and an in-memory operation full-array activation circuit constructed based on the array structure. The self-back 10T-SRAM unit provided by the present application controls the conduction and turn-off of each transistor to perform charging and discharging in the unit by multiplexing the power supply end and the ground end. Not only can various in-memory operations be performed, but also the operation results can be automatically stored without additional area and power consumption overheads, and the application scenarios are more extensive. Moreover, the inputs of two operators are independent of each other, which is more flexible than the traditional structure.

Description

Technical Field

[0001] This invention relates to the field of dynamic random access memory technology, and more specifically, to a self-recall 10T-SRAM cell, an array structure built based on the self-recall 10T-SRAM cell, and an in-memory operation full array activation circuit built based on the array structure. Background Technology

[0002] With breakthroughs in key technologies such as big data and artificial intelligence, the traditional von Neumann architecture, which separates computing and storage, can no longer meet the demands of frequent data access. Computing in memory (CIM) technology breaks down the "memory wall" of the traditional von Neumann architecture, eliminating the need for frequent data exchange between memory and the ALU (arithmetic logic unit), significantly reducing chip power consumption and latency.

[0003] SRAM-CIM (Static Random Access Memory-computing in memory) offers faster write speeds and lower write energy, along with greater durability, making it suitable for small to medium capacity systems and configurable into a wider range of neural networks.

[0004] However, existing traditional storage units cannot store the results of in-memory calculations, requiring additional memory space to store the results, thus resulting in additional area and power consumption overhead; and the current calculation strategy can only activate two rows at a time, resulting in low throughput. Summary of the Invention

[0005] Therefore, it is necessary to address the issue that existing traditional storage units require additional memory space to store computation results, resulting in additional area and power consumption overhead. This necessitates providing a self-recall 10T-SRAM unit and an in-memory computation full array activation circuit.

[0006] This invention is achieved using the following technical solution:

[0007] In a first aspect, the present invention provides a self-recall 10T-SRAM cell, comprising 3 PMOS transistors and 7 NMOS transistors. The 3 PMOS transistors are designated as M1, M2, and M4, and the 7 NMOS transistors are designated as M3, M5, M6, M7, M8, M9, and M10.

[0008] The source of M1 is connected to input IN1. Input IN1 is used to connect to VDD or VSS. The source of M2 is connected to VDD. The drain of M3 is connected to the drain of M1 and has a memory node Q. The gate is connected to the calculation control terminal CN. The source of M4 is connected to the drain of M2 and the gate is connected to the calculation control terminal RCN. The drain of M5 is connected to the gate of M1 and the gate is connected to the calculation control terminal CL. The drain of M6 is connected to the gate of M2 and the gate is connected to the calculation control terminal RCL. The drain of M7 is connected to the source of M3, the gate is connected to the source of M5, and the source is connected to input IN2. Input IN2 is used to connect to VDD or VSS. The drain of M8 is connected to the source of M4 and has a memory node QB. The gate is connected to the source of M6 and the source is connected to the floating terminal FL. The floating terminal FL is used to float the source of M8 or connect it to VSS. The source of M9 is connected to the bit line BL, the gate is connected to the word line WL, and the drain is connected to the drain of M1 and the gate of M2. The source of M10 is connected to the bit line BLB, the gate is connected to WL, and the drain is connected to the drain of M8 and the gate of M7. BL and BLB are used for writing and reading data.

[0009] In operation mode, the self-recall 10T-SRAM unit performs in-memory operations on operator one and operator two; M1, M3, M5, M7, and M9 constitute operation unit one, and M2, M4, M6, M8, and M10 constitute operation unit two. CN and CL control operation unit one, and RCN, RCL, and FL control operation unit two.

[0010] The first operator is input into the self-recall 10T-SRAM unit through IN1 and IN2; the second operator is obtained based on the values ​​of Q and QB at the beginning of the current operation; Q and QB are also used to recall the final result of the current operation.

[0011] This self-recall 10T-SRAM cell is implemented according to the method or process of an embodiment of this disclosure.

[0012] Secondly, this invention discloses a 10T-SRAM cell array structure, including 2 i ×2 i Individual, arrayed self-recall 10T-SRAM cells as disclosed in the first aspect; i>0.

[0013] Among them, the self-recall 10T-SRAM cells located in the same row share the same IN1, the same IN2, the same WL, the same FL, the same CN, the same CL, the same RCN, and the same RCL;

[0014] Self-recall 10T-SRAM cells located in the same column share the same bit line WBL and the same bit line WBLB.

[0015] The implementation of this 10T-SRAM cell array structure is based on the method or process of an embodiment of this disclosure.

[0016] Thirdly, the present invention discloses an in-memory operation full array activation circuit, including a 10T-SRAM cell array structure, an operator one input circuit, an operator two input circuit, a mode module circuit, a data output circuit, and a timing control circuit.

[0017] The operator one input circuit is used to input operator one to the 10T-SRAM cell array structure via IN1 and IN2. The operator two input circuit is used to input operator two to the 10T-SRAM cell array structure via BL and BLB. The mode module circuit is used to input CN, CL, RCN, RCL, and FL to the 10T-SRAM cell array structure. The data output circuit is used to read data based on the voltage difference between BL and BLB. The timing control circuit is used to control the timing of BL, BLB, IN1, IN2, CN, CL, RCN, RCL, and FL.

[0018] The implementation of this in-memory operation full array activation circuit is based on the method or process of an embodiment of this disclosure.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The self-recall 10T-SRAM cell provided by this invention uses a multiplexed power supply and ground terminal to control the conduction and shutdown of each transistor in coordination, enabling charging and discharging within the cell. It not only supports various in-memory operations but also automatically recalls the operation results without requiring additional area or power consumption overhead, thus broadening its application scenarios. Furthermore, the inputs of the two operators are independent, making it more flexible than traditional structures.

[0021] 2. The array structure provided by the present invention can be controlled by a timing control circuit to activate the entire array and perform various logic operations. The operation data can be independent of each other, allowing the entire array to operate on different data simultaneously, which greatly improves the throughput. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 The circuit structure diagram of the self-recall 10T-SRAM cell provided in Embodiment 1 of the present invention is shown below.

[0024] Figure 2 for Figure 1 A schematic diagram of the self-recall 10T-SRAM cell reading data "1";

[0025] Figure 3 for Figure 1 A schematic diagram of writing data "1" into a self-recall 10T-SRAM cell;

[0026] Figure 4 for Figure 1 A schematic diagram of a 1AND1=1 operation performed in a self-recall 10T-SRAM cell;

[0027] Figure 5 for Figure 1 A schematic diagram of a 10T-SRAM cell performing a 0OR0=0 operation;

[0028] Figure 6 for Figure 1 A schematic diagram of a 10T-SRAM cell performing a 1IMP0=0 operation;

[0029] Figure 7 for Figure 1 A schematic diagram of a 10T-SRAM cell performing a 1XOR 0 = 1 operation;

[0030] Figure 8 This is a circuit diagram of the 10T-SRAM cell array structure provided in Embodiment 2 of the present invention;

[0031] Figure 9 This is a circuit structure diagram of the in-memory operation full array activation circuit provided in Embodiment 2 of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] Example 1

[0036] See Figure 1 This is a circuit structure diagram of the self-recall 10T-SRAM cell provided in Embodiment 1. In general, the self-recall 10T-SRAM cell includes 10 MOS transistors, including 3 PMOS transistors (M1, M2, M4) and 7 NMOS transistors (M3, M5, M6, M7, M8, M9, M10).

[0037] Combination Figure 1 The connection relationships are explained one by one: The source of M1 is connected to the input terminal IN1. Input terminal IN1 is used to connect to VDD or VSS. The source of M2 is connected to VDD. The drain of M3 is connected to the drain of M1 and has a storage node Q; its gate is connected to the computation control terminal CN. The source of M4 is connected to the drain of M2, and its gate is connected to the computation control terminal RCN. The drain of M5 is connected to the gate of M1, and its gate is connected to the computation control terminal CL. The drain of M6 is connected to the gate of M2, and its gate is connected to the computation control terminal RCL. The drain of M7 is connected to the source of M3, its gate is connected to the source of M5, and its source is connected to the input terminal IN2. Input terminal IN2 is used to connect to VDD or VSS. The drain of M8 is connected to the source of M4 and has a storage node QB; its gate is connected to the source of M6, and its source is connected to the floating terminal FL. The floating terminal FL is used to float the source of M8 or connect it to VSS. The source of M9 is connected to the bit line BL, the gate is connected to the word line WL, and the drain is connected to the drain of M1 and the gate of M2. The source of M10 is connected to the bit line BLB, the gate is connected to WL, and the drain is connected to the drain of M8 and the gate of M7. BL and BLB are used for writing and reading data.

[0038] The self-recall 10T SRAM cell, as a storage unit capable of in-memory operations, has both storage and operation modes. In storage mode, read and write operations are possible. In operation mode, AND, OR, IMP, and XOR operations can be performed on operators one and two.

[0039] (I) Explanation of the principles of storage mode:

[0040] 1.1 The read operation involves obtaining the voltage difference between BL and BLB to reflect the data being read.

[0041] See Figure 2This is a schematic diagram for reading the data "1". During the data reading stage, if the data stored in the cell is '1', that is, "Q=1, QB=0"; CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS, BL and BLB are precharged to high level (i.e., BL=1, BLB=1), WL=1.

[0042] In this way, M6, M9, and M10 are turned on; BL and Q are connected through M9. Since BL and Q are both 1, they remain unchanged; Q pulls up the gate level of M8 through M6 and turns on M8; BLB discharges through M8 and M10; BL and BLB generate a voltage difference.

[0043] Similarly, during the data reading phase, if the data stored in the cell is '0', i.e. "Q=0, QB=1"; CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS, BL and BLB are precharged to high level (i.e. BL=1, BLB=1), and WL=1.

[0044] In this way, M6, M9, and M10 are turned on; since BL is 1 and Q is 0, BL discharges to Q through M9; BLB and QB are connected through M10, and since BLB is 1 and QB is 1, they remain unchanged; a voltage difference is generated between BL and BLB.

[0045] 1.2 The write operation is to store data in Q and QB.

[0046] See Figure 3 This is a schematic diagram of writing data "1". During the data writing stage, when the data to be written is "1", CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS; BL precharge is high level (BL=1), BLB precharge is low level (BLB=0), WL=1.

[0047] When M10 is turned on, BLB and QB are connected via M10; when M9 is turned on, BL and Q are connected via M9. If the data previously stored in the cell is '0', i.e., "Q=0, QB=1", QB discharges to BLB through M10, and BL charges Q through M9, changing QB from 1 to 0 and Q from 0 to 1, completing the data flip-write. If the data previously stored in the cell is '1', i.e., "Q=1, QB=0", Q and QB remain unchanged.

[0048] Similarly, during the data writing phase, when the data being written is "0", CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS; BL precharge is low (BL=0), BLB precharge is high (BLB=1), WL=1.

[0049] When M10 is open, BLB and QB are connected via M10; when M9 is open, BL and Q are connected via M9. If the data previously stored in the cell is '1', i.e., "Q=1, QB=0", Q discharges to BL through M9, and BLB charges QB through M10. QB changes from 0 to 1, and Q changes from 1 to 0, completing the data flip-write. If the data previously stored in the cell is '0', i.e., "Q=0, QB=1", Q and QB remain unchanged.

[0050] (II) Explanation of the principles of the operation mode:

[0051] In operation mode, the self-recall 10T-SRAM cell performs in-memory operations on operator one and operator two. M1, M3, M5, M7, and M9 constitute operation unit one, and M2, M4, M6, M8, and M10 constitute operation unit two. CN and CL control operation unit one, and RCN, RCL, and FL control operation unit two.

[0052] Operator 1 is input into the self-recall 10T-SRAM unit via IN1 and IN2; Operator 2 is obtained based on the values ​​of Q and QB at the start of the current operation; Q and QB are also used to recall the final result of the current operation.

[0053] If we define the current iteration as the nth iteration, then Q and QB store Q when the operation begins at the nth iteration. n QB n Q n QB n It can be the result of the (n-1)th operation, or the data input by BL and BLB. It is determined according to the operation requirements of the nth operation: compare the operator 2 corresponding to the result of the (n-1)th operation with the operator 2 required by the nth operation. If they are the same, the result of the (n-1)th operation can be used directly; if they are different, the required operator 2 needs to be input to Q and QB through BL and BLB.

[0054] After the nth operation, the final result is defined as Q. n+1 QB n+1 Then save it back to Q and QB.

[0055] In summary, the method for performing in-memory operations in a self-recall 10T-SRAM cell includes the following steps:

[0056] Step 1: The arithmetic unit performs calculations and makes Q the target value 1; M4, M6, M9, and M10 are turned off.

[0057] Step 2: The 10T-SRAM cell is stored in a hold state; M3, M4, M5, M6, M9, and M10 are turned off.

[0058] Step 3: The second arithmetic unit performs calculations and transforms QB into the target value 2; wherein, M3, M5, M9, and M10 are turned off.

[0059] Step four: The 10T-SRAM cell is latched after self-recall; M9 and M10 are turned off.

[0060] If we take Figure 1 The direction of the operation unit is the left half; the operation unit is the right half.

[0061] 2.1 For the AND operation, there are 4 cases: 1 AND 1 = 1, and the rest result is 0. The specific truth table is shown in Table 1.

[0062] Table 1 Truth Table for AND Operation

[0063]

[0064] For operator one, the rule is set as follows:

[0065] When operator 1 is 1, it corresponds to IN1 being connected to VDD and IN2 being connected to VSS; when operator 1 is 0, it corresponds to IN1 being connected to VSS and IN2 being connected to VSS.

[0066] For operator two, the rule is set as follows:

[0067] When operator two is 1, it corresponds to Q. n =1, QB n =0; when the operator two is 0, it corresponds to Q. n =0, QB n =1.

[0068] Figure 4 This demonstrates the specific operation of 1AND1=1 in the current iteration. The initial conditions for the operation are set as follows: IN1 is connected to VDD, IN2 is connected to VSS, i.e., operator one is 1; Q=1, QB=0, i.e., operator two is 1; WL=0, and M9 and M10 are always closed.

[0069] Step 1: Calculate the left half. CL=1, CN=1, M3 and M5 are both on; RCL=0, RCN=1, M4 and M6 are both off.

[0070] QB pulls down the gate level of M1 through M5 and turns M1 on, so IN1 charges Q through M1, and Q=1.

[0071] In the second step, CL=0, CN=0, and both M3 and M5 are turned off. M4 and M6 remain off, thus putting the circuit into a hold state, with the values ​​of Q and QB remaining unchanged.

[0072] In the third step, RCL=1, RCN=0, and both M4 and M6 are turned on. Although Q will pull up the gate level of M8 through M6, turning on M8, QB=0, FL remains floating, and QB also remains 0.

[0073] In the fourth step, CL=1, CN=1, RCL=1, RCN=0, M3, M4, M5, and M6 are all turned on, and the circuit enters the latching state: IN1 charges Q through M1, keeping Q at 1; QB remains at 0.

[0074] Thus, we finally obtain Q = 1 and QB = 0. The result can then be read using the read mode: 1 AND 1 = 1.

[0075] The other three scenarios follow similar steps to the one described above, and will not be repeated here.

[0076] 2.2 For the OR operation, there are 4 cases: 0 OR 0 = 0, and the rest are 1. The specific truth table is shown in Table 2.

[0077] Table 2: Truth Table for OR Operation

[0078]

[0079] For operator one, the rule is set as follows:

[0080] When operator 1 is 1, it corresponds to IN1 being connected to VDD and IN2 being connected to VDD; when operator 1 is 0, it corresponds to IN1 being connected to VDD and IN2 being connected to VSS.

[0081] For operator two, the rule is set as follows:

[0082] When operator two is 1, it corresponds to Q. n =1, QB n =0; when the operator two is 0, it corresponds to Q. n =0, QB n =1.

[0083] Figure 5 This demonstrates the specific operation details of the current 0OR0=0 operation. The initial conditions for the operation are set as follows: IN1 is connected to VDD, IN2 is connected to VSS, meaning operator one is 0; Q=0, QB=1, meaning operator two is 0; WL=0, and M9 and M10 are always closed.

[0084] Step 1: Calculate the left half. CL=1, CN=1, M3 and M5 are both on; RCL=0, RCN=1, M4 and M6 are both off.

[0085] Since QB=1, M7 is turned on; Q discharges through M3 and M7 to IN2, so Q=0.

[0086] In the second step, CL=0, CN=0, and both M3 and M5 are turned off. M4 and M6 remain off, thus putting the circuit into a hold state, with the values ​​of Q and QB remaining unchanged.

[0087] Third step, RCL=1, RCN=0, both M4 and M6 are turned on. Since Q=0, M2 is turned on; VDD charges QB through M2 and M4, QB=1.

[0088] In the fourth step, CL=1, CN=1, RCL=1, RCN=0, M3, M4, M5, and M6 are all turned on, and the circuit enters the latching state: Q discharges IN2 through M3 and M7, and Q remains at 0; VDD charges QB through M2 and M4, and QB remains at 1.

[0089] Thus, we finally obtain Q=0 and QB=1. The result of the operation can then be read out by reading the mode as: 0OR0=0.

[0090] In other cases, the steps are similar to those above, and will not be repeated here.

[0091] 2.3 For the IMP operation, there are 4 cases: 1. IMP0 = 0, and the rest are 1. The specific truth table is shown in Table 3.

[0092] Table 3 Truth Table of IMP Operation

[0093]

[0094] For operator one, the rule is set as follows:

[0095] When operator 1 is 1, it corresponds to IN1 being connected to VSS and IN2 being connected to VDD; when operator 1 is 0, it corresponds to IN1 being connected to VDD and IN2 being connected to VDD.

[0096] For operator two, the rule is set as follows:

[0097] When operator two is 1, it corresponds to Q. n =0, QB n =1; when operator two is 0, it corresponds to Q. n =1, QB n =0.

[0098] Figure 6This demonstrates the specific operation details of the current iteration of 1IMP0=0. The initial conditions for the operation are set as follows: IN1 is connected to VSS, IN2 is connected to VDD, meaning operator one is 1; Q=1, QB=0, meaning operator two is 0; WL=0, and M9 and M10 are always closed.

[0099] Step 1: Calculate the left half. CL=1, CN=1, M3 and M5 are both on; RCL=0, RCN=1, M4 and M6 are both off.

[0100] With M5 turned on, M1 and QB are connected, the gate level of M1 decreases, and M1 is turned on; Q discharges through M1 to IN1, and the value of Q changes from "1" to "0".

[0101] In the second step, CL=0, CN=0, and both M3 and M5 are turned off. M4 and M6 remain off, thus putting the circuit into a hold state, with the values ​​of Q and QB remaining unchanged.

[0102] Third step, RCL=1, RCN=0, both M4 and M6 are turned on. Since Q=0, M2 is turned on; VDD charges QB through M2 and M4, and the value of QB changes from "0" to "1".

[0103] In the fourth step, CL=1, CN=1, RCL=1, RCN=0, M3, M4, M5, and M6 are all turned on, and the circuit enters the latching state: Q discharges IN1 through M1, and Q remains at 0; VDD charges QB through M2 and M4, and QB remains at 1.

[0104] Thus, we finally obtain Q=0 and QB=1. The result of the operation can then be read out by reading the mode: 1IMP0=0.

[0105] In other cases, the steps are similar to those above, and will not be repeated here.

[0106] 2.4 For the XOR operation, there are 4 cases: 1XOR0=1, 0XOR1=1, 1XOR1=0, and 0XOR0=0. The specific truth table is shown in Table 4.

[0107] Table 4: Truth Table for XOR Operation

[0108]

[0109] For operator one, the rule is set as follows:

[0110] When operator 1 is 1, it corresponds to IN1 being connected to VSS and IN2 being connected to VDD; when operator 1 is 0, it corresponds to IN1 being connected to VDD and IN2 being connected to VSS.

[0111] For operator two, the rule is set as follows:

[0112] When operator two is 1, it corresponds to Q. n =1, QB n =0; when the operator two is 0, it corresponds to Q. n =0, QB n =1.

[0113] Figure 7 This demonstrates the specific operation of 1XOR0=1 in the current iteration. The initial conditions for the operation are set as follows: IN1 is connected to VSS, IN2 is connected to VDD, meaning operator one is 1; Q=0, QB=1, meaning operator two is 0; WL=0, and M9 and M10 are always closed.

[0114] Step 1: Calculate the left half. CL=1, CN=1, M3 and M5 are both on; RCL=0, RCN=1, M4 and M6 are both off.

[0115] Since QB=1, M7 is turned on; IN2 charges Q through M3 and M7, and Q changes from "0" to "1".

[0116] In the second step, CL=0, CN=0, and both M3 and M5 are turned off. M4 and M6 remain off, thus putting the circuit into a hold state, with the values ​​of Q and QB remaining unchanged.

[0117] Third step, RCL=1, RCN=0, both M4 and M6 are turned on. Q pulls the gate level of M8 high through M6, turning on M8; since QB=1, FL remains floating, QB discharges FL through M8, and the value of QB changes from "1" to "0".

[0118] In the fourth step, CL=1, CN=1, RCL=1, RCN=0, M3, M4, M5, and M6 are all turned on, and the circuit enters the latching state: IN2 charges Q through M3 and M7, and Q remains at 1; QB discharges FL through M8, and QB remains at 0.

[0119] Thus, we finally obtain Q=1 and QB=0. The result of the operation can then be read out by reading the mode as: 1XOR0=1.

[0120] In other cases, the steps are similar to those above, and will not be repeated here.

[0121] In summary, this self-recall 10T-SRAM cell can perform AND, OR, IMP, and XOR operations in operation mode, and can store the results back to the memory.

[0122] Example 2

[0123] This embodiment 2 discloses a 10T-SRAM cell array structure. The 10T-SRAM cell array structure includes 2i ×2 i The self-recovery 10T-SRAM cells disclosed in Embodiment 1 are arranged in an array. Where i > 0. Generally, i starts from 6. For example... Figure 8 As shown, a 64*64 array design is illustrated.

[0124] Self-recall 10T-SRAM cells located in the same row share the same IN1, IN2, WL, FL, CN, CL, RCN, and RCL. Self-recall 10T-SRAM cells located in the same column share the same bit line WBL and WBLB.

[0125] IN1 and IN2 are used to input operator one. BL and BLB are used to input operator two. For example... Figure 8 As shown, it can be written vertically in both directions to achieve full array activation operation.

[0126] This embodiment 2 also discloses an in-memory operation full array activation circuit. For example... Figure 9 As shown, the in-memory operation full array activation circuit includes the aforementioned 10T-SRAM cell array structure (i.e. Figure 9 The 10T in the middle), operator-input circuit (i.e. Figure 9 Operator 1 Input), Operator 2 Input Circuit (i.e. Figure 9 Operand2 Input), mode module circuit (i.e. Figure 9 Mode Control and data output circuit (i.e.) Figure 9 Data input and timing control circuits (i.e.) Figure 9 Timing Circuits in (the context of the circuits).

[0127] The circuit includes: an operator-1 input circuit for inputting operator-1 to the 10T-SRAM cell array structure via IN1 and IN2; an operator-2 input circuit for inputting operator-2 to the 10T-SRAM cell array structure via BL and BLB; a mode module circuit for inputting CN, CL, RCN, RCL, and FL to the 10T-SRAM cell array structure; a data output circuit for reading data based on the voltage difference between BL and BLB; and a timing control circuit for controlling the timing of BL, BLB, IN1, IN2, CN, CL, RCN, RCL, and FL.

[0128] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A self-recovery 10T-SRAM cell, characterized in that, include: PMOS transistor M1 has its source connected to input terminal IN1; the input terminal IN1 is used to connect to VDD or VSS. PMOS transistor M2, with its source connected to VDD; NMOS transistor M3 has its drain connected to the drain of M1 and has a storage node Q. Its gate is connected to the computing control terminal CN. The source of PMOS transistor M4 is connected to the drain of M2, and its gate is connected to the calculation control terminal RCN. NMOS transistor M5 has its drain connected to the gate of M1, and its gate is connected to the calculation control terminal CL. NMOS transistor M6 has its drain connected to the gate of M2, and its gate is connected to the calculation control terminal RCL. The drain of NMOS transistor M7 is connected to the source of M3, the gate is connected to the source of M5, and the source is connected to the input terminal IN2; the input terminal IN2 is used to connect to VDD or VSS. The NMOS transistor M8 has its drain connected to the source of M4 and has a storage node QB. Its gate is connected to the source of M6, and its source is connected to the floating terminal FL. The floating terminal FL is used to float the source of M8 or connect it to VSS. NMOS transistor M9 has its source connected to bit line BL, its gate connected to word line WL, and its drain connected to the drain of M1 and the gate of M2. as well as The NMOS transistor M10 has its source connected to the bit line BLB, its gate connected to WL, and its drain connected to the drain of M8 and the gate of M7; BL and BLB are used for writing and reading data. In the operation mode, the self-recall 10T-SRAM unit performs in-memory operations on operator one and operator two; M1, M3, M5, M7, and M9 constitute operation unit one, M2, M4, M6, M8, and M10 constitute operation unit two, CN and CL control operation unit one, and RCN, RCL, and FL control operation unit two. The first operator is input into the self-recall 10T-SRAM unit through IN1 and IN2; the second operator is obtained based on the values ​​of Q and QB at the beginning of the current operation; Q and QB are also used to recall the final result of the current operation.

2. The self-returning 10T-SRAM cell according to claim 1, characterized in that, The in-memory operations include AND, OR, IMP, and XOR operations on operator one and operator two.

3. The self-returning 10T-SRAM cell according to claim 1 or 2, characterized in that, The method for performing in-memory operations in the self-recall 10T-SRAM cell includes the following steps: Step one: The arithmetic unit first performs calculations and transforms Q into the target value one; Step two, the self-recall 10T-SRAM cell enters the hold state; Step 3: The second arithmetic unit performs calculations and transforms QB into the target value 2; Step four: The self-recall 10T-SRAM cell enters the latching state.

4. The self-recovery 10T-SRAM cell according to claim 3, characterized in that, In step one, M4, M6, M9, and M10 are turned off; In step two, M3, M4, M5, M6, M9, and M10 are turned off; In step three, M3, M5, M9, and M10 are turned off; In step four, M9 and M10 are turned off.

5. The self-returning 10T-SRAM cell according to claim 1, characterized in that, During the data reading phase, if the data stored in the cell is '1', i.e. "Q=1, QB=0"; CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS, BL and BLB are precharged to high level, WL=1, BLB is discharged through M8 and M10, and a voltage difference is generated between BL and BLB.

6. The self-returning 10T-SRAM cell according to claim 1, characterized in that, During the data reading phase, if the data stored in the cell is '0', i.e. "Q=0, QB=1"; CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS, BL and BLB are both precharged to high level, WL=1, BL discharges Q through M9, and BL and BLB generate a voltage difference.

7. The self-returning 10T-SRAM cell according to claim 1, characterized in that, During the data writing phase, when the data to be written is "1", CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS; BL precharge is high level, BLB precharge is low level, WL=1; If the data previously stored in the cell is '0', i.e. "Q=0, QB=1", QB discharges to BLB through M10, and BL charges Q through M9. QB changes from 1 to 0, and Q changes from 0 to 1, completing the data flipping and writing. If the data previously stored in the cell is '1', i.e. "Q=1, QB=0", then Q and QB remain unchanged.

8. The self-returning 10T-SRAM cell according to claim 1, characterized in that, During the data writing phase, when the data being written is "0", CN=1, CL=1; RCL=1, RCN=0; IN1 is connected to VDD, IN2 is connected to VSS, FL is connected to VSS; BL precharge is low, BLB precharge is high, WL=1; If the data previously stored in the cell is '1', i.e. "Q=1, QB=0", Q discharges to BL through M9, and BLB charges QB through M10. QB changes from 0 to 1, and Q changes from 1 to 0, thus completing the data flipping and writing. If the data previously stored in the cell is '0', i.e. "Q=0, QB=1", then Q and QB remain unchanged.

9. A 10T-SRAM cell array structure, characterized in that, including 2 i x 2 i self-refreshing 10T-SRAM cells as in any of claims 1-8 in an array; i>0; Among them, the self-recall 10T-SRAM cells located in the same row share the same IN1, the same IN2, the same WL, the same FL, the same CN, the same CL, the same RCN, and the same RCL; Self-recall 10T-SRAM cells located in the same column share the same bit line WBL and the same bit line WBLB.

10. A full-array activation circuit for in-memory operations, characterized in that, include: The 10T-SRAM cell array structure as described in claim 9; The operator-1 input circuit is used to input operator-1 to the 10T-SRAM cell array structure through IN1 and IN2; The operator two input circuit is used to input operator two into the 10T-SRAM cell array structure through BL and BLB. The mode module circuit is used to input CN, CL, RCN, RCL, and FL to the 10T-SRAM cell array structure; The data output circuit is used to read data based on the voltage difference between BL and BLB; and Timing control circuit, which is used to control the timing of BL, BLB, IN1, IN2, CN, CL, RCN, RCL, and FL.

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