Semiconductor memory device

Abstract

The present application provides a semiconductor memory device that allows a read operation to be performed at high speed. A semiconductor memory device according to one embodiment includes a plurality of first memory cell transistors (MT0 to MT7), a first selection transistor (ST1), a second selection transistor (ST2), a plurality of second memory cell transistors (MT0 to MT7), a third selection transistor (ST3), a fourth selection transistor (ST4), a plurality of third memory cell transistors (MT8 to MT15) that are commonly driven with the plurality of first memory cell transistors (MT0 to MT7), a fifth selection transistor (ST5), a sixth selection transistor (ST6), a plurality of fourth memory cell transistors (MT8 to MT15) that are commonly driven with the plurality of second memory cell transistors (MT0 to MT7), a seventh selection transistor (ST7), and an eighth selection transistor (ST8).

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-002327 (filed on January 11, 2022). This application incorporates the entire contents of this base application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] NAND flash memory is known as a non-volatile semiconductor memory device. Summary of the Invention

[0005] The purpose of this implementation is to provide a semiconductor memory device capable of high density.

[0006] A semiconductor memory device according to an embodiment includes: a substrate; a first memory pillar extending from the substrate along a first direction, having: a plurality of first memory cell transistors connected in series and having a first end and a second end; a first selection transistor electrically connected to the first end; a second selection transistor electrically connected to the second end; a plurality of second memory cell transistors electrically insulated from the plurality of first memory cell transistors and connected in series, having a third end and a fourth end; a third selection transistor electrically connecting the first selection transistors to the third end; a fourth selection transistor electrically connecting the second selection transistors to the fourth end; and a plurality of third memory cell transistors connected in series. An electrical connection is provided, having a fifth end and a sixth end; a fifth selection transistor electrically connecting the second and fourth selection transistors to the fifth end; a sixth selection transistor electrically connected to the sixth end; a plurality of fourth memory cell transistors electrically insulated from the plurality of third memory cell transistors, the plurality of fourth memory cell transistors being connected in series and having a seventh end and an eighth end; a seventh selection transistor electrically connecting the second, fourth, and fifth selection transistors to the seventh end; and an eighth selection transistor electrically connecting the sixth selection transistor to the eighth end; a first selection gate line is disposed on the substrate, parallel to the substrate surface of the substrate. A plurality of first word lines are disposed above the first select gate lines, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gates of the plurality of first memory cell transistors, respectively; a second select gate line is disposed above the plurality of first word lines, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gate of the second select transistor; a third select gate line is disposed on the substrate, parallel to the substrate surface of the substrate, and its position in the first direction is the same as that of the first select gate line in the first direction. A plurality of second word lines are disposed above the third select gate lines, parallel to the substrate surface of the substrate, and are positioned in the first direction at the same position as the plurality of first word lines in the first direction. They are disposed above the second side of the first storage pillar and are electrically connected to the gate of the plurality of second storage cell transistors. A fourth select gate line is disposed above the plurality of second word lines, parallel to the substrate surface of the substrate, and is positioned in the first direction at the same position as the second select gate lines in the first direction. It is disposed above the second side of the first storage pillar and is electrically connected to the gate of the fourth select transistor.A fifth select gate line is disposed on the substrate, parallel to the substrate surface, opposite to the first side of the first memory pillar, and electrically connected to the gate of the fifth select transistor; a plurality of third word lines are disposed on the fifth select gate line, parallel to the substrate surface, opposite to the first side of the first memory pillar, and electrically connected to the gates of the plurality of third memory cell transistors and the plurality of first word lines respectively; a sixth select gate line is disposed on the plurality of third word lines, parallel to the substrate surface, opposite to the first side of the first memory pillar, and electrically connected to the gate of the sixth select transistor; a seventh select gate line is disposed on the substrate, parallel to the substrate surface, and positioned in the first direction opposite to the fifth select gate line. The positions in the first direction are the same as those of the third word lines, opposite the second side of the first memory pillar, and electrically connected to the gate of the seventh selection transistor; a plurality of fourth word lines, above the seventh selection gate line, are disposed parallel to the substrate surface of the substrate, and are positioned in the first direction as the positions of the plurality of third word lines in the first direction, opposite the second side of the first memory pillar, and electrically connected to the gates of the plurality of fourth memory cell transistors and the plurality of second word lines respectively; and an eighth selection gate line, above the plurality of fourth word lines, is disposed parallel to the substrate surface of the substrate, and is positioned in the first direction as the positions of the sixth selection gate line in the first direction, opposite the second side of the first memory pillar, and electrically connected to the gate of the eighth selection transistor. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the structure of a storage system including the semiconductor storage device of the first embodiment.

[0008] Figure 2 This is a schematic diagram showing the circuit structure of the memory cell array in the semiconductor memory device of the first embodiment.

[0009] Figure 3 This is a schematic diagram showing the planar layout of the gate line, bit line, and memory pillars in the first embodiment.

[0010] Figure 4 This is a schematic diagram showing the planar layout of the word lines and storage columns in the first embodiment.

[0011] Figure 5 yes Figure 3 and Figure 4 The diagram shows the end face of the B1-B2 cut-off section of the semiconductor memory device.

[0012] Figure 6 yes Figure 3 and Figure 4The diagram shows the end face of the A1-A2 cut-off portion of the semiconductor memory device.

[0013] Figure 7 yes Figure 5 The diagram shows the end face of the C1-C2 cut-off portion of the memory cell transistor.

[0014] Figure 8 yes Figure 7 The diagram shows the cut-off end face of the D1-D2 section of the memory cell transistor.

[0015] Figure 9 This is a diagram showing the equivalent circuit of the memory column in the semiconductor memory device of the first embodiment.

[0016] Figure 10 This is a diagram showing another example of the equivalent circuit of the storage column in the semiconductor storage device of the first embodiment.

[0017] Figure 11 This is a diagram illustrating the electrical connections of the voltage generation circuit, driver group, and select gate line or word line in the first embodiment.

[0018] Figure 12 This is a diagram illustrating the electrical connections of the voltage generation circuit, driver group, and select gate line or word line in the first embodiment.

[0019] Figure 13 This is a schematic diagram illustrating the electrical connection between the even-digit line driver and the line decoder in the first embodiment.

[0020] Figure 14 This is a schematic diagram illustrating the electrical connection between the odd-number line driver and the line decoder in the first embodiment.

[0021] Figure 15 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit and the even-number line driver in the first embodiment.

[0022] Figure 16 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit and the odd-number line driver in the first embodiment.

[0023] Figure 17 This is a schematic diagram illustrating the equivalent circuit of the memory column and the voltage applied to each memory cell transistor via word lines in the semiconductor memory device of the first embodiment.

[0024] Figure 18 (a) to (c) are schematic diagrams showing the timing of various signals during data readout operation in the semiconductor memory device of the first embodiment.

[0025] Figure 19This is a schematic diagram illustrating the equivalent circuit of the memory column and the voltage applied to each memory cell transistor via word lines in the semiconductor memory device of the first embodiment.

[0026] Figure 20 (a) to (c) are schematic diagrams showing the timing of various signals during data readout operation in the semiconductor memory device of the first embodiment.

[0027] Figure 21 This is a schematic diagram illustrating the equivalent circuit of the memory column and the voltage applied to each memory cell transistor via word lines in the first example of the semiconductor memory device of the second embodiment.

[0028] Figure 22 This is a schematic diagram illustrating the equivalent circuit of the memory column and the voltage applied to each memory cell transistor via word lines in a second example of the semiconductor memory device according to the second embodiment.

[0029] Figure 23 This is a schematic diagram illustrating the equivalent circuit of the memory column and the voltage applied to each memory cell transistor via the word line in the third example of the semiconductor memory device of the second embodiment.

[0030] Figure 24 This is a schematic diagram illustrating the equivalent circuit of the memory column and the voltage applied to each memory cell transistor via word lines in the fourth example of the semiconductor memory device of the second embodiment.

[0031] Figure 25 This diagram schematically illustrates the voltage of the select transistor applied to the memory column (two adjacent NAND strings) via the select gate line and the voltage of the memory cell transistor applied to the memory column via the word line in the semiconductor memory device of the third embodiment. Detailed Implementation

[0032] The embodiments will now be described using the accompanying drawings. Furthermore, in the drawings, the same or similar reference numerals are used to label the same or similar parts.

[0033] (First Embodiment)

[0034] Figure 1 This is a block diagram illustrating an example of the structure of a memory system 3 including the semiconductor memory device 1 of the first embodiment. The structure of the memory system 3 including the semiconductor memory device 1 of the first embodiment is not limited to... Figure 1 The structure shown.

[0035] like Figure 1As shown, the storage system 3 includes a semiconductor storage device 1 and a storage controller 2. The storage system 3 may be, for example, a memory card such as an SSD (solid-state drive) or an SDTM card. The storage system 3 may also include a host device (not shown).

[0036] Semiconductor storage device 1 is connected to, for example, storage controller 2 and is controlled by storage controller 2. Storage controller 2 receives commands from host device required for the operation of semiconductor storage device 1 and sends these commands to semiconductor storage device 1. Storage controller 2 sends these commands to semiconductor storage device 1 to control the reading of data from semiconductor storage device 1, the writing of data to semiconductor storage device 1, or the erasure of data on semiconductor storage device 1. In this embodiment, semiconductor storage device 1 is, for example, NAND flash memory.

[0037] like Figure 1 As shown, the semiconductor memory device 1 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a sequence generator 24, a register 25, a ready / busy control circuit 26, a voltage generation circuit 27, a driver group 28, a line decoder 29, a sense amplifier 30, an input / output pad group 71, and a logic control pad group 72. In the semiconductor memory device 1, various operations are performed, such as writing data DAT to the memory cell array 21 and reading data DAT from the memory cell array 21. The structure of the semiconductor memory device 1 in this embodiment is not limited to... Figure 1 The structure shown.

[0038] The memory cell array 21 is connected, for example, to the sense amplifier 30, the line decoder 29, and the driver group 28. The memory cell array 21 includes blocks BLK0, BLK1, ..., BLKn (n is an integer greater than or equal to 1). Details will be described later, but each block BLK includes multiple serial cells SU (SU0, SU1, SU2, ...). Each serial cell SU includes multiple non-volatile memory cells associated with bit lines and word lines. The block BLK serves as, for example, the data erasure unit. The memory cell transistors MT included within the same block BLK (… Figure 2 The data stored therein is also erased.

[0039] In the semiconductor memory device 1, for example, a TLC (Triple-Level Cell) or QLC (Quadrup Level Cell) method can be applied. In the TLC method, 3 bits of data are stored in each memory cell, and in the QLC method, 4 bits of data are stored in each memory cell. Alternatively, less than 2 bits of data or more than 5 bits of data can be stored in each memory cell.

[0040] Input / output circuit 22 is connected, for example, to register 25, logic control circuit 23, and sense amplifier 30. Input / output circuit 22 controls the transmission and reception of data signal DQ<7:0> between memory controller 2 and semiconductor memory device 1.

[0041] The data signals DQ<7:0> are 8-bit signals. The data signals DQ<7:0> are entities representing the data transmitted and received between the semiconductor memory device 1 and the memory controller 2, including instruction CMD, data DAT, address information ADD, and status information STS. Instruction CMD includes, for example, commands for executing commands sent from the host device (memory controller 2) to the semiconductor memory device 1. Data DAT includes write data DAT to or read data DAT from the semiconductor memory device 1. Address information ADD includes, for example, column addresses and row addresses for selecting multiple non-volatile memory cells associated with bit lines and word lines. Status information STS includes, for example, information related to the status of the semiconductor memory device 1 associated with write and read operations.

[0042] More specifically, the input / output circuit 22 includes an input circuit and an output circuit, which perform the following processing: The input circuit receives write data DAT, address information ADD, and instruction CMD from the memory controller 2. The input circuit sends the received write data DAT to the sense amplifier 70 and sends the received address information ADD and instruction CMD to the register 25. On the other hand, the output circuit receives status information STS from the register 25 and read data DAT from the sense amplifier 70. The output circuit sends the received status information STS and read data DAT to the memory controller 2.

[0043] The logic control circuit 23 is connected, for example, to the memory controller 2 and the sequence generator 24. The logic control circuit 23 receives from the memory controller 2, for example, a chip enable signal CEn, an instruction latch enable signal, an address latch enable signal ALE, a write enable signal WEn, a read enable signal, and a write protection signal WPn. The logic control circuit 23 controls the input / output circuit 22 and the sequence generator 24 based on the received signals.

[0044] The chip enable signal CEn is used to enable (activate) the semiconductor memory device 1. The instruction latch enable signal is used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 is the instruction CMD. The address latch enable signal ALE is used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 is the address information ADD. The write enable signal WEn and the read enable signal are, for example, signals used to command the input / output circuit 22 to input and output the data signal DQ, respectively. The write protect signal WPn is used to indicate to the semiconductor memory device 1 that writing and erasing data are prohibited.

[0045] The sequence generator 24 is connected, for example, to the ready / busy control circuit 26, the sense amplifier 30, and the driver group 28. Based on the instruction CMD held in the instruction register, the sequence generator 24 controls the overall operation of the semiconductor memory device 1. For example, the sequence generator 24 controls the sense amplifier 30, the line decoder 29, the voltage generation circuit 27, and the driver group 28 to perform various operations such as write and read operations.

[0046] Register 25 includes, for example, a status register (not shown), an address register (not shown), and an instruction register (not shown). The status register receives and holds status information STS from the sequence generator 24, and sends the status information STS to the input / output circuit 22 based on the instructions of the sequence generator 24. The address register receives and holds address information ADD from the input / output circuit 22. The address register sends the column address from the address information ADD to the sense amplifier 70 and the row address from the address information ADD to the row decoder 29. The instruction register receives and holds the instruction CMD from the input / output circuit 22 and sends the instruction CMD to the sequence generator 24.

[0047] The ready / busy control circuit 26 generates a ready / busy signal R / Bn under the control of the sequence generator 24, and sends the generated ready / busy signal R / Bn to the memory controller 2. The ready / busy signal R / Bn is used to notify the semiconductor memory device 1 whether it is in a ready state that accepts commands from the memory controller 2, or in a busy state that does not accept commands.

[0048] The voltage generation circuit 27 is connected, for example, to the driver assembly 28. Based on the control of the sequence generator 24, the voltage generation circuit 27 generates the voltage used in write operations and read operations, and supplies the generated voltage to the driver assembly 28.

[0049] Driver group 28 includes, for example, even-number line driver 28A ( Figure 12 ) and odd digital line driver 28B ( Figure 12Driver group 28 is connected to memory cell array 21, sense amplifier 70, and line decoder 29. Driver group 28 generates select gate line SGD (select voltage generator) based on the voltage supplied from voltage generation circuit 27, for example, during various operations such as read and write operations. Figure 2 ), Word line WL ( Figure 2 ) and source line SL ( Figure 2 Various voltages are applied by the driver group 28. The generated voltage is supplied to the even digital line driver 28A, the odd digital line driver 28B, the sense amplifier 30, the line decoder 29, the source line SL, etc.

[0050] The row decoder 29 receives the row address from the address register and decodes the received row address. Based on the decoding result, the row decoder 29 selects the block BLK to which various operations such as read and write operations are performed. The row decoder 29 can supply voltage from the driver group 28 to the selected block BLK.

[0051] The sense amplifier 30 receives a column address from the address register and decodes the received column address. Based on the decoding result, the sense amplifier 30 performs data transmission and reception operations (DAT) between the memory controller 2 and the memory cell array 21. The sense amplifier 30 includes, for example, a sense amplifier unit (not shown) for each bit line. The sense amplifier 30 can supply voltage to the bit line BL using the sense amplifier unit. For example, the sense amplifier 30 can supply voltage to the bit line using the sense amplifier unit. Furthermore, the sense amplifier 30 reads the data read from the memory cell array 21, generates sense data (DAT), and sends the generated sense data (DAT) to the memory controller 2 via the input / output circuit 22. Additionally, the sense amplifier 30 receives write data (DAT) from the memory controller 2 via the input / output circuit 22 and sends the received write data (DAT) to the memory cell array 21.

[0052] The input / output pad group 71 sends the data signal DQ<7:0> received from the memory controller 2 to the input / output circuit 22. The input / output pad group 71 sends the data signal DQ<7:0> received from the input / output circuit 22 to the memory controller 2.

[0053] The logic control pad group 72 transmits the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn received from the memory controller 2 to the logic control circuit 23. The logic control pad group 72 transmits the ready / busy signal R / Bn received from the ready / busy control circuit 26 to the memory controller 2.

[0054] Figure 2 yes Figure 1An example of the circuit structure of the memory cell array 21 shown. Figure 2 This is a diagram showing the circuit structure of one block BLK among the multiple blocks BLK included in the memory cell array 21. For example, the multiple blocks BLK included in the memory cell array 21 each have... Figure 2 The circuit structure shown is not limited to the structure of the memory cell array 21 in this embodiment. Figure 2 The structure shown. In Figure 2 In the description, sometimes the terms "and" are omitted. Figure 1 Descriptions of the same or similar structures.

[0055] like Figure 2 As shown, the block BLK includes multiple string units SU (SU0, SU1, SU2, SU3). In this embodiment, write and read operations are performed on a per-string unit SU (page). Each string unit SU includes multiple NAND strings 50. For example, string units SU0 and SU2 include multiple NAND strings 50e, and string units SU1 and SU3 include multiple NAND strings 50o. Furthermore, in... Figure 2 The example shown illustrates that each block BLK includes four string units SU0, SU1, SU2, and SU3, but the number of string units included in each block is not limited to four. For example, each block BLK may also include six or eight string units.

[0056] The NAND string 50 includes, for example, 16 memory cell transistors MT (MT0 to MT15) and 4 select transistors (ST1, ST2, ST5, ST6 or ST3, ST4, ST7, ST8). The memory cell transistors MT have a control gate and a charge storage layer to non-volatilely retain data. The 16 memory cell transistors MT and the 4 select transistors are connected in series.

[0057] More specifically, for example Figure 9 and Figure 10As shown, in NAND string 50e, memory cell transistors MT0 to MT15 are connected in series between the drain of select transistor ST1 and the source of select transistor ST6. In NAND string 50o, memory cell transistors MT0 to MT15 are connected in series between the drain of select transistor ST3 and the source of select transistor ST8. More specifically, in NAND string 50e, eight memory cell transistors MT0 to MT7 are connected in series between the drain of select transistor ST1 and the source of select transistor ST2, and the remaining eight memory cell transistors MT8 to MT15 are connected in series between the drain of select transistor ST5 and the source of select transistor ST6. Furthermore, the source of select transistor ST2 and the drain of select transistor ST5 are connected at the midpoint MP. Similarly, in NAND string 50o, eight memory cell transistors MT0 to MT7 are connected in series between the drain of select transistor ST3 and the source of select transistor ST4, and the remaining eight memory cell transistors MT8 to MT15 are connected in series between the drain of select transistor ST7 and the source of select transistor ST8. The source of select transistor ST3 and the drain of select transistor ST7 are connected at the midpoint MP.

[0058] In other words, NAND string 50e is connected to the source line SL via select transistor ST1, to the bit line BL via select transistor ST6, and to the midpoint MP via select transistors ST2 and ST5. Similarly, NAND string 50o is connected to the source line SL via select transistor ST3, to the bit line BL via select transistor ST8, and to the midpoint MP via select transistors ST4 and ST7.

[0059] The gates of the selection transistor ST6 in each serial unit SU are connected to the selection gate lines SGD (SGDU0, SGDU2, ...). The gates of the selection transistor ST8 in each serial unit SU are connected to the selection gate lines SGD (SGDU1, SGDU3, ...). The gates of the selection transistor ST5 in each serial unit SU are connected to the selection gate line SGS (SGSUe). The gates of the selection transistor ST7 in each serial unit SU are connected to the selection gate line SGS (SGSUo). The gates of the selection transistor ST2 in each serial unit SU are connected to the selection gate lines SGD (SGDLe0, SGDLe2, ...). The gates of the selection transistor ST4 in each serial unit SU are connected to the selection gate lines SGD (SGDLo1, SGDLo3, ...). The gates of the selection transistor ST1 in each serial unit SU are connected to the selection gate line SGS (SGSLe). The gates of the selection transistor ST3 in each serial unit SU are connected to the selection gate line SGS (SGSLo). The selection gate line SGD is independently controlled by the line decoder 29. Even-numbered select gate lines SGSUe and SGSLe, and odd-numbered select gate lines SGSUo and SGSLo, can be interconnected and controlled in the same way, or they can be set and controlled independently.

[0060] The control gates of the memory cell transistors MT (MT0 to MT15) contained in the serial unit SUE within the same block BLK are all connected to word lines WLe (WLe0 to WLe15). The control gates of the memory cell transistors MT (MT0 to MT15) contained in the serial unit SUo within the same block BLK are all connected to word lines WLo (WLo0 to WLo15). The selection gate lines WLe and WLo are independently controlled by the line decoder 29.

[0061] The drains of the select transistors ST6 or ST8 of the NAND strings 50 located in the same column within the memory cell array 21 are commonly connected to the bit line BL (BL0 to BL(L-1), where (L-1) is a natural number greater than 2). That is, the bit line BL connects the NAND strings 50 across multiple string cells SU. The sources of multiple select transistors ST1 or ST2 are commonly connected to the source line SL. The source line SL is electrically connected to the driver group 28, for example, and is supplied with voltage from the voltage generation circuit 27 or the driver group 28 by controlling the voltage generation circuit 27 of the sequence generator 24 and the driver group 28. Alternatively, the semiconductor memory device 1 in one embodiment may also have multiple source lines SL. For example, multiple source lines SL may be electrically connected to the driver group 28 respectively, and the multiple source lines SL may be supplied with different voltages from the voltage generation circuit 27 or the driver group 28 by controlling the voltage generation circuit 27 of the sequence generator 24 and the driver group 28 respectively.

[0062] Each string cell SU comprises multiple NAND strings 50 connected to different bit lines BL and the same select gate line SGD. Each block BLK comprises multiple string cells SU shared by multiple word lines WL. The memory cell array 21 comprises multiple blocks BLK shared by the bit lines BL. Within the memory cell array 21, the aforementioned select gate line SGS, word lines WL, and select gate line SGD are stacked above the source line layer, and the memory cell transistors MT are stacked in three dimensions.

[0063] Figure 3 This is a diagram showing the planar layout of the select gate line (SGDU) in the plane (XY plane) parallel to the source line layer of a certain block BLK. For example... Figure 3 As shown, in the semiconductor memory device 1 of this embodiment, for example, four select gate lines (SGDUs) are included within one block BLK. The planar layout of the select gate lines (SGDUs) in one embodiment is not limited to... Figure 3 The layout shown. In Figure 3 In the description, sometimes the terms "and" are omitted. Figure 1 and Figure 2 Descriptions of the same or similar structures.

[0064] like Figure 3As shown, in the semiconductor memory device 1 of this embodiment, for example, three wiring layers 10-0a, 10-0b, and 10-0c extending in the X direction are connected using a first connection portion 10-0d extending in the Y direction. Wiring layers 10-0a and 10-0c are located at opposite ends in the Y direction. Wiring layers 10-0a and 10-0b are adjacent in the Y direction, separated by another wiring layer (wiring layer 10-1a). The first connection portion 10-0d is located at one end in the X direction. The three wiring layers 10-0a, 10-0b, and 10-0c function as a select gate line SGDU0. In this embodiment, for example, the Y direction is orthogonal or substantially orthogonal to the X direction.

[0065] Wiring layers 10-1a and 10-1b extending in the X direction are connected by a second connection portion 10-1d extending in the Y direction. Wiring layer 10-1a is located between wiring layers 10-0a and 10-0b. Wiring layer 10-1b is located between wiring layer 10-0b and another wiring layer (wiring layer 10-2a). The second connection portion 10-1d is located at the opposite end of the first connection portion 10-0d in the X direction. The two wiring layers 10-1a and 10-1b function as the select gate line SGDU1.

[0066] Routing layers 10-2a and 10-2b extending along the X direction are connected by a first connecting portion 10-2d extending along the Y direction. Similarly, routing layers 10-3a and 10-3b extending along the X direction are connected by a second connecting portion 10-3d extending along the Y direction. Routing layer 10-2a is located between routing layer 10-1b and routing layer 10-3a. Routing layer 10-3a is located between routing layer 10-2a and routing layer 10-2b. Routing layer 10-2b is located between routing layer 10-3a and routing layer 10-3b. Routing layer 10-3b is located between routing layer 10-2b and routing layer 10-0c. The first connecting portion 10-2d is located at one end on the same side as the first connecting portion 10-0d in the X direction. The second connecting portion 10-3d is located at the other end on the opposite side of the first connecting portion 10-0d in the X direction. Two wiring layers, 10-2a and 10-2b, function as the select gate line SGDU2. Two wiring layers, 10-3a and 10-3b, function as the select gate line SGDU3.

[0067] In this embodiment, a structure is illustrated where each wiring layer is connected using the first connection portion 10-0d, 10-2d, or the second connection portion 10-1d, 10-3d, but the embodiment is not limited to this structure. For example, each wiring layer is independently controlled to supply the same voltage to wiring layers 10-0a, 10-0b, and 10-0c, the same voltage to wiring layers 10-1a and 10-1b, the same voltage to wiring layers 10-2a and 10-2b, and the same voltage to wiring layers 10-3a and 10-3b.

[0068] The string cell SU including the NAND string 50e of the memory pillar MP adjacent to wiring layers 10-0a, 10-0b, and 10-0c is called SU0. The string cell SU including the NAND string 50o of the memory pillar MP adjacent to wiring layers 10-1a and 10-1b is called SU1. The string cell SU including the NAND string 50e of the memory pillar MP adjacent to wiring layers 10-2a and 10-2b is called SU2. The string cell SU including the NAND string 50o of the memory pillar MP adjacent to wiring layers 10-3a and 10-3b is called SU3.

[0069] Within block BLK, adjacent wiring layers 10 in the Y direction are insulated. The region that insulates adjacent wiring layers 10 is called slot SLT2. In slot SLT2, for example, an insulating film (not shown) is used to fill the area from the plane parallel to the source line layer up to the layer where the wiring layers 10 are disposed. Additionally, within the memory cell array 21, for example, multiple [missing information - likely referring to a specific array of cells] are arranged in the Y direction. Figure 3 The diagram shows a block BLK. Within a block BLK, similar to the adjacent wiring layers 10 in the Y direction, an insulating film (not shown) is used to fill the spaces between adjacent blocks BLK in the Y direction, and these adjacent blocks BLK are also insulated. The area that insulates adjacent blocks BLK is called slit SLT1. Similar to slit SLT2, in slit SLT1, the insulating film fills the area from the plane parallel to the source line layer at least up to the layer where the wiring layer 10 is located.

[0070] Multiple memory pillars MP (MP0 to MP15) are provided between adjacent wiring layers 10 in the Y direction. The multiple memory pillars MP are provided in the memory cell section. The multiple memory pillars MP are respectively provided along the Z direction. In one embodiment, for example, the Z direction is a direction orthogonal or substantially orthogonal to the XY direction, and is a direction perpendicular or substantially perpendicular to the source line layer. Furthermore, the Z direction is an example of a first direction. Additionally, the Y direction is an example of a second direction.

[0071] Specifically, storage pillars MP4 and MP12 are provided between routing layers 10-0a and 10-1a. Storage pillars MP0 and MP8 are provided between routing layers 10-1a and 10-0b. Storage pillars MP5 and MP13 are provided between routing layers 10-0b and 10-1b. Storage pillars MP1 and MP9 are provided between routing layers 10-1b and 10-2a. Storage pillars MP6 and MP14 are provided between routing layers 10-2a and 10-3a. Storage pillars MP2 and MP10 are provided between routing layers 10-3a and 10-2b. Storage pillars MP7 and MP15 are provided between routing layers 10-2b and 10-3b. Storage pillars MP3 and MP11 are provided between routing layers 10-3b and 10-0c.

[0072] The memory column (MP) is a structure that forms multiple select transistors (ST) and multiple memory cell transistors (MT). The detailed structure of the memory column (MP) will be described later.

[0073] Storage columns MP0 to MP3 are arranged along the Y direction. Storage columns MP8 to MP11 are arranged along the Y direction and adjacent to storage columns MP0 to MP3 in the X direction. That is, storage columns MP0 to MP3 and storage columns MP8 to MP11 are arranged side by side.

[0074] Storage columns MP4~MP7 and storage columns MP12~MP15 are arranged along the Y direction. Storage columns MP4~MP7 are located between storage columns MP0~MP3 and storage columns MP8~MP11 in the X direction. Storage columns MP12~MP15 are located together with storage columns MP4~MP7, sandwiching storage columns MP8~MP11 in the X direction. That is, storage columns MP4~MP7 and storage columns MP12~MP15 are arranged side by side.

[0075] Two bit lines, BL0 and BL1, are positioned above memory cylinders MP0 to MP3. Bit line BL0 is connected to memory cylinders MP1 and MP3. Bit line BL1 is connected to memory cylinders MP0 and MP2. Two bit lines, BL2 and BL3, are positioned above memory cylinders MP4 to MP7. Bit line BL2 is connected to memory cylinders MP5 and MP7. Bit line BL3 is connected to memory cylinders MP4 and MP6.

[0076] Two bit lines, BL4 and BL5, are positioned above memory cylinders MP8-MP11. Bit line BL4 is connected to memory cylinders MP9 and MP11. Bit line BL5 is connected to memory cylinders MP8 and MP10. Two bit lines, BL6 and BL7, are positioned above memory cylinders MP12-MP15. Bit line BL6 is connected to memory cylinders MP13 and MP15. Bit line BL7 is connected to memory cylinders MP12 and MP14.

[0077] As described above, the memory pillar MP is positioned across two wiring layers 10 in the Y direction to fill a portion of any one of the multiple slots SLT2. Additionally, one slot SLT2 is provided between adjacent memory pillars MP in the Y direction.

[0078] Furthermore, no storage pillar MP is provided between the adjacent wiring layers 10-0a and 10-0c separated by the slit SLT1.

[0079] Figure 4 This is a diagram showing the planar layout of the character line WL in the XY plane. Figure 4 The layout shown is Figure 3 The layout of a single block corresponds to the setting of a larger area. Figure 3 The layout of the wiring layer 11 below the wiring layer 10 is shown. The planar layout of the word line WL in one embodiment is not limited to... Figure 4 The layout shown. In Figure 4 In the description, sometimes the terms "and" are omitted. Figures 1-3 Descriptions of the same or similar structures.

[0080] like Figure 4 As shown, nine wiring layers 11 (including wiring layers 11-0 to 11-7, where wiring layer 11-0 includes wiring layers 11-0a and 11-0b) extending in the X direction are arranged along the Y direction. Each wiring layer 11-0 to 11-7 is arranged below each wiring layer 10-0 to 10-7 relative to the Z direction. An insulating film is provided between wiring layers 11-0 to 11-7 and wiring layers 10-0 to 10-7, thus insulating wiring layers 11-0 to 11-7 from each other.

[0081] Each routing layer 11 functions as word line WL15. Other word lines WL0~WL14 also have the same structure and function as word line WL15. Figure 4 In the example shown, routing layers 11-0a, 11-2, 11-4, 11-6, and 11-0b function as word lines WLe15. Routing layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected using a first connection portion 11-8 extending in the Y direction. The first connection portion 11-8 is located at one end in the X direction. In the first connection portion 11-8, routing layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected to the line decoder 29. In one embodiment, the first connection portion 11-8 and routing layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are sometimes collectively referred to as routing layer 11e.

[0082] Furthermore, routing layers 11-1, 11-3, 11-5, and 11-7 function as word lines WLo15. Routing layers 11-1, 11-3, 11-5, and 11-7 are connected using a second connection portion 11-9 extending in the Y direction. The second connection portion 11-9 is located in the X direction at the opposite end to the first connection portion 11-8. In the second connection portion 11-9, routing layers 11-1, 11-3, 11-5, and 11-7 are connected to the line decoder 29. In one embodiment, the second connection portion 11-9 and routing layers 11-1, 11-3, 11-5, and 11-7 are sometimes collectively referred to as routing layer 11o.

[0083] The storage cell section is disposed between the first connection section 11-8 and the second connection section 11-9. In the storage cell section, adjacent wiring layers 11 in the Y direction are... Figure 3 The slit SLT2 shown is used for isolation. Additionally, the wiring layer 11 between adjacent blocks BLK in the Y direction is similarly isolated by slit SLT1, just like slit SLT2. The memory cell section and... Figure 3 Similarly, this includes storage columns MP0 to MP15.

[0084] The selected gate line SGDL, described later, has the same characteristics as... Figure 3 The selected gate line SGDU shown has the same structure. Furthermore, the selected gate lines SGSU, SGSL, and word lines WL0 to WL14, described later, have the same structure as... Figure 4 The word line WL15 shown has the same structure.

[0085] Figure 5 It means Figure 4 The diagram shows the end faces of the cut-off portions B1-B2. The end faces of the cut-off portions of block BLK in this embodiment are not limited to... Figure 5 The cut-off end face shown. Figure 5 In the description, sometimes the terms "and" are omitted. Figures 1-4 Descriptions of the same or similar structures.

[0086] like Figure 5 As shown, wiring layer 12a is disposed above source line layer 13 along the Z direction. Source line layer 13 functions as source line SL. Alternatively, wiring layer 12a can also replace... Figure 5 The source line layer 13 shown is disposed on the p-type well region in the semiconductor substrate (substrate). In this case, the source line SL is electrically connected to the p-type well region in the semiconductor substrate.

[0087] Wiring layer 12a functions as the select gate line SGSL. An 8-layer wiring layer 11a is stacked above wiring layer 12a along the Z direction. Wiring layer 11a functions as the word line WL. Furthermore, the 8-layer wiring layer 11a corresponds to word lines WL0 to WL7 in a one-to-one configuration. Wiring layer 10a is disposed above wiring layer 11a. Wiring layer 10a functions as the select gate line SGDL. Wiring layer 12b is disposed above wiring layer 10a. Wiring layer 12b functions as the select gate line SGSU. An 8-layer wiring layer 11b is stacked above wiring layer 12b along the Z direction. Wiring layer 11b functions as the word line WL. Furthermore, the 8-layer wiring layer 11b corresponds to word lines WL8 to WL15 in a one-to-one configuration. Wiring layer 10b is disposed above wiring layer 11b. Wiring layer 10b functions as the select gate line SGDU. Furthermore, an insulating layer 38 is provided between wiring layer 10a and wiring layer 12b. Furthermore, insulating layers 30b are provided in the memory pillar MP above the insulating layer 38 and in the memory pillar MP below the insulating layer 38. The semiconductor layer 31 ( Figure 7 ) and the semiconductor layer 31 within the storage pillar MP below the insulating layer 38 ( Figure 7 For example, they are electrically connected to each other in the storage column MP between wiring layer 10a and wiring layer 12b. Figure 4 This is a diagram showing the planar layout of wiring layers 11a, 11b, 12a, and 12b, which function as word line WL, select gate line SGSL, and select gate line SGSU. Figure 3 This is a diagram showing the planar layout of wiring layers 10a and 10b that function as select gate line SGDL and select gate line SGDU.

[0088] Wiring layer 12a functions as either an even-numbered gate selection line (SGSLe) or an odd-numbered gate selection line (SGSLo). The even-numbered gate selection lines (SGSLe) and odd-numbered gate selection lines (SGSLo) are alternately arranged in the Y direction, separated by a slit (SLT2). Wiring layer 12b functions as either an even-numbered gate selection line (SGSUe) or an odd-numbered gate selection line (SGSUo). The even-numbered gate selection lines (SGSUe) and odd-numbered gate selection lines (SGSUo) are alternately arranged in the Y direction, separated by a slit (SLT2). Memory pillars (MP) are provided between adjacent even-numbered gate selection lines (SGSLe) and odd-numbered gate selection lines (SGSLo) in the Y direction, and between adjacent even-numbered gate selection lines (SGSUe) and odd-numbered gate selection lines (SGSUo) in the Y direction.

[0089] Wiring layers 11a and 11b function as either even-number lines WLe or odd-number lines WLo. Even-number lines WLe and odd-number lines WLo are alternately arranged in the Y direction, separated by a slit SLT2. Even-number lines WLe0~WLe7 and odd-number lines WLo0~WLo7 are located below insulating layer 38. Even-number lines WLe8~15 and odd-number lines WLo8~15 are located above insulating layer 38. Storage pillars MP are located between adjacent word lines WLe and WLo in the Y direction. Storage cells (described later) are located between storage pillars MP and word lines WLe, and between storage pillars MP and word lines WLo.

[0090] A slit SLT1 is provided between adjacent blocks BLK in the Y direction. As described above, an insulating layer is provided in the slit SLT1. However, a contact plug or a slot-shaped structure formed of a conductor may also be provided in the slit SLT1, which serves as an insulator. When a contact plug or a slot-shaped structure formed of a conductor is provided in the slit SLT1, a voltage can be applied to the source line layer 13. In addition, the width of the slit SLT1 along the Y direction is larger than the width of the slit SLT2 along the Y direction.

[0091] like Figure 3 as well as Figure 5 As shown, memory cylinders MP are electrically connected to bit lines BL. For example, memory cylinder MP0 and bit line BL1 are connected via contact plug 16. Additionally, memory cylinder MP1 is connected to bit line BL0 via contact plug 16, memory cylinder MP2 is connected to bit line BL1 via contact plug 16, and memory cylinder MP3 is connected to bit line BL0 via contact plug 16. Similarly, memory cylinders MP4 to MP7 are connected to bit lines BL2 or BL3 respectively, memory cylinders MP8 to MP11 are connected to bit lines BL4 or BL5, and memory cylinders MP12 to MP15 are connected to bit lines BL6 or BL7.

[0092] Figure 6 It means Figure 3 The diagram shows the cut-off end face of the semiconductor memory device, specifically the A1-A2 section. In one embodiment, the cut-off end face of block BLK is not limited to... Figure 6 The cut-off end face shown. Figure 6 In the description, sometimes the terms "and" are omitted. Figures 1-5 Description of similar or identical structures. The stack-up structure of source line layer 13, wiring layer 12, wiring layer 11, and wiring layer 10, and the structure of the memory cell section, as used... Figure 5 As explained, therefore, further explanation is omitted here. Additionally, in Figure 6 In the diagram, the structure existing in the depth direction of the cut-off end face of section A1-A2 is depicted with dashed lines.

[0093] like Figure 6As shown, in the first connection region, wiring layers 10, 11, and 12 are configured, for example, in a stepped shape. That is, when viewed in the XY plane, the upper surfaces of the ends of wiring layers 10, 16, 11, and 12 are exposed in the first connection region. Contact plugs 17 are provided on the upper surfaces of the ends of wiring layers 10, 16, 11, and 12 exposed in the first connection region. Contact plugs 17 are connected to metal wiring layer 18. For example, using metal wiring layer 18, wiring layer 10b, which functions as even-numbered select gate lines SGDU0 and SGDU2, wiring layer 10a, which functions as even-numbered select gate lines SGDL0 and SGDL2, wiring layers 11a and 11b, which function as even-numbered line WLe, wiring layer 12b, which functions as even-numbered select gate line SGSUe, and wiring layer 12a, which functions as even-numbered select gate line SGSLe, are transmitted via line decoder 29 ( Figure 1 It is electrically connected to the even digital line driver 28A.

[0094] Similar to the first connection region, in the second connection region, wiring layers 10, 11, and 12 are, for example, stepped and led out from the source line layer 13. Viewed in the XY plane, the upper surfaces of the ends of wiring layers 10, 11, and 12 are exposed in the second connection region. Contact plugs 19 are provided on the upper surfaces of the ends of wiring layers 10, 11, and 12 exposed in the second connection region, and these contact plugs 19 are connected to the metal wiring layer 20. For example, using the metal wiring layer 20, wiring layers 10b functioning as odd-numbered select gate lines SGDU1 and SGDU1, wiring layers 11a and 11b functioning as odd-numbered lines WLo, wiring layer 12b functioning as odd-numbered select gate lines SGSUo, and wiring layer 12a functioning as odd-numbered select gate lines SGSLo are transmitted via the line decoder 29 ( Figure 1 It is electrically connected to the odd number line driver 28B.

[0095] The wiring layer 10 can replace the first connection area 7 and be electrically connected to the line decoder 29 or the even digital line driver 28A and the odd digital line driver 28B via the second connection area, or it can be electrically connected to the line decoder 29 or the even digital line driver 28A and the odd digital line driver 28B via both the first connection area and the second connection area.

[0096] Figure 7 This is a diagram showing the C1-C2 cut-off end face of the memory cell transistor in this embodiment. Figure 8 It means Figure 7The diagram shows the cut-off end face of the D1-D2 section of the memory cell transistor. Figure 7 and Figure 8 This is a cut-off end-face view of the region including two memory cell transistors MT. In the first example, the charge accumulation layer included in the memory cell transistor MT is an insulating film. The first example of the memory cell transistor in this embodiment is not limited to... Figure 7 and Figure 8 The structure shown. In Figure 7 and Figure 8 In the description, sometimes the terms "and" are omitted. Figures 1-6 Descriptions of the same or similar structures.

[0097] like Figure 7 and Figure 8 As shown, the memory pillar MP includes an insulating layer 30a (an example of an insulator) disposed along the Z-direction, an insulating layer 30b (an example of an insulator) disposed along the Z-direction, a semiconductor layer 31, and insulating layers 32-34. The insulating layers 30a and 30b are formed, for example, using a silicon oxide film. The semiconductor layer 31 is disposed outside the insulating layer 30a and functions as a region for forming the channels of the memory cell transistors MT. The semiconductor layer 31 (an example of a first channel and a second channel) is formed, for example, using a polysilicon layer. The semiconductor layers 31 are separated between the memory cell transistors MT located within the same memory pillar MP.

[0098] As described above, semiconductor layer 31 is separated between two opposing memory cell transistors MT. Specifically, in Figure 7 as well as Figure 8 In the memory cell transistors MT on the left and right sides, which are opposite each other, the channel formed by the first memory cell and the channel formed by the second memory cell are separated from each other and insulated from each other.

[0099] An insulating layer 32 is disposed outside the semiconductor layer 31 and functions as a gate insulating film for the memory cell transistor MT. The insulating layer 32 is formed, for example, using a stacked structure of silicon oxide and silicon nitride films. An insulating layer 33 is disposed outside the semiconductor layer 31 and functions as a charge storage layer for the memory cell transistor MT. The insulating layer 33 is formed, for example, using a silicon nitride film. An insulating layer 34 is disposed outside the insulating layer 33 and functions as a barrier insulating film for the memory cell transistor MT. The insulating layer 34 is formed, for example, using a silicon oxide film. An insulating layer 37 is buried within the slit SLT2, excluding the memory pillar MP portion. The insulating layer 37 is formed, for example, using a silicon oxide film. The insulating layers 33 (charge storage layer, charge storage film) of the memory cell transistor MT on the left (first memory cell) and the insulating layers 33 (charge storage layer, charge storage film) of the memory cell transistor MT on the right (second memory cell) are separated, for example, by an insulating layer 30b.

[0100] In the first embodiment, an AlO layer 35 is provided around the memory column MP, for example. A barrier metal layer 36 is provided around the AlO layer 35, for example. The barrier metal layer 36 is formed using a TiN film, for example. A wiring layer 11, which functions as a word line WL, is provided around the barrier metal layer 36. The wiring layer 11 is formed using a tungsten film, for example.

[0101] Thus, at a certain position on the Z-axis, a storage column MP includes two storage cell transistors MT and MT, or two selection transistors ST1 and ST2 along the Y direction.

[0102] Figure 9 This is an equivalent circuit diagram of the memory column in the semiconductor memory device 1 of this embodiment. The equivalent circuit diagram of the memory column in this embodiment is not limited to... Figure 9 The equivalent circuit diagram is shown below. Figure 9 In the description, sometimes the terms "and" are omitted. Figures 1 to 8 Descriptions of the same or similar structures.

[0103] like Figure 9As shown, two NAND strings 50e and 50o are formed in one storage column MP. NAND string 50e has a select transistor ST1, memory cell transistors MT0-MT7, select transistor ST2, select transistor ST5, memory cell transistors MT8-MT15, and select transistor ST6 connected in series. NAND string 50o has a select transistor ST3, memory cell transistors MT0-MT7, select transistor ST4, select transistor ST7, memory cell transistors MT8-MT15, and select transistor ST8 connected in series. NAND string 50e and NAND string 50o are arranged in a face-to-face (opposite) manner. Therefore, the selection transistor ST1, memory cell transistors MT0 to MT7, selection transistor ST2, selection transistor ST5, memory cell transistors MT8 to MT15 and selection transistor ST6 included in the NAND string 50e are arranged in a 1-to-1 opposite manner to the selection transistor ST3, memory cell transistors MT0 to MT7, selection transistor ST4, selection transistor ST7, memory cell transistors MT8 to MT15 and selection transistor ST8 included in the NAND string 50o. Specifically, the selection transistor ST1 included in NAND string 50e and the selection transistor ST3 included in NAND string 50o are arranged in an opposite manner; the memory cell transistors MT0 to MT7 included in NAND string 50e and the memory cell transistors MT0 to MT7 included in NAND string 50o are arranged in a 1-to-1 opposite manner; the selection transistors ST2 included in NAND string 50e and the selection transistor ST4 included in NAND string 50o are arranged in an opposite manner; the selection transistors ST5 included in NAND string 50e and the selection transistor ST7 included in NAND string 50o are arranged in an opposite manner; the memory cell transistors MT8 to MT15 included in NAND string 50e and the memory cell transistors MT8 to MT15 included in NAND string 50o are arranged in a 1-to-1 opposite manner; and the selection transistors ST6 included in NAND string 50e and the selection transistor ST8 included in NAND string 50o are arranged in an opposite manner.

[0104] In the following description, the focus is primarily on the first storage column MP (e.g., Figure 4 MP4) and the second storage column MP adjacent to the first storage column MP (e.g., Figure 4 The example of the two storage columns MP (MP0) will be used to illustrate this.

[0105] The select transistor ST1 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGSLe, for example. The select transistor ST3 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGSLo, for example. The memory cell transistors MT0 to MT7 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP are connected to common word lines WLe0 to WLe7, for example. The memory cell transistors MT0 to MT7 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP are connected to common word lines WLo0 to WLo7, for example. The select transistor ST2 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGDLe0, for example. The select transistor ST4 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGDLo1, for example. The select transistor ST5 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGSUe, for example. The select transistor ST7 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGSUo, for example. The memory cell transistors MT8 to MT15 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP are connected to common word lines WLe8 to WLe15, for example. The memory cell transistors MT8 to MT15 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP are connected to common word lines WLo8 to WLo15, for example. The select transistor ST6 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGDU0, for example. The select transistor ST8 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP is connected to a common select gate line SGDU1 or SGDU3, for example.

[0106] exist Figure 9 In this structure, word lines WLe0~WLe7 are connected to shared word lines WLSe0~WLSe7 respectively, and word lines WLe15~WLe8 are connected to shared word lines WLSe0~WLSe7 respectively. Additionally, word lines WLo0~WLo7 are connected to shared word lines WLSo0~WLSo7 respectively, and word lines WLo15~WLo8 are connected to shared word lines WLSe0~WLSo7 respectively.

[0107] Furthermore, when considering, for example Figure 4 MP6 is used as the first storage column MP, including, for example Figure 4In the case where MP2 is used as the second storage pillar MP, the select transistor ST2 of the NAND string 50e disposed in the first storage pillar MP and the second storage pillar MP is connected, for example, to the common select gate line SGDLe2. The select transistor ST4 of the NAND string 50o disposed in the first storage pillar MP and the second storage pillar MP is connected, for example, to the common select gate line SGDLo3. The select transistor ST6 of the NAND string 50e disposed in the first storage pillar MP and the second storage pillar MP is connected, for example, to the common select gate line SGDU2. The select transistor ST8 of the NAND string 50o disposed in the first storage pillar MP and the second storage pillar MP is connected, for example, to the common select gate line SGDU1 or SGDU3. In addition, considering, for example, Figure 4 MP4 as the first storage column MP, including, for example Figure 4 The case is the same as that of MP0 as the second storage column MP.

[0108] As described above, the selection transistor ST1, memory cell transistors MT0-7, selection transistor ST2, selection transistor ST5, memory cell transistors MT8-15 and selection transistor ST6 included in NAND string 50e correspond to the selection transistor ST3, memory cell transistors MT0-7, selection transistor ST4, selection transistor ST7, memory cell transistors MT8-15 and selection transistor ST8 included in NAND string 50o.

[0109] Two NAND strings 50e and 50o within the same storage column MP are connected to the same bit line BL and the same source line SL.

[0110] use Figure 3 and Figure 4 The following explanation addresses the case where the select gate line SGD is selected. When any one of the select gate lines SGDU0 to SGDU3 is selected, a voltage is supplied to one wiring layer 10-0 to 10-3 corresponding to each select gate line to turn on the select transistor ST6. For example, when wiring layer 10-1 is selected, the eight select transistors ST6 located in memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 are turned on. As a result, the eight memory cell transistors MT belonging to the aforementioned memory pillars are selected. That is, one page is formed by the aforementioned eight memory cell transistors MT. The operation is the same when wiring layers other than wiring layer 10-1 are selected, so the explanation is omitted.

[0111] Figure 10This is another example of an equivalent circuit diagram showing a memory column (two adjacent NAND strings) in the semiconductor memory device 1 of this embodiment. The equivalent circuit diagram of the memory column in this embodiment is not limited to... Figure 9 The equivalent circuit diagram is shown below. Figure 10 In the description, sometimes the terms "and" are omitted. Figures 1 to 8 Description of the same or similar structure. In this equivalent circuit diagram, the memory cell transistors MT8~MT15 of the NAND string 50e located in the first memory pillar MP and the second memory pillar MP are respectively connected to the common word lines WLe8~WLe15. The memory cell transistors MT8~MT15 of the NAND string 50o located in the first memory pillar MP and the second memory pillar MP are respectively connected to the common word lines WLo8~WLo15. Moreover, in Figure 10 In this configuration, word lines WLe0~WLe7 are connected to shared word lines WLSe0~WLSe7, and word lines WLe8~WLe15 are connected to shared word lines WLSe0~WLSe7. Additionally, word lines WLo0~WLo7 are connected to shared word lines WLSo0~WLSo7, and word lines WLo8~WLo15 are connected to shared word lines WLSe0~WLSo7.

[0112] In addition to this and Figure 9 The equivalent circuit diagrams shown are the same. Regardless of Figure 9 The equivalent circuit diagram shown and Figure 10 In this embodiment, any of the equivalent circuit diagrams shown can be preferably used. Hereinafter, we will assume that any of them are used... Figure 10 An example of the equivalent circuit diagram will be used to illustrate this.

[0113] In this embodiment, the writing method for the memory cell transistor MT is, for example, TLC (Through-Limited Cell) method. Multiple memory cell transistors MT using the TLC method form eight threshold distributions (write levels). These eight threshold distributions are, for example, named sequentially from the lowest threshold voltage as "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level. Different 3-bit data are assigned to each of the "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level.

[0114] The semiconductor memory device 1 of this embodiment repeatedly executes a programming cycle during the write operation. The programming cycle includes, for example, a programming operation and a verification operation. The programming operation is an action that raises the threshold voltage of the selected memory cell transistor MT by injecting electrons into the charge accumulation layer in the selected memory cell transistor MT. Alternatively, the programming operation is an action that maintains the threshold voltage of the selected memory cell transistor MT by preventing the injection of electrons into the charge accumulation layer. The verification operation is an action that follows the programming operation, using a verification voltage to read the data until the threshold voltage of the selected memory cell transistor MT has reached a target level. Once the threshold voltage of the selected memory cell transistor MT has reached the target level, writing to it is prohibited.

[0115] In the semiconductor memory device 1 of this embodiment, by repeatedly executing a programming cycle including the programming and verification operations described above, the threshold voltage of the selected memory cell transistor MT rises to the target level.

[0116] Electrons accumulated in the charge accumulation layer are sometimes in an unstable state. Therefore, from the moment the programming operation ends, electrons accumulated in the charge accumulation layer of the memory cell transistor MT may detach from the charge accumulation layer over time. If electrons detach from the charge accumulation layer, the threshold voltage of the memory cell transistor MT decreases. Therefore, in the read operation performed after the write operation is completed, a read voltage lower than the verification voltage is used to address the potential decrease in the threshold voltage of the memory cell transistor over time. The read operation may also include a verification operation.

[0117] Figure 11 and Figure 12 This diagram illustrates the electrical connections of the sequence generator 24, voltage generation circuit 27, driver group 28, line decoder 29, and select gate line SGD or word line WL in this embodiment. The electrical connections of the sequence generator 24, voltage generation circuit 27, driver group 28, line decoder 29, and select gate line SGD or word line WL in this embodiment are not limited to... Figure 11 The face shown. In Figure 11 and Figure 12 In the description, sometimes the terms "and" are omitted. Figures 1-10 Description of similar or identical structures. The circuit including sequence generator 24, voltage generation circuit 27, driver group 28, and line decoder 29 is an example of a control circuit.

[0118] like Figure 11As shown, wiring layer 11, which functions as an even-number line WLe (or an even-number shared word line WLSe), can be connected to even-number line driver 28A, and wiring layer 11, which functions as an odd-number line WLo (or an odd-number shared word line WLSo), can be electrically connected to odd-number line driver 28B. As described above, even-number line driver 28A and odd-number line driver 28B are included in driver group 28. Driver group 28 is electrically connected to voltage generation circuit 27. Figure 11 and Figure 12 As shown, even-number line driver 28A and odd-number line driver 28B can also generate various voltages using the voltage supplied from voltage generation circuit 27. Furthermore, even-number line driver 28A can supply the generated voltage to the even-number lines WLe of each block BLK via line decoder 29A. Similarly, odd-number line driver 28B can supply the generated voltage to the odd-number lines WLo of each block BLK via line decoder 29B. Line decoders 29A and 29B are included in line decoder 29.

[0119] like Figure 12 As shown, and as described above, the sequence generator 24 can control the driver group 28, etc., to perform various operations such as writing and reading.

[0120] Figure 13 This is a schematic diagram illustrating the electrical connection between the even-digit line driver 28A and the line decoder 29A in this embodiment.

[0121] The even-number line driver 28A is connected to signal lines SGe0, SGe1, SGe2, SGe3, SGe4, SGe6, and signal lines CGe0, ..., CGe7, which are signal lines CGe. Furthermore, regarding signal lines CGe, for example, the same number of signal lines CGe as the number of even-numbered shared word lines WLSe within the block BLK are connected.

[0122] Signal line SGe0 is connected to the even-numbered select gate line SGSLe in each block BLK via transistor TR_SGe0. Transistor TR_SGe0 functions as a switch to turn the signal from signal line SGe0 on and off via block decoder 29A1.

[0123] Signal line SGe1 is connected to the select gate line SGSUe in each block BLK via transistor TR_SGe1. Transistor TR_SGe1 functions as a switch to turn the signal from signal line SGe1 on and off via block decoder 29A1.

[0124] Signal lines CGe0, ..., CGe7 are connected to the even-numbered shared word lines WLSe0, ..., WLSe7 in each block BLK via transistors TR_CGe0, ..., TRCGe7. Transistors TR_CGe0, ..., TRCGe7 function as switches to turn signals from signal lines CGe0, ..., CGe7 on and off via the block decoder 29A1.

[0125] Signal line SGe2 is connected to the select gate line SGDL0 in each block BLK via transistor TR_SGe2. Transistor TR_SGe2 functions as a switch to turn the signal from signal line SGe2 on and off via block decoder 29A1.

[0126] Signal line SGe3 is connected to the select gate line SGDU0 in each block BLK via transistor TR_SGe3. Transistor TR_SGe3 functions as a switch to turn the signal from signal line SGe3 on and off via block decoder 29A1.

[0127] Signal line SGe4 is connected to the select gate line SGDL2 in each block BLK via transistor TR_SGe4. Transistor TR_SGe4 functions as a switch to turn the signal from signal line SGe4 on and off via block decoder 29A1.

[0128] Signal line SGe6 is connected to the select gate line SGDU2 in each block BLK via transistor TR_SGe6. Transistor TR_SGe6 functions as a switch to turn the signal from signal line SGe6 on and off via block decoder 29A1.

[0129] Figure 14 This is a schematic diagram illustrating the electrical connection between the odd-number line driver 28B and the line decoder 29B in this embodiment.

[0130] Signal lines SGo0, SGo1, SGo2, SGo3, SGo4, SGo6, and signal lines CGo0, ..., CGo7 (as signal lines CGo) are connected to the odd-number line driver 28. Furthermore, regarding signal lines CGo, for example, the same number of signal lines CGo as the number of odd-numbered shared word lines WLSo within the block BLK are connected.

[0131] Signal line SGo0 is connected to the odd-numbered select gate line SGSLo in each block BLK via transistor TR_SGo0. Transistor TR_SGo0 functions as a switch to turn the signal from signal line SGo0 on and off via block decoder 29B1.

[0132] Signal line SGo1 is connected to the select gate line SGSUo in each block BLK via transistor TR_SGo1. Transistor TR_SGo1 functions as a switch to turn the signal from signal line SGo1 on and off via block decoder 29B1.

[0133] Signal lines CGo0, ..., CGo7 are connected to the odd-numbered shared word lines WLSo0, ..., WLSo7 in each block BLK via transistors TR_CGo0, ..., TRCGo7. Transistors TR_CGo0, ..., TRCGo7 function as switches to turn signals from signal lines CGo0, ..., CGo7 on and off via the block decoder 29B1.

[0134] Signal line SGo2 is connected to the select gate line SGDL1 in each block BLK via transistor TR_SGo2. Transistor TR_SGo1 functions as a switch to turn the signal from signal line SGo2 on and off via block decoder 29B1.

[0135] Signal line SGo3 is connected to the select gate line SGDU1 in each block BLK via transistor TR_SGo3. Transistor TR_SGo3 functions as a switch to turn the signal from signal line SGo3 on and off via block decoder 29B1.

[0136] Signal line SGo4 is connected to the select gate line SGDL3 in each block BLK via transistor TR_SGo4. Transistor TR_SGo4 functions as a switch to turn the signal from signal line SGo4 on and off via block decoder 29B1.

[0137] Signal line SGo6 is connected to the select gate line SGDU3 in each block BLK via transistor TR_SGo6. Transistor TR_SGo6 functions as a switch to turn the signal from signal line SGo6 on and off via block decoder 29B1.

[0138] Figure 15 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit 27 and the even-number line driver 28A in this embodiment.

[0139] The voltages Vread, VreadK, Vcg, and Vm, described later, are generated, for example, by the first charge pump circuit 27A, the second charge pump circuit 27B, the third charge pump circuit 27C, and the fourth charge pump circuit 27D within the voltage generation circuit 27. Furthermore, Vread, VreadK, Vcg, and Vm are maintained by the first regulator circuit 28A1, the second regulator circuit 28A2, the third regulator circuit 28A3, and the fourth regulator circuit 28A4 within the even-digit line driver 28A. Finally, Vread, VreadK, Vcg, and Vm are appropriately summed and supplied to signal lines CGe0, ..., CGe7.

[0140] Figure 16 This is a schematic diagram illustrating the electrical connection between the voltage generation circuit 27 and the odd-number line driver 28B in this embodiment.

[0141] Vread, VreadK, Vcg, and Vm are held by the first regulator circuit 28B1, the second regulator circuit 28B2, the third regulator circuit 28B3, and the fourth regulator circuit 28B4 within the odd-digit line driver 28B, respectively. Furthermore, Vread, VreadK, Vcg, and Vm are appropriately added together and supplied to signal lines CGe0, ..., CGe7.

[0142] In addition, Vpgm, Vpass, and VSGD, which are voltages described later, can also be supplied to the wiring in the same way.

[0143] (First Embodiment)

[0144] Figure 17 This diagram schematically illustrates the equivalent circuit of the memory columns (two adjacent NAND strings) in the semiconductor memory device of this embodiment, and the voltage applied to each memory cell transistor via the word line. Furthermore, the voltage in the third operation described later is also included.

[0145] Here, the selection transistor ST1, selection transistor ST2, and the memory cell transistors MT0 to MT7 connected between selection transistors ST1 and ST2 are referred to as the first substring. The selection transistor ST3, selection transistor ST4, and the memory cell transistors MT0 to MT7 connected between selection transistors ST3 and ST4 are referred to as the second substring. The selection transistor ST5, selection transistor ST6, and the memory cell transistors MT8 to MT15 connected between selection transistors ST5 and ST6 are referred to as the third substring. The selection transistor ST7, selection transistor ST8, and the memory cell transistors MT8 to MT15 connected between selection transistors ST7 and ST8 are referred to as the fourth substring.

[0146] Additionally, as mentioned above, when set to use Figure 10 The equivalent circuit diagram shows that the memory transistors MT0~MT7 of NAND string 50e and the memory cell transistors MT8~MT15 of NAND string 50e are connected to the common shared word lines WLSe0~WLSe7. Additionally, the memory transistors MT0~MT7 of NAND string 50o and the memory cell transistors MT8~MT15 of NAND string 50e are connected to the common shared word lines WLSo0~WLSo7.

[0147] Figure 18 This is a schematic diagram showing the timing of various signals during data readout in the semiconductor memory device of this embodiment.

[0148] Figure 18 (a) is a diagram schematically showing the voltage applied to the select gate line SG. Figure 18 (b) is a diagram schematically representing the voltage applied to the shared word line WLSe. Figure 18 (c) is a diagram schematically representing the voltage applied to the shared word line WLSo.

[0149] As an example, the read operation of the memory cell transistor MT12, whose gate is connected to word line WLe12 (shared word line WLSe4), is shown in the third substring of NAND string 50e.

[0150] In the following examples, Vss is an example of the 1st and 7th voltages, Vsg is an example of the 2nd voltage, Vcg is an example of the 3rd voltage, Vread is an example of the 4th voltage, Vpgm is an example of the 5th voltage, Vpass is an example of the 6th voltage, and Vdd is an example of the 8th voltage.

[0151] Additionally, Vss is approximately 0V, Vsg is approximately 2.5V, Vcg is approximately 1V, Vread is approximately 5V, Vpgm is approximately 20V, Vpass is approximately 10V, and Vdd is approximately 2.5V. However, the voltages mentioned above are just examples and are not limited to these.

[0152] The following explanation concerns the read operation of the memory cell transistor MT12, assuming, for example, that operations 1, 2, and 3 are performed. Here, it is assumed that operation 2 is performed after operation 1, and operation 3 is performed after operation 2.

[0153] First, let's explain the first operation. Vsg is applied to the select gate lines SGDU0, SGDU1, SGDU2, SGDU3, SGSUe, SGSUo, SGDL0, SGDL1, SGDL2, SGDL3, SGSLe, and SGSUo. This turns on select transistors ST8, ST7, ST6, ST5, ST4, ST3, ST2, and ST1.

[0154] Additionally, in the first operation, Vread is applied to the shared word lines WLSe0-7 and WLSo0-7. Vread is the voltage applied to the non-selected word lines during the read operation, and it is the voltage that turns on the memory cell transistor MT regardless of data retention.

[0155] Next, in the second action, Vss is applied to the shared word line WLSe4.

[0156] Next, in the third operation, a Vcg higher than Vss is applied to the shared word line WLSe4. Additionally, Vsg is applied to the select gate lines SGDU2, SGSUe, SGDL1, SGDL3, and SGSLo. This turns on the select transistors ST6, ST5, ST4, and ST3. Furthermore, Vss is applied to the select gate lines SGDU0, SGDU1, SGDU3, SGSUo, SGDL0, SGDL2, and SGSLe. This turns off the select transistors ST8, ST7, ST2, and ST1. Thus, the third and second substrings are energized. On the other hand, the first and fourth substrings are not energized.

[0157] Therefore, in the third substring, readout is performed only from the gate of memory cell transistor MT12, where Vcg is applied. Additionally, in the first substring, Vcg is also applied to the gate of memory cell transistor MT4. However, since select transistors ST1 and ST2 are turned off, no readout is performed.

[0158] Figure 20 This is a schematic diagram showing the timing of various signals during data readout in the semiconductor memory device of this embodiment. Figure 19 This diagram schematically illustrates the equivalent circuit of the memory columns (two adjacent NAND strings) in the semiconductor memory device of this embodiment, and the voltage applied to each memory cell transistor via the word line. Additionally, the voltages recorded are those used in the third operation described later.

[0159] Here, as an example, we show an example of the read operation of the memory cell transistor MT4, whose gate is connected to word line WLe4 (shared word line WLSe4), in the first substring of NAND string 50e.

[0160] Action 1 and Action 2 and Figure 18 The situation is the same as shown.

[0161] Next, in the third operation, a Vcg higher than Vss is applied to the shared word line WLSe4. Additionally, Vsg is applied to the select gate lines SGDU1, SGSUo, SGDL0, SGDL2, and SGSLe. This turns on select transistors ST8, ST7, ST2, and ST1. Furthermore, Vss is applied to the select gate lines SGDU0, SGDU2, SGDU3, SGSUe, SGDL1, SGDL3, and SGSLo. This turns off select transistors ST6, ST5, ST4, and ST3. Thus, the fourth and first substrings are energized. On the other hand, the third and second substrings are not energized.

[0162] Therefore, in the first substring, readout is performed only from the gate of memory cell transistor MT4, where Vcg is applied. Additionally, in the third substring, Vcg is also applied to the gate of memory cell transistor MT12. However, since select transistors ST6 and ST5 are turned off, no readout is performed.

[0163] Next, the effects of the semiconductor memory device of this embodiment will be described.

[0164] With the increasing density of semiconductor memory devices, the number of word lines (WL) is increasing. Here, if using... Figure 13 as well as Figure 14 As explained, each word line WL is provided with transistors TR_CGe0, ..., CGe7 and transistors TR_CGo0, ..., CGo7, which function as switches to turn signals from signal lines CGe0, ..., CGe7 and CGo0, ..., CGo7 on and off. These transistors, for example, are simply the product of the number of blocks BLK and the number of word lines within each block BLK. Therefore, with the increasing density of semiconductor memory devices, the increase in the number of transistors TR_CG connected to the word lines WL may actually become an obstacle to achieving higher density.

[0165] Therefore, in the semiconductor memory device of this embodiment, the word line WL in the first substring and the word line WL in the third memory cell string are respectively connected. In other words, the word line WL in the first substring and the word line WL in the third memory cell string are controlled together as a shared word line WLS. As a result, the number of transistors TR_CG connected to the word line WL can be reduced by, for example, by half. Therefore, high density of the semiconductor memory device can be achieved.

[0166] The semiconductor memory device according to this embodiment can provide a semiconductor memory device capable of high density.

[0167] (Second Implementation)

[0168] Figure 21 This diagram schematically illustrates the equivalent circuit of the memory columns (two adjacent NAND strings) and the voltage applied to each memory cell transistor via word lines in the first example of the semiconductor memory device of this embodiment.

[0169] As the first example of this embodiment, an example of the write operation of the memory cell transistor MT12, whose gate is connected to word line WLe12 (shared word line WLSe4), is shown in the third substring of NAND string 50e.

[0170] Applying Vsg to the select gate line SGDU0 turns on the select transistor ST6. On the other hand, applying Vss to the other select gate lines turns off the select transistors ST1, ST2, ST3, ST4, ST5, ST7, and ST8.

[0171] Additionally, Vpgm is applied to the shared word line WLSe4. Then, Vpass is applied to the shared word lines WLSe0-3, WLSe5-7, and WLSo0-7. Then, Vss is applied to the bit line BL. Thus, a write operation is performed on the memory cell transistor MT12 of the third substring. In addition, in the first substring, Vpgm is also applied to the gate of the memory cell transistor MT4. However, the channel of the memory cell transistor MT in the first substring is floated. The floated channel is coupled to the word line WL to which Vpass or Vpgm is applied, and the channel voltage increases to the boost voltage Vboost. Therefore, no write operation is performed to the memory cell transistor MT4. Furthermore, the channel voltages of the memory cell transistors MT in the second and fourth substrings are also increased to the boost voltage Vboost.

[0172] Figure 22 This diagram schematically illustrates the equivalent circuit of the memory columns (two adjacent NAND strings) and the voltage applied to each memory cell transistor via word lines in the second example of the semiconductor memory device of this embodiment.

[0173] As a second example of this embodiment, an example of the write operation of the memory cell transistor MT4, whose gate is connected to word line WLe4 (shared word line WLSe4), is shown in the first substring of NAND string 50o.

[0174] Applying Vsg to the select gate lines SGDU1, SGSUo, SGGSLo, and SGDLe0 turns on select transistors ST2, ST3, ST7, and ST8. Conversely, applying Vss to the other select gate lines turns off select transistors ST1, ST4, ST5, and ST6.

[0175] Additionally, Vpgm is applied to the shared word line WLSe4. Then, Vpass is applied to the shared word lines WLSe0-3, WLSe5-7, and WLSo0-7. Then, Vss is applied to the bit line BL. Thus, a write operation is performed on the memory cell transistor MT4 of the first substring. Furthermore, in the third substring, Vpgm is also applied to the gate of the memory cell transistor MT12. However, the channel voltage of the memory cell transistor MT in the third substring is floating, and the channel voltage is increased to the boost voltage Vboost. Therefore, no write operation is performed to the memory cell transistor MT12. Additionally, the channel voltage of the memory cell transistor MT in the second substring is also increased to the boost voltage Vboost.

[0176] Figure 23 This diagram schematically illustrates the equivalent circuit of the memory columns (two adjacent NAND strings) and the voltage applied to each memory cell transistor via word lines in the third example of the semiconductor memory device of this embodiment.

[0177] As a third example of this embodiment, an example of suppressing writes to the memory cell transistor MT12 is shown in other memory pillars MP having a memory cell transistor MT12 whose gate is connected to word line WLe12 (shared word line WLSe4). When Vdd is applied to the bit line, the select transistor ST6 becomes off. Therefore, the channel of the memory cell transistor in the third substring increases to the boost voltage Vboost. Therefore, writes to the memory cell transistor MT12 can be suppressed.

[0178] Figure 24 This diagram schematically illustrates the equivalent circuit of the memory columns (two adjacent NAND strings) and the voltage applied to each memory cell transistor via word lines in the fourth example of the semiconductor memory device in this embodiment.

[0179] As a fourth example of this embodiment, an example of suppressing writes to the memory cell transistor MT4 is shown in other memory pillars MP having a memory cell transistor MT4 whose gate is connected to the word line WLe4 (shared word line WLSe4). When Vdd is applied to the bit line, the select transistor ST8 becomes off. Therefore, the channel voltage of the memory cell transistor in the fourth substring increases to the boost voltage Vboost. Furthermore, the channels of the memory cell transistors in the first substring and the fourth substring are turned on. Therefore, the channel voltage of the memory cell transistors in the first substring also increases to the boost voltage Vboost. Thus, writes to the memory cell transistor MT4 can be suppressed.

[0180] The semiconductor memory device of this embodiment can also reduce the number of transistors TR_CG connected to the word line WL by, for example, half. Therefore, it is possible to achieve high density in semiconductor memory devices.

[0181] Furthermore, in the semiconductor memory device of this embodiment, the number of select gate lines is increased (e.g., select gate lines SGDLe, SGDLo, SGSUe, SGSUo). Therefore, the number of transistors TR_SG connected to the select gate lines increases. However, for example in… Figure 17 In the example shown, the number of transistors TR_CG connected to the word line WL is reduced by half. Furthermore, generally speaking, the highest voltage Vpgm applied to the word line WL is higher than the highest voltage Vsg applied to the select gate line SG. Therefore, the transistor TR_CG connected to the word line requires a higher voltage rating than the select transistor ST. Thus, the transistor TR_CG is a larger transistor than the select transistor ST. Here, to achieve high density in semiconductor memory devices, it is necessary to increase the number of memory cell transistors included in a substring. Therefore, in achieving high density in semiconductor memory devices, the miniaturization effect of reducing the number of transistors TR_CG is greater than the effect of increasing the size of the semiconductor memory device based on increasing the number of select transistors ST.

[0182] The semiconductor memory device of this embodiment can also provide a semiconductor memory device capable of high density.

[0183] Figure 25 In the semiconductor memory device of this embodiment, Figure 3 and Figure 4 The diagram shows the end face of the B1-B2 cut-off section of the semiconductor memory device. Figure 25 yes Figure 5 The diagram shows the storage columns MP4, MP5, MP6, and MP7, which are appended with dashed lines.

[0184] When reading out the memory cell transistors MT in the fourth substring of the selection transistor ST8, which has its gate connected to the selection gate line SGDU1, the selection transistors ST7, ST2, and ST1, whose gates are connected to the selection gate lines SGSUo, SGDL0, and SGSLe, are turned on.

[0185] However, the gate of the selection transistor ST6 included in the memory column MP1 is connected to the selection gate line SGDU1. In the memory column MP1, when performing a read operation on the memory cell transistor MT included in the third substring having the selection transistor ST6, it is preferable to further provide SGDL2 to the selection gate line SGDL. In other words, regarding the selection gate line SGDL provided on the selection gate line SGGSLe, it is preferable to provide at least two types: selection gate line SGDL0 and selection gate line SGDL2. Similarly, regarding the selection gate line SGDL provided on the selection gate line SGGSLo, it is preferable to provide at least two types: selection gate line SGDL1 and selection gate line SGDL3. Similarly, regarding the selection gate line SGLU provided on the selection gate line SGSUe, it is preferable to provide at least two types: selection gate line SGDU0 and selection gate line SGDU2. Similarly, regarding the selection gate line SGLU provided on the selection gate line SGSUo, it is preferable to provide at least two types: selection gate line SGDU1 and selection gate line SGDU3. Thus, it is possible to implement... Figure 18 as well as Figure 20 Control as shown.

[0186] The semiconductor memory device of this embodiment can also provide a semiconductor memory device capable of high density.

[0187] Several embodiments and examples of the present invention have been described, but these embodiments and examples are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0188] [Explanation of reference numerals in the attached figures]

[0189] 1: Semiconductor memory devices

[0190] 2: Storage Controller

[0191] 3: Storage System

[0192] 10: Wiring layer

[0193] 11: Wiring Layer

[0194] 12: Wiring layer

[0195] 13: Source Line Layer

[0196] 16: Contact plug

[0197] 17: Contact plug

[0198] 18: Metal wiring layer

[0199] 19: Contact plug

[0200] 20: Metal wiring layer

[0201] 21: Memory cell array

[0202] 22: Input / output circuit

[0203] 23: Logic control circuit

[0204] 24: Sequence Generator

[0205] 25: Register

[0206] 26: Ready / Busy Control Circuit

[0207] 27: Voltage generation circuit

[0208] 27A: First charge pump circuit

[0209] 27B: Second charge pump circuit

[0210] 27C: Third charge pump circuit

[0211] 27D: Fourth charge pump circuit

[0212] 28: Drive Group

[0213] 28A: Even-digit line driver

[0214] 28A1: First Regulator Circuit

[0215] 28A2: Second Regulator Circuit

[0216] 28A3: Third Regulator Circuit

[0217] 28A4: Fourth Regulator Circuit

[0218] 28B: Odd Number Line Driver

[0219] 28B1: First Regulator Circuit

[0220] 28B2: Second Regulator Circuit

[0221] 28B3: Third Regulator Circuit

[0222] 28B4: Fourth Regulator Circuit

[0223] 29: Line Decoder

[0224] 29A: Line Decoder

[0225] 29B: Line decoder

[0226] 30: Readout Amplifier

[0227] 31: Semiconductor layer

[0228] 32: Insulation layer

[0229] 33: Insulation layer

[0230] 34: Insulation layer

[0231] 35: AlO layer

[0232] 36: Barrier Metal Layer

[0233] 37: Insulation layer

[0234] 40: Semiconductor layer

[0235] 41: Insulation layer

[0236] 42: Conductive layer

[0237] 43: Insulation layer

[0238] 45: AlO layer

[0239] 46: Insulation layer

[0240] 47: Barrier Metal Layer

[0241] 48: Insulation layer

[0242] 50: NAND string

[0243] 70: Readout Amplifier

[0244] 71: Input / output pad group

[0245] 72: Logic control pad set

[0246] BL: Bitline

[0247] BLK: Block

[0248] C: Coupling capacitor

[0249] CEn: Chip enable signal

[0250] CG: Signal Line

[0251] CLE: Instruction Latch Enable Signal

[0252] CMD: Commands

[0253] DAT: Data

[0254] DQ: Signal

[0255] SU: Serial Unit

[0256] MP: Same storage column

[0257] MT: Memory cell transistor

[0258] R: Resistance component

[0259] REn: Read enable signal

[0260] SG: Signal line

[0261] SGD: Select Gate Line

[0262] SGS: Select Gate Line

[0263] SL: Source Line

[0264] SL: Slit

[0265] ST: Select Transistor

[0266] STS: Status Information

[0267] WLe: Even number line

[0268] WLo: Odd Number Line

[0269] WPn: Write-protect signal

Claims

1. A semiconductor memory device comprising: substrate; The first storage column extends from the substrate along a first direction and has: Multiple first-cell transistors are connected in series and have a first end and a second end; The first selection transistor is electrically connected to the first terminal; The second selection transistor is electrically connected to the second terminal; A plurality of second memory cell transistors are electrically insulated from the plurality of first memory cell transistors, the plurality of second memory cell transistors are connected in series and electrically connected to each other, and have a third end and a fourth end; The third selection transistor electrically connects the first selection transistor to the third terminal; The fourth selection transistor electrically connects the second selection transistor to the fourth terminal; Multiple third-cell transistors are connected in series and have a fifth end and a sixth end; The fifth selection transistor electrically connects the second and fourth selection transistors to the fifth terminal. The sixth selection transistor is electrically connected to the sixth terminal; A plurality of fourth memory cell transistors, electrically insulated from the plurality of third memory cell transistors, are connected in series and electrically connected to each other, and have a seventh end and an eighth end; The 7th selection transistor electrically connects the 2nd selection transistor, the 4th selection transistor, and the 5th selection transistor to the 7th terminal; as well as The 8th selection transistor electrically connects the 6th selection transistor to the 8th terminal; The first selection gate line is disposed on the substrate, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gate of the first selection transistor. Multiple first word lines are disposed above the first selected gate line, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gates of the multiple first memory cell transistors respectively. The second selection gate line is disposed above the plurality of first word lines, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gate of the second selection transistor. The third selection gate line is disposed on the substrate, parallel to the substrate surface of the substrate, and is positioned in the first direction at the same position as the first selection gate line in the first direction. It is opposite to the second side of the first memory pillar and is electrically connected to the gate of the third selection transistor. Multiple second word lines are disposed above the third select gate line, parallel to the substrate surface of the substrate, and are positioned in the first direction at the same position as the multiple first word lines in the first direction. They are opposite to the second side of the first memory pillar and are electrically connected to the gates of the multiple second memory cell transistors. The fourth selection gate line is disposed above the plurality of second word lines, parallel to the substrate surface of the substrate, and is positioned in the first direction at the same position as the second selection gate line in the first direction. It is opposite to the second side of the first memory pillar and is electrically connected to the gate of the fourth selection transistor. The fifth selection gate line is disposed on the substrate, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gate of the fifth selection transistor. Multiple third word lines are disposed above the fifth select gate line, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gates of the multiple third memory cell transistors and the multiple first word lines respectively. The sixth select gate line is disposed above the plurality of third word lines, parallel to the substrate surface of the substrate, opposite to the first side of the first memory pillar, and electrically connected to the gate of the sixth select transistor. The 7th select gate line is disposed on the substrate, parallel to the substrate surface of the substrate, and is positioned in the first direction at the same position as the 5th select gate line in the first direction. It is opposite to the second side of the 1st memory pillar and is electrically connected to the gate of the 7th select transistor. Multiple fourth word lines are disposed above the seventh select gate line, parallel to the substrate surface of the substrate, and are positioned in the first direction at the same position as the multiple third word lines in the first direction. They are opposite to the second side of the first memory pillar and are electrically connected to the gates of the multiple fourth memory cell transistors and the multiple second word lines, respectively. as well as The 8th select gate line is disposed above the plurality of 4th word lines, parallel to the substrate surface of the substrate, and is positioned in the 1st direction at the same position as the 6th select gate line in the 1st direction. It is opposite to the 2nd side of the 1st memory pillar and is electrically connected to the gate of the 8th select transistor.

2. The semiconductor memory device according to claim 1, It also has control circuitry. This control circuit, A first voltage is applied to the first selected gate line, the second selected gate line, the seventh selected gate line, and the eighth selected gate line. A second voltage, higher than the first voltage, is applied to the third, fourth, fifth, and sixth selected gate lines. A third voltage higher than the first voltage and lower than the second voltage is applied to one of the plurality of first word lines, and a fourth voltage higher than the second voltage is applied to the plurality of second word lines and the other plurality of first word lines.

3. The semiconductor memory device according to claim 1, It also has control circuitry. This control circuit, A first voltage is applied to the third, fourth, fifth, and sixth select gate lines. A second voltage, higher than the first voltage, is applied to the first selected gate line, the second selected gate line, the third selected gate line, and the fourth selected gate line. A third voltage higher than the first voltage and lower than the second voltage is applied to one of the plurality of first word lines, and a fourth voltage higher than the second voltage is applied to the plurality of second word lines and the other plurality of first word lines.

4. The semiconductor memory device according to claim 1, It also has control circuitry. This control circuit, A first voltage is applied to the first selected gate line, the second selected gate line, the third selected gate line, the fourth selected gate line, the fifth selected gate line, the seventh selected gate line, and the eighth selected gate line. A second voltage, higher than the first voltage, is applied to the sixth selected gate line. A fifth voltage, higher than the second voltage, is applied to one of the plurality of first word lines, and a sixth voltage, lower than the fifth voltage, is applied to the plurality of second word lines and the other plurality of first word lines. A seventh voltage, which is lower than the second voltage, is applied to the first bit line.

5. The semiconductor memory device according to claim 1, It also has control circuitry. This control circuit, A first voltage is applied to the first selected gate line, the fourth selected gate line, the fifth selected gate line, and the sixth selected gate line. A second voltage higher than the first voltage is applied to the second, third, seventh, and eighth selected gate lines. A fifth voltage, higher than the second voltage, is applied to one of the plurality of first word lines. A sixth voltage, lower than the fifth voltage, is applied to the plurality of second word lines and the other plurality of first word lines. A seventh voltage, which is lower than the second voltage, is applied to the first bit line.

6. The semiconductor memory device according to claim 1, further comprising: The second storage column extends from the substrate along the first direction and has: Multiple fifth-cell transistors are connected in series and have a ninth end and a tenth end; The 9th selection transistor is electrically connected to the 9th terminal; The 10th selection transistor is electrically connected to the 10th terminal; A plurality of sixth memory cell transistors, electrically insulated from the plurality of fifth memory cell transistors, are connected in series and electrically connected to each other, and have an eleventh end and a twelfth end; The 11th selection transistor electrically connects the 9th selection transistor to the 11th terminal; The 12th selection transistor electrically connects the 10th selection transistor to the 12th terminal; Multiple 7th memory cell transistors are connected in series and have 13th and 14th terminals; The 13th selection transistor electrically connects the 10th selection transistor and the 12th selection transistor to the 13th terminal; The 14th selection transistor is electrically connected to the 14th terminal; A plurality of eighth memory cell transistors, electrically insulated from the plurality of seventh memory cell transistors, are connected in series and electrically connected to each other, and have a 15th end and a 16th end; The 15th selection transistor electrically connects the 10th selection transistor, the 12th selection transistor, and the 13th selection transistor to the 15th terminal; as well as The 16th selection transistor electrically connects the 8th selection transistor to the 16th terminal; The 9th select gate line is disposed above the plurality of 1 word lines, parallel to the substrate surface of the substrate, opposite to the 3rd side of the 2nd memory pillar, and electrically connected to the gate of the 10th select transistor. The 10th select gate line is disposed above the plurality of 2nd word lines, parallel to the substrate surface of the substrate, opposite to the 4th side of the 2nd memory pillar, and electrically connected to the gate of the 12th select transistor. The 11th select gate line is disposed above the plurality of 3rd word lines, parallel to the substrate surface of the substrate, opposite to the 3rd side of the 2nd memory pillar, and electrically connected to the gate of the 14th select transistor. as well as The 12th select gate line is disposed above the plurality of 4th word lines, parallel to the substrate surface of the substrate, opposite the 4th side of the 2nd memory pillar, and electrically connected to the gate of the 16th select transistor. The plurality of first word lines are electrically connected to the gates of the plurality of fifth memory cell transistors and the gates of the plurality of seventh memory cell transistors, respectively. The plurality of second word lines are respectively connected to the gates of the plurality of sixth memory cell transistors and the gates of the plurality of eighth memory cell transistors. The first selected gate line is also electrically connected to the gate of the ninth selected transistor. The third selected gate line is also electrically connected to the gate of the eleventh selected transistor. The fifth selected gate line is also electrically connected to the gate of the 13th selected transistor. The 7th selected gate line is also electrically connected to the gate of the 15th selected transistor.

Images