Method for improving gate critical dimension uniformity, computer device and storage medium

Abstract

The application provides a method for improving the uniformity of gate critical dimensions, comprising: providing a semiconductor structure formed with a gate polysilicon layer; placing the semiconductor structure in different film forming machines respectively to form an APF layer on the surface of the gate polysilicon layer; placing the semiconductor structure formed with the APF layer in different photolithography machines respectively to form a photoresist layer on the surface of the APF layer; placing the semiconductor structure formed with the photoresist layer in different etching machines respectively to etch the APF layer and the gate polysilicon layer to form a gate; obtaining the critical dimensions of the gate formed by each film forming machine, each photolithography machine and each etching machine, and determining the defect machine which has an impact on the critical dimensions according to the critical dimensions; and performing photolithography compensation on the semiconductor structure which will use the defect machine in the future to improve the uniformity of the critical dimensions of the gate. The application solves the problem of poor uniformity of the critical dimensions of the gate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method, computer device, and storage medium for improving the uniformity of gate critical dimensions. Background Technology

[0002] As integrated circuit technology enters the era of very large-scale integrated circuits, the process size of integrated circuits is developing towards structures of 65nm and below, which places higher and more detailed technical requirements on wafer processing. The critical dimension of the polysilicon gate on the wafer is increasingly becoming an important parameter for polysilicon etching. The critical dimension of the gate determines the operating performance of the device and has an increasingly significant impact on the wafer yield.

[0003] The gate critical dimension is affected by the interaction of various processes, such as the uniformity of photolithography and the etching chamber. Currently, in order to improve the impact on the uniformity of the gate critical dimension, the common approach is to obtain different combinations of compensation values, take the average of these compensation values, and then perform compensation. However, this approach cannot provide accurate compensation, and the accuracy of the compensation is limited, which cannot meet the current requirements. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method, computer device and storage medium for improving the uniformity of gate critical dimensions, so as to solve the problem of poor uniformity of critical dimensions of existing gates.

[0005] To achieve the above and other related objectives, the present invention provides a method for improving the uniformity of gate critical dimensions, the method comprising:

[0006] Provides a semiconductor structure with a gate polysilicon layer formed thereon;

[0007] The semiconductor structure is placed in different film deposition machines to form an APF layer on the surface of the gate polysilicon layer;

[0008] The semiconductor structure on which the APF layer is formed is placed in different lithography machines to form a photoresist layer on the surface of the APF layer;

[0009] The semiconductor structure on which the photoresist layer is formed is placed in different etching machines to etch the APF layer and the gate polysilicon layer to form the gate.

[0010] The critical dimensions of the gate formed by each of the film-forming equipment, each of the lithography equipment and each of the etching equipment are obtained, and the defective equipment that affects the gate is determined based on the critical dimensions.

[0011] Photolithographic compensation is performed on the semiconductor structure that will be used in the defective equipment to improve the uniformity of the critical dimensions.

[0012] Optionally, the film-forming equipment includes a machine for forming the APF layer by spraying, spin coating, vapor deposition, electroplating, or deposition.

[0013] Optionally, before etching the APF layer and the gate polysilicon layer, the method includes: patterning the photoresist layer to define the pattern of the APF layer.

[0014] Optionally, when etching the APF layer and the gate polysilicon layer, the APF layer, which is etched first, is used as a mask layer.

[0015] Optionally, the method for photolithographic compensation of the semiconductor structure that will subsequently utilize the defective machine includes: correcting the exposure energy in the photolithography process.

[0016] The present invention also provides a computer device including a processor and a memory, the processor being adapted to implement various instructions, the memory being adapted to store a plurality of instructions, wherein the instructions are adapted to be loaded by the processor and executed as described above for improving gate critical size uniformity.

[0017] The present invention also provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are executed to implement the method for improving gate critical dimension uniformity as described above.

[0018] As described above, the method, computer device, and storage medium for improving gate critical dimension uniformity of the present invention, after forming an APF layer on the surface of the gate polysilicon layer, identify the defective equipment that ultimately affects the gate critical dimension and determine whether the APF layer affects the gate critical dimension. Furthermore, photolithographic compensation is performed on the semiconductor structure that will subsequently utilize the defective equipment, thereby achieving precise compensation of the gate critical dimension to improve gate critical dimension uniformity. Attached Figure Description

[0019] Figure 1 The diagram shown is a flowchart of the method for improving gate critical dimension uniformity according to the present invention. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] like Figure 1 As shown, this embodiment provides a method for improving the uniformity of gate critical dimensions, the method comprising:

[0023] Step 1) Provide a semiconductor structure with a gate polysilicon layer formed thereon;

[0024] Step 2) The semiconductor structure is placed in different film deposition machines to form an APF layer on the surface of the gate polysilicon layer;

[0025] Step 3) The semiconductor structure with the APF layer formed is placed in different photolithography machines to form a photoresist layer on the surface of the APF layer;

[0026] Step 4) The semiconductor structure on which the photoresist layer is formed is placed in different etching machines to etch the APF layer and the gate polysilicon layer to form the gate;

[0027] Step 5) Obtain the critical dimensions of the gate formed by each of the film deposition machines, each of the lithography machines and each of the etching machines, and determine the defective machines that affect them based on the critical dimensions;

[0028] Step 6) Photolithographic compensation will be performed on the semiconductor structure that will be used in the defective equipment to improve the uniformity of the gate critical dimension.

[0029] In step 1), a semiconductor structure with a gate polysilicon layer is provided.

[0030] In this embodiment, the semiconductor structure further includes a semiconductor substrate and a gate dielectric layer formed on the surface of the semiconductor substrate, and the gate polysilicon layer is formed on the surface of the gate dielectric layer.

[0031] In step 2), the semiconductor structure is placed in different film deposition machines to form an APF layer on the surface of the gate polysilicon layer.

[0032] In this embodiment, different film-forming equipment is used to form the APF layer in order to determine whether the film-forming equipment affects the critical dimensions of the gate.

[0033] Specifically, the film-forming equipment includes equipment for forming the APF layer by spraying, spin coating, vapor deposition, electroplating, or deposition.

[0034] In step 3), the semiconductor structure with the APF layer is placed in different photolithography machines to form a photoresist layer on the surface of the APF layer.

[0035] In this embodiment, different lithography machines are used to form the photoresist layer in order to determine whether the lithography machine affects the critical dimensions of the gate.

[0036] In step 4), the semiconductor structure on which the photoresist layer is formed is placed in different etching machines to etch the APF layer and the gate polysilicon layer to form the gate.

[0037] In this embodiment, different etching machines are used to etch the APF layer and the gate polysilicon layer in order to determine whether the etching machine affects the critical dimensions of the gate.

[0038] Specifically, before etching the APF layer and the gate polysilicon layer, the method includes: patterning the photoresist layer to define the pattern of the APF layer.

[0039] Specifically, when etching the APF layer and the gate polysilicon layer, the APF layer, which is etched first, serves as a mask layer.

[0040] In step 5), the critical dimensions of the gate formed by each of the film-forming machines, each of the lithography machines and each of the etching machines are obtained, and the defective machines that affect the gate are determined based on the critical dimensions.

[0041] Specifically, the method for photolithographic compensation of the semiconductor structure using the defective machine includes: correcting the exposure energy in the photolithography process.

[0042] In step 6), the semiconductor structure that will be used in the defect machine is photolithographically compensated to improve the uniformity of the gate critical dimension.

[0043] In this embodiment, after the defective machine is determined through steps 1) to 5), a new recipe is created. The new recipe includes the corrected exposure energy. The critical dimension uniformity of the gate is improved by using the corrected exposure energy for exposure.

[0044] This embodiment also provides a computer device, including a processor and a memory, wherein the processor is adapted to implement various instructions, and the memory is adapted to store multiple instructions, wherein the instructions are adapted to be loaded by the processor and executed as described above for improving gate critical size uniformity.

[0045] This embodiment also provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are executed to implement the method for improving gate critical dimension uniformity as described above.

[0046] In summary, the method, computer device, and storage medium for improving gate critical dimension uniformity of the present invention, after forming an APF layer on the surface of the gate polysilicon layer, identify the defective equipment that ultimately affects the gate critical dimension and determine whether the APF layer affects the gate critical dimension. Furthermore, photolithographic compensation is performed on the semiconductor structure that will subsequently utilize the defective equipment, thereby achieving precise compensation of the gate critical dimension to improve gate critical dimension uniformity. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the uniformity of gate critical dimensions, characterized in that, The method includes: Provides a semiconductor structure with a gate polysilicon layer formed thereon; The semiconductor structure is placed in different film deposition machines to form an APF layer on the surface of the gate polysilicon layer; The semiconductor structure on which the APF layer is formed is placed in different lithography machines to form a photoresist layer on the surface of the APF layer; The semiconductor structure on which the photoresist layer is formed is placed in different etching machines to etch the APF layer and the gate polysilicon layer to form the gate. The critical dimensions of the gate formed by each of the film-forming equipment, each of the lithography equipment and each of the etching equipment are obtained, and the defective equipment that affects the gate is determined based on the critical dimensions. Photolithographic compensation is performed on the semiconductor structure that will be used in the defective equipment to improve the uniformity of the critical dimensions.

2. The method for improving the uniformity of gate critical dimensions according to claim 1, characterized in that, The film-forming equipment includes equipment that forms the APF layer by spraying, spin coating, vapor deposition, electroplating, or deposition.

3. The method for improving the uniformity of gate critical dimensions according to claim 1, characterized in that, Before etching the APF layer and the gate polysilicon layer, the method includes: patterning the photoresist layer to define the pattern of the APF layer.

4. The method for improving the uniformity of gate critical dimensions according to claim 1, characterized in that, When etching the APF layer and the gate polysilicon layer, the APF layer, which is etched first, serves as a mask layer.

5. The method for improving the uniformity of gate critical dimensions according to claim 1, characterized in that, The method for photolithographic compensation of the semiconductor structure that will be used in the defective equipment includes: correcting the exposure energy in the photolithography process.

6. A computer device, characterized in that, The device includes a processor and a memory, the processor being adapted to implement various instructions, and the memory being adapted to store multiple instructions, wherein the instructions are adapted to be loaded by the processor and executed as described in any one of claims 1 to 5 to improve gate critical dimension uniformity.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, wherein the computer-executable instructions are executed to implement the method for improving gate critical dimension uniformity as described in any one of claims 1 to 5.

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