Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes providing a wafer including a middle region and an edge region surrounding the middle region, forming a target layer on the middle region and the edge region of the wafer, forming a mask pattern layer on the target layer, and the thickness of the mask pattern layer on the edge region is less than the thickness of the mask pattern layer on the middle region; etching the target layer with the mask pattern layer as a mask to form a target structure in the target layer on the middle region and the edge region. The foregoing method can prevent the problem that the etching depths of devices in different regions of the wafer are different, thereby improving the performance of the devices.

Description

Technical Field

[0001] This application relates to the field of memory fabrication, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] In the fabrication process of existing semiconductor structures (such as DRAM), different regions of the wafer have different etching depths, which affects the performance of the devices. Summary of the Invention

[0004] In view of this, some embodiments of this application provide a method for forming a semiconductor structure, including:

[0005] A wafer is provided, the wafer including a central region and an edge region surrounding the central region;

[0006] A target layer is formed on the middle and edge regions of the wafer;

[0007] A mask pattern layer is formed on the target layer, and the thickness of the mask pattern layer on the edge region is less than the thickness of the mask pattern layer on the middle region;

[0008] Using the mask pattern layer as a mask, the target layer is etched to form a target structure in the target layer in the middle and edge regions.

[0009] In some embodiments, the target layer comprises a stacked structure formed by alternating layers of sacrificial and support layers. The formation process of the mask layer is as follows: a mask material layer is formed on the stacked structure; the mask material layer is ground by a chemical mechanical polishing process to form a mask layer, wherein during the grinding process, the grinding rate of the mask material layer on the edge region is greater than the grinding rate of the mask material layer on the middle region, such that the thickness of the formed mask layer on the edge region is less than the thickness on the middle region; and the mask layer is patterned to form a mask pattern layer.

[0010] In some embodiments, during the grinding process, the wafer is held by a grinding head, the mask material layer on the wafer is attached to the grinding pad, and pressure is applied by the grinding head. The grinding head applies greater pressure to the edge region of the wafer than to the middle region of the wafer during the grinding process, thereby making the grinding rate of the mask material layer on the edge region greater than that on the middle region.

[0011] In some embodiments, the grinding head applies 15%-35% greater pressure to the edge region of the wafer than to the center region of the wafer during the grinding process.

[0012] In some embodiments, the edge region is an annular region located 5-10 mm from the edge of the wafer.

[0013] In some embodiments, the thickness of the mask pattern layer on the edge region is 0.5%-5% smaller than the thickness of the mask pattern layer on the middle region.

[0014] In some embodiments, the thickness of the mask pattern layer on the edge region is less than the thickness of the mask pattern layer on the middle region by a numerical range of 3nm-10nm.

[0015] In some embodiments, the mask pattern layer is a single-layer or multi-layer stacked structure, and an etch stop layer is further provided between the mask pattern layer and the stacked structure.

[0016] In some embodiments, the material of the mask pattern layer may be one or more of polycrystalline silicon, amorphous silicon, amorphous carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0017] In some embodiments, the thickness of the mask pattern layer on the edge region gradually decreases from near the center region to far away from the center region.

[0018] In some embodiments, the target structure includes a plurality of capacitor holes formed between the stacked structures, and the forming method further includes: forming lower electrodes on the sidewalls and bottom surfaces of the capacitor holes, removing the sacrificial layer between the lower electrodes, and forming a cavity.

[0019] In some embodiments, a bottom dielectric layer is further formed on the middle region and the edge region of the wafer, and a plurality of lower electrode contact pads are further formed in the bottom dielectric layer on the middle region and the edge region; the stacked structure is formed on the bottom dielectric layer, and the bottom of the plurality of capacitor holes exposes the corresponding lower electrode contact pads.

[0020] In some embodiments, the method further includes: forming a dielectric layer on the surface of the lower electrode and the inner wall surface of the cavity; and forming an upper electrode layer on the surface of the dielectric layer.

[0021] In some embodiments, the material of the support layer is different from the material of the sacrificial layer.

[0022] In some embodiments, the number of layers of the support layer and the sacrificial layer is at least one.

[0023] The method for forming a semiconductor structure in some of the foregoing embodiments of this application provides a wafer, the wafer including a central region and an edge region surrounding the central region. After forming a target layer on the central region and the edge region of the wafer, a mask pattern layer is formed on the target layer, and the thickness of the mask pattern layer on the edge region is less than the thickness of the mask pattern layer on the central region. Using the mask pattern layer as a mask, the target layer is etched to form a target structure in the target layer on the central region and the edge region. The thickness of the mask pattern layer in the edge region is less than that in the middle region. When etching the target layer using the mask pattern layer as a mask to form the target structure, even if the amount of plasma distributed in the edge region is less than that in the middle region, the thinner mask pattern layer in the edge region reduces the blocking effect of the mask pattern layer on the plasma, and the time it takes for the plasma to reach the surface of the target layer in the edge region is also reduced. This results in an increase in the amount of plasma reaching the surface of the target layer in the edge region per unit time. Consequently, during the etching process, the amount of plasma on the surface of the target layer in the edge region and the middle region are comparable, and the etching rates of the target layer in the edge region and the middle region are comparable. When the etching process is completed, the depth of the target structure formed in the target layer in the edge region and the middle region is comparable, thereby preventing under-etching defects in the final target structure formed in the edge region. This also prevents the problem of different etching depths in different areas of the wafer, thereby improving the performance of the device. Furthermore, since there is no over-etching of the target structure formed in the middle region, the size uniformity of the target structure formed on the edge region and the middle region is relatively high. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the DRAM formation process in some embodiments;

[0025] Figures 2-6 , Figures 10-12 This is a schematic diagram of the DRAM formation process in some other embodiments;

[0026] Figure 7Here are schematic diagrams of the grinding apparatus in some embodiments:

[0027] Figure 8 This is a partial structural diagram of the grinding head in some embodiments;

[0028] Figure 9 This is a tabular diagram showing the pressure applied to the grinding head in some embodiments. Detailed Implementation

[0029] As mentioned in the background section, devices in different areas of a wafer have different etching depths, which in turn affects the performance of the devices.

[0030] refer to Figure 1 In some embodiments, the method for forming a semiconductor structure includes: providing a wafer 301, the wafer 301 including a central region 31 and an edge region 32 surrounding the central region 31; forming a first sacrificial layer 303 on the wafer 301; forming a first support layer 304 on the first sacrificial layer 303; forming a second sacrificial layer 305 on the first support layer 304; forming a second support layer 306 on the second sacrificial layer 305; forming a patterned mask layer (not shown in the figure) on the second support layer 306; and etching away a portion of the first support layer using the patterned mask layer as a mask. Layer 303, first sacrificial layer 304, first support layer 305, and first sacrificial layer 306 form a plurality of capacitor holes 311; a lower electrode (not shown in the figure) is formed on the sidewall and bottom surface of the capacitor holes 311; after the lower electrode is formed, the remaining first sacrificial layer 303 and second sacrificial layer 305, as well as part of the remaining first support layer 304 and second support layer 306, are removed to form a cavity (not shown in the figure); a dielectric layer (not shown in the figure) is formed on the surface of the lower electrode and the sidewall surface of the cavity; an upper electrode (not shown in the figure) is formed on the surface of the dielectric layer.

[0031] Further research revealed that during the formation of capacitor holes 311, some capacitor holes 311 on the edge region 32 exhibited under-etching defects 313 (specifically, the first sacrificial layer 303 on the edge region 32 was not etched through, resulting in some first sacrificial layer material remaining at the bottom of the capacitor holes 311 formed on the edge region 32 and connecting with the first sacrificial layer material on both sides of the capacitor holes 313. The specific reason for the under-etching defect 313 is that during etching, the amount of plasma in the edge region of the wafer is less. Under the same thickness of mask layer, the etching rate on the edge region of the wafer is slower during the etching process, resulting in different etching depths between the edge region and the middle region of the wafer). Further research revealed that after forming the lower electrode (not shown in the figure) on the sidewall and bottom surface of the capacitor hole 311, a portion of the remaining second support layer 306 is subsequently removed to form an opening exposing the remaining second sacrificial layer 305. The remaining second sacrificial layer 305, along with a portion of the remaining first support layer 304 and the remaining first sacrificial layer 303 at the bottom of the opening, are removed through etching at the opening to form a cavity. Because some capacitor holes 311 on the edge region 32 may have under-etched defects 313 during cavity formation, the second sacrificial layer 303 at the under-etched defects 313 is also completely removed during the removal of the second sacrificial layer 303. This results in the bottom of the lower electrode layer formed on the sidewall and bottom of the capacitor hole 311 on the edge region 32 being suspended, leading to extreme mechanical instability. Consequently, the lower electrode layer (capacitor pattern) formed on the edge region 32 is prone to detachment or peeling defects. Although the under-etching defect 313 can be prevented by increasing the etching time, this will cause over-etching of the capacitor hole 311 already formed in the middle region 31, resulting in an enlarged size of the capacitor hole in the middle region 31, which in turn causes the size of the capacitor hole to be uneven and affects the performance of the device.

[0032] To address this issue, some embodiments of this application provide a method for forming a memory device, which can prevent the problem of different etching depths in different areas of the wafer, thereby improving device performance. To make the above-mentioned objects, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of this application, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and these schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0033] refer to Figure 2 and Figure 3 , Figure 3 for Figure 2A cross-sectional view along the cutting line AB shows a wafer 201, which includes a central region 21 and an edge region 22 surrounding the central region 21.

[0034] The material of wafer 201 can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the material of wafer 201 is silicon.

[0035] The wafer 201 includes a central region 21 and an edge region 22 surrounding the central region 21. The edge region 21 is a region close to the edge of the wafer 201. In some embodiments, the edge region 21 is an annular region at a distance of 5-10 mm from the edge of the wafer 201.

[0036] In some embodiments, the middle region 21 and the edge region 22 of the wafer 201 each include a plurality of discrete chip regions and dicing regions located between the chip regions. The chip regions are used to form integrated circuits, and the dicing regions are subsequently used as regions for dividing chips after chips are formed in the chip regions.

[0037] The chip region of wafer 201 can be doped with a certain number of impurity ions as needed. These impurity ions can be N-type or P-type. In some embodiments, a plurality of trench transistors can also be formed in the chip region of wafer 201. Each trench transistor includes an active region; at least one trench located within the active region, dividing the active region into a drain region and at least one source region (specifically, when there is one trench, the trench divides the active region into source and drain regions located on opposite sides of the trench; when there are two trenches, the two trenches are parallel to each other, and the two trenches divide the active region into a drain region located between the two trenches and two source regions located on the outer sides of the two trenches); and a gate structure or word line (WL) located within the trench. The drain region of the trench transistor is subsequently connected to the bit line, and the source region of the trench transistor is subsequently connected to a capacitor.

[0038] In some embodiments, a bottom dielectric layer (not shown) may also be formed on wafer 201. A plurality of lower electrode contact pads (not shown) may be formed in the bottom dielectric layer. The lower end of the lower electrode contact pad is connected to the corresponding source region. Specifically, the lower electrode contact pad can be connected to the corresponding source region through a metal plug located in the bottom dielectric layer. The upper end of the lower electrode contact pad is subsequently used to connect the lower electrode.

[0039] In some embodiments, the bottom dielectric layer can be a single layer or a multi-layer (greater than or equal to 2 layers) stacked structure, and the material of the dielectric layer can be silicon nitride, silicon oxynitride, silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), low dielectric constant material, other suitable materials and / or combinations thereof.

[0040] refer to Figure 4 The target layer is formed on the middle region 21 and the edge region 22 of the wafer 301.

[0041] In this embodiment, the target layer is a stacked structure 205 formed by alternating layers of sacrificial layer 203 and support layer 204, and a plurality of capacitor vias are subsequently formed in the stacked structure 205 as the target structure. In some other embodiments, the target layer can be a single layer or multiple layers of stacked dielectric layers, and vias or trenches are subsequently formed in the single layer or multiple layers of stacked dielectric layers as the target structure.

[0042] In some embodiments, the number of layers of the sacrificial layer 203 and the support layer 204 in the stacked structure 205 is multiple (greater than or equal to 2 layers). In this embodiment, the number of layers of the sacrificial layer 203 and the support layer 204 in the stacked structure 205 is two, including a first sacrificial layer on the wafer 201, a first support layer on the first sacrificial layer, a second sacrificial layer on the first support layer, and a second support layer on the second sacrificial layer. In some other embodiments, the number of layers of the sacrificial layer and the support layer in the stacked structure may both be one, including one sacrificial layer and one support layer on the sacrificial layer.

[0043] After the capacitor vias are formed, cavities can be formed by removing the remaining sacrificial layer. The sacrificial layer 203 and the support layer 204 are made of different materials. The sacrificial layer 203 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride, while the support layer 204 can also be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the support layer 204 is made of silicon nitride, and the sacrificial layer 203 is made of silicon oxide.

[0044] In some embodiments, the stacked structure 205 is formed on the surface of the underlying dielectric layer on the wafer 201.

[0045] refer to Figure 5 A mask material layer 207 is formed on the stacked structure 205.

[0046] The mask material layer 207 is subsequently used to form the mask layer 207. The mask material layer 207 is formed by a chemical vapor deposition process, which can be atmospheric or low-pressure chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), or high-density plasma chemical vapor deposition (HDPCVD).

[0047] After the mask material layer 207 is formed, a chemical mechanical polishing process is required to planarize the surface of the mask material layer 207 in order to form a mask layer of a predetermined thickness.

[0048] In some embodiments, the mask material layer 207 can be a single layer or a multi-layer stacked structure.

[0049] In some embodiments, the mask material layer 207 may be made of one or more of the following: polycrystalline silicon, amorphous silicon, amorphous carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide. In this embodiment, the mask material layer 207 is a single layer of polycrystalline silicon.

[0050] In some instances, an etch stop layer 206 is formed on the stacked structure 205 between the mask material layers 207. The etch stop layer 206 is used as a stop layer in subsequent patterning of the mask layers.

[0051] The etch stop layer 206 can be a single layer or a multi-layer stacked structure. The material of the etch stop layer 206 is different from the material of the mask material layer 207. In some embodiments, the material of the etch stop layer 206 can be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0052] refer to Figure 6 The mask material layer 207 (reference) was ground using a chemical mechanical polishing process. Figure 5 A mask layer 218 is formed, and during the grinding process, the grinding rate of the mask material layer on the edge region 22 is greater than the grinding rate of the mask material layer on the middle region 21, so that the thickness T1 of the formed mask layer 218 on the edge region 21 is less than the thickness T2 on the middle region 21.

[0053] The purpose of the thickness T1 of the formed mask layer 218 on the edge region 21 being less than that on the middle region 21 is to: subsequently pattern the mask layer 218 (etch the mask layer 218, forming several openings 210 in the mask layer 218) to form the mask pattern layer 208 (reference). Figure 11 After that, the mask pattern layer 208 (reference) is made. Figure 11The thickness T1 in the edge region 21 is less than the thickness in the middle region 21. The stacked structure 205 is etched using the mask pattern layer 208 as a mask, forming a plurality of capacitor holes 211 penetrating the thickness of the stacked structure 205 (see reference). Figure 12 When the plasma distributed on the edge region 22 is less than that distributed on the middle region 21, the mask pattern layer 218 on the edge region 22 has a smaller blocking effect on the plasma because its thickness is less than that on the middle region 21. Furthermore, the time it takes for the plasma to reach the surface of the stacked structure 205 on the edge region 22 is also reduced. This results in an increase in the amount of plasma reaching the surface of the stacked structure 205 on the edge region 22 per unit time. This ensures that during the etching process, the amount of plasma on the surface of the stacked structure 205 on the edge region 22 and the middle region is comparable, resulting in comparable etching rates for the stacked structure 205 on both regions. Upon completion of the etching process, the depth of the capacitor holes (or target structures) formed in the stacked structure 205 on both regions is comparable, thus preventing under-etching defects in the capacitor holes (or target structures) ultimately formed on the edge region 22. This prevents the problem of different etching depths in different areas of the wafer, thereby improving device performance. Furthermore, since there is no over-etching of the capacitor holes (or target structures) formed in the middle region, the size uniformity of the capacitor holes (or target structures) formed on the edge region 22 and the middle region is high. It should be noted that the aforementioned "comparable" means that the two are equal or have a small difference, or a difference within 10%.

[0054] In some embodiments, the thickness T1 of the mask layer 218 on the edge region 21 gradually decreases from near the middle region 21 to away from the middle region 21, and the corresponding subsequently formed mask pattern layer 208 (reference) Figure 11 The thickness T1 of the mask layer 218 on the edge region 22 gradually decreases from near the middle region 21 to away from the middle region 21. During the subsequent formation of the capacitor aperture (or target structure), this better prevents under-etching defects in the capacitor aperture (or target structure) ultimately formed on the edge region 22 and improves the dimensional uniformity of the capacitor aperture (or target structure) formed on the edge region 22 and the middle region. In some other embodiments, the thickness T1 of the mask layer 218 on the edge region 22 remains constant or changes only slightly from near the middle region 21 to away from the middle region 21.

[0055] In some embodiments, the thickness (average thickness) of the mask layer 218 on the edge region 22 is 0.5%-5% smaller than the thickness (average thickness) of the mask layer 218 on the middle region 21, and the corresponding subsequently formed mask pattern layer 208 (reference) Figure 11 The thickness (average thickness) of the mask layer 218 on the edge region 22 is also 0.5%-5% smaller than the thickness (average thickness) of the mask pattern layer 208 on the middle region 21. In a specific embodiment, the thickness (average thickness) of the mask layer 218 on the edge region 22 is 3nm-10nm smaller than the thickness (average thickness) of the mask layer 218 on the middle region 21. The corresponding subsequent mask pattern layer 208 (reference) Figure 11 The thickness (average thickness) of the mask pattern layer 208 on the middle region 21 is less than the thickness (average thickness) of the mask pattern layer 208 on the middle region 21. The thickness range is 3nm-10nm, so as to better prevent under-etching defects in the capacitor holes (or target structures) finally formed on the edge region 22 and to better improve the size uniformity of the capacitor holes (or target structures) formed on the edge region 22 and the middle region.

[0056] The mask material layer 207 is ground using a chemical mechanical polishing process in a grinding apparatus, as referenced. Figure 7 and Figure 8 During the grinding process, the wafer 201 is clamped by the grinding head 104, and the mask material layer on the wafer 201 is removed. Figure 7 and Figure 8 (Not shown) is attached to the polishing pad 102, and pressure is applied by the polishing head 104. During the polishing process, the polishing head 104 applies greater pressure to the edge region 22 of the wafer 201 than to the middle region 21 of the wafer 201. This results in a higher polishing rate for the mask material layer on the edge region 22 than for the mask material layer 21 on the middle region, leading to the final formed mask layer 218 (see reference). Figure 6 The thickness T1 in the edge region 21 is less than the thickness T2 in the middle region 21.

[0057] In some embodiments, the grinding apparatus may further include a chuck 105 for rotating the grinding head 104, a grinding fluid supply pipe 106 for supplying grinding fluid 107, and a grinding disc 101 for fixing the grinding pad 102 and rotating the grinding pad.

[0058] In some embodiments, the grinding head 104 applies 15%-35% greater pressure to the edge region 22 of the wafer 201 than to the middle region 21 of the wafer 201 during the grinding process.

[0059] In some embodiments, a comparison film 108 is provided on the lower surface of the polishing head 104. The comparison film 108 includes a plurality of concentric annular regions. Different pressures can be applied to different annular regions of the comparison film 108 by a driving device located in the polishing head 104, thereby allowing a greater pressure to be applied to the edge region 22 of the wafer 201.

[0060] In some embodiments, reference Figure 8 The comparison film 108 on the polishing head 104 includes seven concentric regions, specifically: region Z1, region Z2, region Z3, region Z4, region Z5, region Z6 and region Z7. During polishing, after the polishing head clamps the wafer 201, regions Z1, Z2 and Z3 correspond to the edge region 22 of the wafer 201, and regions Z4, Z5, Z6 and Z7 correspond to the middle region 21 of the wafer 201.

[0061] In some embodiments, when the material of the mask layer 218 is polycrystalline silicon, in order to form Figure 6 The thickness T1 of the mask layer on the edge region 22 shown is less than the thickness T2 of the mask layer 218 on the middle region 21, and the thickness T1 of the mask layer 218 on the edge region 21 gradually decreases from near the middle region 21 to far away from the middle region 21. The pressure applied to the comparison film 108 on the grinding head is as follows: Figure 9 As shown in the table, the pressure range applied to region Z1 is 1.9-2.1 Psi, the pressure range applied to region Z2 is 1.1-1.3 Psi, the pressure range applied to region Z3 is 1.3-1.5 Psi, and the pressure range applied to regions Z4, Z5, Z6 and Z7 is 1.4-1.6 Psi.

[0062] In some embodiments, before patterning the mask layer, a reference is made. Figure 10 A patterned photoresist layer 209 is formed on the mask layer 218, and the thickness of the photoresist layer 209 on the edge region 22 is less than the thickness of the photoresist layer 209 on the middle region 21.

[0063] A patterned photoresist layer 209 is formed through spin coating, exposure, and development processes.

[0064] refer to Figure 11 For mask layer 218 (reference) Figure 10 Patterning is performed to form a mask graphic layer 208.

[0065] In some embodiments, patterning includes: patterning a photoresist layer 209 (reference 209). Figure 10 The mask layer 218 is etched to form several openings 210 in the mask layer 218.

[0066] In some embodiments, when etching the mask layer 218, an etching stop layer 206 is used as a stop layer.

[0067] The etching mask layer 218 employs anisotropic dry etching processes, including anisotropic plasma etching processes.

[0068] After patterning the mask layer to form the mask pattern layer 208, the thickness T1 of the mask pattern layer 218 on the edge region 21 is less than the thickness T2 on the middle region 21.

[0069] refer to Figure 12 Using the mask graphic layer 218 as a mask, the target layer is etched to form the target structure in the target layer in the middle region 21 and the edge region 22.

[0070] In this embodiment, the target layer is a stacked structure 205, and the target structure is a plurality of capacitor holes 210 formed through the stacked structure 205. Specifically, using a mask pattern layer 218 as a mask, the stacked structure 205 on the middle region 21 and the edge region 22 is etched along the plurality of openings 210, forming a plurality of capacitor holes 210 through the stacked structure 205 on the middle region 21 and the edge region 22. In some other embodiments, when the target layer is a single-layer or multi-layer stacked dielectric layer, the target structure is a via or trench formed in the single-layer or multi-layer stacked dielectric layer.

[0071] The etched stack structure 205 employs anisotropic plasma etching. The plasma etching process is performed in a plasma etching apparatus, which dissociates the etching gas introduced into the etching chamber to form plasma, which is then used to etch the material to be etched. In some embodiments, the mask layer 218 is also etched simultaneously when the stack structure 205 is etched.

[0072] When forming the capacitor hole 211, the mask pattern layer 208 (reference) Figure 11 The thickness T1 in the edge region 21 is less than the thickness in the middle region 21. The stacked structure 205 is etched using the mask pattern layer 208 as a mask, forming a plurality of capacitor holes 211 penetrating the thickness of the stacked structure 205 (see reference). Figure 12Even if the amount of plasma distributed on the edge region 22 is less than the amount of plasma distributed on the middle region 21, the mask layer 218 on the edge region 22 has a smaller blocking effect on the plasma because its thickness is less than that on the middle region 21. Furthermore, the time it takes for the plasma to reach the surface of the stacked structure 205 on the edge region 22 is also reduced. This results in an increase in the amount of plasma reaching the surface of the stacked structure 205 on the edge region 22 per unit time, thus increasing the plasma density on the edge region 22 and the middle region 21 during etching. The amount of plasma on the surface of the stacked structure 205 in the middle region is comparable, and the etching rates of the stacked structure 205 in the edge region 22 and the middle region are comparable. Upon completion of the etching process, the depth of the capacitor holes formed in the stacked structure 205 in the edge region 22 and the middle region is comparable, thus preventing under-etching defects in the capacitor holes ultimately formed in the edge region 22. Subsequently, a lower electrode layer is formed on the sidewalls and bottom of the capacitor holes, and then the sacrificial layer is removed to form a cavity. This prevents detachment or peeling defects caused by the bottom of the lower electrode layer in the edge region being suspended. Furthermore, since there is no over-etching of the capacitor holes formed in the middle region, the size uniformity of the capacitor holes formed in the edge region 22 and the middle region is high. It should be noted that the aforementioned "comparable" means that the two are equal or have a small difference, or a difference within 10%.

[0073] In some embodiments, the bottom of a plurality of capacitor holes 211 exposes the surface of the corresponding lower electrode contact pad.

[0074] In some embodiments, after forming the capacitor hole 211, the method further includes: forming a lower electrode layer on the sidewall and bottom surface of the capacitor hole 211; removing the sacrificial layer between the lower electrode layers to form a cavity; forming a dielectric layer on the surface of the lower electrode and the inner wall surface of the cavity; and forming an upper electrode layer on the surface of the dielectric layer.

[0075] In some embodiments, when removing the sacrificial layer, a portion of the topmost support layer between the capacitor holes is first removed to form an opening that exposes the topmost sacrificial layer. All of the topmost sacrificial layer, as well as a portion of the support layer of other layers and all of the sacrificial layers of other layers at the bottom of the opening, are then removed along the opening.

[0076] In some embodiments, the lower electrode layer and the upper electrode layer can be a single-layer structure formed by one of the materials selected from W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked structure formed by two or more materials from the group consisting of the aforementioned materials. The dielectric layer is made of a high-k dielectric material (k greater than 2.8) to increase the capacitance value per unit area of ​​the capacitor. In a specific embodiment, the dielectric layer can be a single-layer structure formed by one of the materials selected from HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO, or a stacked structure formed by two or more materials from the group consisting of the aforementioned materials.

[0077] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A wafer is provided, the wafer including a central region and an edge region surrounding the central region; A target layer is formed on the middle and edge regions of the wafer; A mask material layer is formed on the target layer; The mask material layer is ground by a chemical mechanical polishing process to form a mask layer. In the chemical mechanical polishing process, the grinding rate of the mask material layer on the edge region is greater than the grinding rate of the mask material layer on the middle region, so that the thickness of the mask layer on the edge region is less than the thickness of the mask layer on the middle region. A patterned photoresist layer is formed on the mask layer, wherein the thickness of the patterned photoresist layer on the edge region is less than the thickness of the patterned photoresist layer on the middle region; Using the patterned photoresist layer as a mask, the mask layer is etched to form a mask pattern layer, wherein the thickness of the mask pattern layer on the edge region is less than the thickness of the mask pattern layer on the middle region; using the mask pattern layer as a mask, the target layer is etched to form a target structure in the target layer on the middle region and the edge region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The target layer comprises a stacked structure formed by alternating layers of sacrificial and support layers.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the grinding process, the wafer is held by a grinding head, and the mask material layer on the wafer is attached to the grinding pad. Pressure is applied by the grinding head, and the pressure applied by the grinding head to the edge area of ​​the wafer is greater than the pressure applied to the middle area of ​​the wafer, so that the grinding rate of the mask material layer on the edge area is greater than the grinding rate of the mask material layer on the middle area.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The grinding head applies 15%-35% greater pressure to the edge region of the wafer than to the center region of the wafer during the grinding process.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The edge region is a ring-shaped region located 5-10 mm from the edge of the wafer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the mask pattern layer on the edge region is 0.5%-5% less than the thickness of the mask pattern layer on the middle region.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the mask pattern layer on the edge region is less than the thickness of the mask pattern layer on the middle region in the range of 3nm-10nm.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The mask pattern layer is a single-layer or multi-layer stacked structure.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the mask pattern layer is one or more of polycrystalline silicon, amorphous silicon, amorphous carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

10. The method for forming a semiconductor structure as described in claim 1 or 8, characterized in that, The thickness of the mask pattern layer on the edge region gradually decreases from near the center region to far away from the center region.

11. The method for forming a semiconductor structure as described in claim 2, characterized in that, The target structure includes a plurality of capacitor holes formed between the stacked structures, and the forming method further includes: forming lower electrodes on the sidewalls and bottom surfaces of the capacitor holes, removing the sacrificial layer between the lower electrodes, and forming a cavity.

12. The forming method as described in claim 11, characterized in that, A bottom dielectric layer is formed on the middle and edge regions of the wafer, and a plurality of lower electrode contact pads are formed in the bottom dielectric layer on the middle and edge regions; the stacked structure is formed on the bottom dielectric layer, and the bottom of the plurality of capacitor holes exposes the corresponding lower electrode contact pads as described in claim 11, characterized in that it further includes: forming a dielectric layer on the surface of the lower electrode and the inner wall surface of the cavity; and forming an upper electrode layer on the surface of the dielectric layer.

13. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the support layer is different from that of the sacrificial layer.

14. The method for forming a semiconductor structure as described in claim 2, characterized in that, The number of layers for both the support layer and the sacrificial layer is at least one.

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