Semiconductor device and method of forming the same

Abstract

A semiconductor device and a forming method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a cell region and a cutoff ring region, and the cutoff ring region surrounding the cell region; forming a shield gate structure and a cutoff ring structure in the semiconductor substrate of the cutoff ring region; wherein the cutoff ring structure is electrically connected with the shield gate structure. The present application can improve the anti-breakdown capability on the basis of maintaining the size of the cutoff ring structure, and can also maintain similar anti-breakdown effect and improve the cutoff efficiency on the basis of reducing the size of the cutoff ring structure, thereby meeting the demand of reducing the size of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] Shielded gate trench (SGT, also known as split gate) field-effect transistor (MOS) devices are widely used in personal computers, mobile phones and other smart terminals because they have lower gate-drain capacitance Cgd, lower on-resistance and higher voltage withstand performance, which is more conducive to the flexible application of semiconductor integrated circuits compared with traditional MOS.

[0003] Specifically, in shielded-gate field-effect transistors (SFETs), by placing a shielding electrode below the gate electrode, the gate-drain capacitance can be significantly reduced, the device electric field optimized, and the breakdown voltage improved. Furthermore, the drift region of a shielded-gate SFET also exhibits a higher concentration of impurity carriers, which correspondingly reduces the on-resistance. Since shielded-gate SFETs need to withstand a certain voltage when used as power devices, their voltage withstand reliability becomes a crucial factor limiting their application.

[0004] In existing technologies, a stop-loop region can be set up, and a stop-loop structure can be placed within this region to improve the lateral breakdown resistance (also known as cutoff capability) of the device and prevent depletion of the depletion region. However, existing stop-loop structures occupy a large chip area, making it difficult to meet the requirements for miniaturizing device size. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor device and a method for forming the same, which can improve isolation, cutoff, and breakdown resistance while maintaining the size of the cutoff ring structure, and can also maintain similar isolation, cutoff, and breakdown resistance effects and improve cutoff efficiency while reducing the size of the cutoff ring structure, thereby reducing the area occupied by the cutoff ring structure and meeting the need to reduce device size.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a cell region and a cutoff ring region, wherein the cutoff ring region surrounds the cell region; forming a shielding gate structure and a cutoff ring structure within the semiconductor substrate in the cutoff ring region; wherein the cutoff ring structure is electrically connected to the shielding gate structure.

[0007] Optionally, the shielding gate structure is located inside the cutoff ring structure, or the shielding gate structure is located outside the cutoff ring structure and biased towards the outer side of the cutoff ring region; wherein, the outer side of the cutoff ring region is the side away from the cell region.

[0008] Optionally, the shielding grid structure is positioned inside the stop ring structure towards the outer side of the stop ring region.

[0009] Optionally, a shielding gate structure and a cutoff ring structure are formed within the semiconductor substrate of the cutoff ring region. The forming method includes: forming a shielding gate trench within the semiconductor substrate of the cutoff ring region; forming a first dielectric layer covering the bottom and sidewall surfaces of the shielding gate trench; filling the surface of the first dielectric layer within the shielding gate trench with a first conductive material; and forming the cutoff ring structure on one or both sides of the shielding gate trench.

[0010] Optionally, before forming the cutoff ring structure on one or both sides of the shielding gate trench, the method further includes: removing a portion of the first conductive material, removing a first dielectric layer surrounding the removed portion of the first conductive material, and removing a portion of the sidewall of the semiconductor substrate surrounding the removed portion of the first dielectric layer to obtain an enlarged trench, wherein the cross-sectional dimension of the enlarged trench is larger than the cross-sectional dimension of the shielding gate trench; forming a second dielectric layer in the enlarged trench, the second dielectric layer covering the sidewall surface of the enlarged trench and exposing at least a portion of the surface of the first conductive material, and the thickness of the second dielectric layer being greater than the thickness of the first dielectric layer; and filling the surface of the second dielectric layer in the enlarged trench with a second conductive material.

[0011] Optionally, the cutoff ring structure includes a source region and a body region, the source region covering at least a portion of the body region; the depth of the boundary line between the shielding trench and the enlarged trench is greater than the depth of the boundary line between the source region and the body region.

[0012] Optionally, the method for forming the semiconductor device further includes: forming a plurality of contact hole structures, wherein the contact hole structures are electrically connected to the cutoff ring structure and the shielding gate structure respectively; and forming a cutoff ring metal layer, wherein the cutoff ring metal layer covers the cutoff ring structure, the shielding gate structure and the contact hole structures.

[0013] Optionally, the semiconductor device further includes a voltage divider region surrounding the cell region, and a cutoff ring region surrounding the voltage divider region; the forming method further includes: reducing the number of shielding gate structures in the voltage divider region according to the number of shielding gate structures in the cutoff ring region.

[0014] Optionally, the sum of the number of shielding grid structures in the cutoff ring region and the number of shielding grid structures in the reduced voltage divider region is equal to the designed number of shielding grid structures in the voltage divider region.

[0015] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate including a cell region and a cutoff ring region, wherein the cutoff ring region surrounds the cell region; a shielding gate structure and a cutoff ring structure located within the semiconductor substrate of the cutoff ring region; wherein the cutoff ring structure is electrically connected to the shielding gate structure.

[0016] Optionally, the shielding gate structure is located inside the cutoff ring structure, or the shielding gate structure is located outside the cutoff ring structure and biased towards the outer side of the cutoff ring region; wherein, the outer side of the cutoff ring region is the side away from the cell region.

[0017] Optionally, the shielding grid structure is positioned inside the stop ring structure towards the outer side of the stop ring region.

[0018] Optionally, the shielding gate structure includes: a shielding gate trench located within the semiconductor substrate of the cutoff ring region; a first dielectric layer covering the bottom and sidewall surfaces of the shielding gate trench; and a first conductive material filling the surface of the first dielectric layer within the shielding gate trench; wherein the cutoff ring structure is located on one or both sides of the shielding gate trench.

[0019] Optionally, the shielding gate structure further includes: an enlarged trench, obtained by removing a portion of the first conductive material, removing a first dielectric layer surrounding the removed portion of the first conductive material, and removing a portion of the sidewalls of the semiconductor substrate surrounding the removed portion of the first dielectric layer, wherein the cross-sectional dimension of the enlarged trench is larger than the cross-sectional dimension of the shielding gate trench; a second dielectric layer, covering the sidewall surface of the enlarged trench and exposing at least a portion of the surface of the first conductive material, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer; and a second conductive material, filling the surface of the second dielectric layer within the enlarged trench.

[0020] Optionally, the cutoff ring structure includes a source region and a body region, the source region covering at least a portion of the body region; the depth of the boundary line between the shielding trench and the enlarged trench is greater than the depth of the boundary line between the source region and the body region.

[0021] Optionally, the semiconductor device further includes: a plurality of contact hole structures, the contact hole structures being electrically connected to the cutoff ring structure and the shielding gate structure respectively; and a cutoff ring metal layer, the cutoff ring metal layer covering the cutoff ring structure, the shielding gate structure and the contact hole structures.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0023] In this embodiment of the invention, by forming a shielding gate structure and a cutoff ring structure in the cutoff ring region, and electrically connecting the cutoff ring structure to the shielding gate structure, the shielding gate structure can be utilized to have smaller size and stronger breakdown resistance than the cutoff ring structure. This allows for improved isolation, cutoff, and breakdown resistance while maintaining the size of the cutoff ring structure. It also allows for maintaining similar isolation, cutoff, and breakdown effects and improving cutoff efficiency while reducing the size of the cutoff ring structure, thereby reducing the area occupied by the cutoff ring structure and meeting the need for smaller device size.

[0024] Furthermore, the shielding gate structure is located inside the cutoff ring structure, or the shielding gate structure is located outside the cutoff ring structure and biased towards the outer side of the cutoff ring region. Since the shielding gate structure in the cutoff ring region has better breakdown resistance than the cutoff ring structure, compared to setting the shielding gate structure biased towards the inner side of the device and then relying on the cutoff ring structure as the last line of defense against breakdown, the solution of this embodiment can set the shielding gate structure with better breakdown resistance as the last line of defense against breakdown, and better play the role of isolation, cutoff and breakdown resistance at the periphery of the device. While obtaining better isolation effect, the area occupied by the cutoff ring structure can also be further reduced.

[0025] Furthermore, after forming a shielding gate trench and a first dielectric layer in the semiconductor substrate of the cutoff ring region, a first conductive material can be filled on the surface of the first dielectric layer in the shielding gate trench to obtain a shielding gate structure, thereby obtaining a cutoff structure with better breakdown resistance than the cutoff ring structure under the same area.

[0026] Furthermore, after forming a shielding gate trench and a first dielectric layer within the semiconductor substrate of the cutoff ring region, the first conductive material, the first dielectric layer, and the sidewalls of the semiconductor substrate of a certain thickness can be removed to obtain an enlarged trench with a cross-sectional dimension larger than the shielding gate trench. A second dielectric layer with a thickness greater than the first dielectric layer is formed within this enlarged trench, and then filled with a second conductive material, so that the resulting shielding gate structure has a thicker second dielectric layer, further improving its breakdown resistance. Furthermore, since the cross-sectional dimension of the upper half of the original trench is pre-enlarged, the amount of second conductive material filled is not significantly reduced, and may even increase slightly, thus not affecting the conductivity within the shielding gate structure.

[0027] Furthermore, the depth of the boundary line between the shielding trench and the enlarged trench is greater than the depth of the boundary line between the source region and the body region. Since the boundary line between the source region and the body region is more prone to lateral junction breakdown than other locations, the solution of this embodiment of the invention can make the boundary line position correspond laterally to a thicker second dielectric layer, rather than a thinner first dielectric layer, which helps to further improve the anti-breakdown effect.

[0028] Furthermore, by reducing the number of shielding gate structures in the voltage divider region based on the number of shielding gate structures in the cutoff ring region, the number of shielding gate structures in the voltage divider region can be reduced by utilizing the shielding gate structures already set in the cutoff ring region, which helps to further reduce the device area. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device in the prior art;

[0030] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0031] Figures 3 to 9 This is a schematic diagram of the cross-sectional structure of a semiconductor device corresponding to each step in a method for forming a semiconductor device according to an embodiment of the present invention;

[0032] Figure 10 This is a top view of a semiconductor device according to an embodiment of the present invention;

[0033] Figure 11 This is a partial cross-sectional structural diagram of another semiconductor device in an embodiment of the present invention.

[0034] Figure label:

[0035] Semiconductor substrate 100; cell region shielding gate structure 11; voltage divider region shielding gate structure 12; first body region 131; first source region 132; semiconductor substrate 200; shielding gate trench 211; first dielectric layer 221; first conductive material 222; enlarged trench 231; second dielectric layer 241; second conductive material 242; body region 251; source region 252; cell region shielding gate structure 21; voltage divider region shielding gate structure 22; cell region body region 253; cell region source region 254; contact hole structure 260; metal layer 270; source region 352. Detailed Implementation

[0036] In the prior art, a cutoff ring region can be set in a shielded gate field-effect transistor device, and a cutoff ring structure can be set in this region to improve the device's lateral breakdown resistance.

[0037] Specifically, some charge needs to be introduced on the surface of the semiconductor substrate to reduce the curvature effect in areas other than the cell region (such as the edge of the terminal region), so that the electric field distribution is closer to the distribution of the ideal parallel planar junction, thereby improving the junction breakdown voltage.

[0038] Reference Figure 1 , Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device in the prior art.

[0039] As shown in the figure, the semiconductor device may include a semiconductor substrate 100, which includes a cell region, a voltage divider region, and a cutoff ring region.

[0040] A cell region shielding grid structure 11 can be provided in the cell region, a voltage divider region shielding grid structure 12 can be provided in the voltage divider region, and a cutoff ring structure can be provided in the cutoff ring region.

[0041] The cutoff ring structure can be formed by ion implantation into the first body region 131, and then ion implantation within the first body region 131 to form the first source region 132.

[0042] Research has revealed that in existing technologies, the cutoff ring structure is fabricated by implanting ions around the power device, resulting in a large chip area occupied by the cutoff ring structure.

[0043] Further research revealed that traditional semiconductor power devices can also employ other junction termination extension technologies such as field limiting rings and field plates. For example, when manufacturing medium and high voltage products, the spacing and number of field limiting rings or the area of ​​the field plate can be increased to meet the voltage withstand requirements.

[0044] However, regardless of the method used Figure 1 Whether using the cutoff ring structure shown or other junction termination extension technologies such as field limiting rings and field plates, all suffer from the problem of occupying a large chip area, making it difficult to meet the requirements for reducing device size, increasing the manufacturing cost of semiconductor power devices, and weakening their market competitiveness.

[0045] In this embodiment of the invention, by forming a shielding gate structure and a cutoff ring structure in the cutoff ring region, and electrically connecting the cutoff ring structure to the shielding gate structure, the shielding gate structure can be utilized to have smaller size and stronger breakdown resistance than the cutoff ring structure. This allows for improved isolation, cutoff, and breakdown resistance while maintaining the size of the cutoff ring structure. It also allows for maintaining similar isolation, cutoff, and breakdown effects and improving cutoff efficiency while reducing the size of the cutoff ring structure, thereby reducing the area occupied by the cutoff ring structure and meeting the need for smaller device size.

[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Reference Figure 2 , Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. The method for forming the semiconductor device may include steps S21 to S26:

[0048] Step S21: Provide a semiconductor substrate, the semiconductor substrate comprising a cell region and a stop ring region, wherein the stop ring region surrounds the cell region;

[0049] Step S22: A shielding gate structure and a cutoff ring structure are formed in the semiconductor substrate of the cutoff ring region, wherein the cutoff ring structure is electrically connected to the shielding gate structure.

[0050] The following is combined with Figures 3 to 11 The steps described above will be explained.

[0051] Figures 3 to 9 This is a schematic diagram of the cross-sectional structure of a semiconductor device in a method for forming a semiconductor device according to an embodiment of the present invention.

[0052] Reference Figure 3 A semiconductor substrate 200 is provided, which may include a cell region and a stop ring region, wherein the stop ring region surrounds the cell region, and a shielding gate trench 211 is formed in the semiconductor substrate 200 within the stop ring region.

[0053] The semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may include germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 200 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate with an epitaxy layer (Epi layer) grown on it.

[0054] Without limitation, a first type of epitaxial layer may be formed on the surface of the initial semiconductor substrate, for example, forming an N-type epitaxial layer as the semiconductor substrate 200; the semiconductor substrate 200 may also be formed by implanting a first type of ion into the initial semiconductor substrate, for example, implanting N-type ions to form an N-type lightly doped (N-) substrate.

[0055] Reference Figure 4 A first dielectric layer 221 is formed, which covers the bottom and sidewall surfaces of the shielding trench 211. The surface of the first dielectric layer 221 in the shielding trench 211 is filled with a first conductive material 222.

[0056] The material of the first dielectric layer 221 can be a dielectric material, such as a stack of oxides and nitrides, oxides, nitrides, or other suitable dielectric materials.

[0057] In a non-limiting manner, by employing a first oxidation process to oxidize the material of the semiconductor substrate 200 to form a first dielectric layer 221, the thickness of the first dielectric layer 221 can be effectively controlled, and better insulation quality can be obtained.

[0058] The first conductive material 222 can be a material with a dielectric constant less than a preset value, such as polysilicon or other suitable conductive materials.

[0059] It should be noted that, in one specific embodiment of the present invention, the following method may be used: Figure 4 The formed structure serves as a shielding grid structure for the cutoff ring region, and a cutoff ring structure is then formed on one or both sides of the formed shielding grid structure, thus allowing for the formation of the shielding grid structure using a less complex process.

[0060] In this embodiment of the invention, after forming a shielding gate trench 211 and a first dielectric layer 221 in the semiconductor substrate 200 of the cutoff ring region, a first conductive material 222 can be filled on the surface of the first dielectric layer 221 in the shielding gate trench 211 to obtain a shielding gate structure, thereby obtaining a cutoff structure with better breakdown resistance than the cutoff ring structure under the same area.

[0061] In another specific embodiment of the present invention, the following can be used: Figures 5 to 7 The formed structure serves as a shielding grid structure for the cutoff ring region, and a cutoff ring structure is formed on one or both sides of the formed shielding grid structure. This allows for the use of a shielding grid structure with better isolation performance, resulting in better anti-penetration effect.

[0062] Reference Figure 5 A portion of the first conductive material 222 is removed, a first dielectric layer 221 surrounding the removed portion of the first conductive material 222 is removed, and a portion of the sidewalls of the semiconductor substrate 200 surrounding the removed portion of the first dielectric layer 221 is removed to obtain an enlarged trench 231.

[0063] The cross-sectional dimension of the enlarged trench 231 can be larger than the cross-sectional dimension of the shielding gate trench 211. The extension direction of the cross-section is parallel to the surface of the semiconductor substrate 200.

[0064] Specifically, in Figure 5In the process shown, the first conductive material 222, the first dielectric layer 221, and the sidewalls of the semiconductor substrate 200 of a certain thickness can be removed to obtain an enlarged trench 231 with a cross-sectional size larger than the shielding gate trench 211, which is equivalent to enlarging the cross-sectional size of the upper half of the original trench.

[0065] Specifically, a dry etching method can be used to remove a portion of the first conductive material 222, the first dielectric layer 221, and the sidewalls of the semiconductor substrate 200 of a certain thickness from top to bottom.

[0066] In one specific embodiment of the present invention, a portion of the first conductive material 222 and the first dielectric layer 221 surrounding the removed portion of the first conductive material 222 can be removed firstly, and then a portion of the sidewall of the semiconductor substrate 200 surrounding the removed portion of the first dielectric layer 221 can be removed. Specifically, a first etching material can be used to etch a portion of the first conductive material 222; wherein the etching ratio of the first etching material for the first conductive material 222 and the first dielectric layer 221 is less than a first preset ratio, so that the first dielectric layer 221 surrounding the removed portion of the first conductive material 222 is removed along with the first conductive material 222.

[0067] In another specific embodiment of the present invention, a portion of the first conductive material 222 may be removed first, followed by the removal of the first dielectric layer 221 surrounding the removed portion of the first conductive material 222, and the removal of a portion of the sidewalls of the semiconductor substrate 200 surrounding the removed portion of the first dielectric layer 221. Specifically, after removing a portion of the first conductive material 222, a second etching material may be used to etch a portion of the first dielectric layer 221; wherein the etching ratio of the second etching material for the first dielectric layer 221 and the semiconductor substrate 200 is less than a second preset ratio, so that a portion of the sidewalls of the semiconductor substrate 200 surrounding the removed portion of the first dielectric layer 221 is removed along with the first dielectric layer 221.

[0068] It is understood that an etching material with a relatively small etching ratio (e.g., less than a third preset ratio) can also be used to simultaneously etch the first conductive material 222, the first dielectric layer 221, and the semiconductor substrate 200.

[0069] In this embodiment of the invention, an etching material with a small etching ratio is used, so that multiple material layers can be removed simultaneously, which can effectively improve process efficiency and reduce process complexity.

[0070] It should be noted that, when higher precision is required, etching materials with high etching ratios can also be used to remove the first conductive material 222, the first dielectric layer 221, and the semiconductor substrate 200, respectively.

[0071] Reference Figure 6 A second dielectric layer 241 is formed within the enlarged trench, the second dielectric layer 241 covering the sidewall surface of the enlarged trench 231 and exposing at least a portion of the surface of the first conductive material 222.

[0072] The thickness of the second dielectric layer 241 is greater than the thickness of the first dielectric layer 221, and the direction of the thickness is parallel to the surface of the semiconductor substrate 200.

[0073] Furthermore, the material of the second dielectric layer 241 can be the same as that of the first dielectric layer 221, and can be an oxide, such as silicon oxide.

[0074] In a non-limiting manner, by employing a second oxidation process to oxidize the material of the semiconductor substrate 200 to form a second dielectric layer 241, the thickness of the second dielectric layer 241 can be effectively controlled, and better insulation quality can be obtained.

[0075] Reference Figure 7 The surface of the second dielectric layer 241 within the enlarged trench 231 is filled with a second conductive material 242.

[0076] The second conductive material 242 can be a material with a dielectric constant less than a preset value, such as polycrystalline silicon or other suitable conductive materials.

[0077] In this embodiment of the invention, after forming a shielding gate trench 211 and a first dielectric layer 221 within the semiconductor substrate 200 of the cutoff ring region, the first conductive material 222, the first dielectric layer 221, and the sidewalls of the semiconductor substrate 200 of a certain thickness can be removed to obtain an enlarged trench 231 with a cross-sectional dimension larger than the shielding gate trench 211. A second dielectric layer 241 with a thickness greater than the first dielectric layer 221 is formed within this enlarged trench 231, and then filled with a second conductive material 242, so that the resulting shielding gate structure has a thicker second dielectric layer 241, further improving its breakdown resistance. Furthermore, since the cross-sectional dimension of the upper half of the original trench is pre-enlarged, the amount of the filled second conductive material 242 is not significantly reduced, and may even increase slightly, thus not affecting the conductivity within the shielding gate structure.

[0078] Reference Figure 8 A cutoff ring structure is formed in the cutoff ring region, comprising a source region 252 and a body region 251, wherein the source region 252 covers at least a portion of the body region 251.

[0079] The depth of the boundary line between the shielding trench 211 and the enlarged trench 231 is greater than the depth of the boundary line between the source region 252 and the body region 251.

[0080] The depth direction of the boundary line is perpendicular to the surface of the semiconductor substrate 200.

[0081] Specifically, the bottom of the source region 252 is higher than the boundary line between the shielding grid trench 211 and the enlarged trench 231.

[0082] In this embodiment of the invention, the depth of the boundary line between the shielding trench 211 and the enlarged trench 231 is greater than the depth of the boundary line between the source region 252 and the body region 251. Since the boundary line between the source region 252 and the body region 251 is more prone to lateral junction breakdown than other locations, the solution of this embodiment of the invention can make the boundary line position correspond laterally to the thicker second dielectric layer 241, rather than the thinner first dielectric layer 221, which helps to further improve the anti-breakdown effect.

[0083] Non-limiting, the body region 251 can be formed by performing a first type of ion implantation, for example, implanting P-type ions to form a P-type doped body region 251.

[0084] Without limitation, the source region 252 can be formed by performing a second type of ion implantation, for example, by implanting N-type ions to form an N-type doped source region 252.

[0085] It should be noted that other appropriate structures can also be used to form the cutoff ring structure, such as by increasing or decreasing the appropriate doping region.

[0086] Combined with reference Figure 9 and Figure 10 , Figure 10 This is a top view of a semiconductor device according to an embodiment of the present invention. Figure 9 for Figure 10 A cross-sectional view along the A1-A2 direction.

[0087] Specifically, the semiconductor device further includes a voltage dividing region surrounding the cell region, and a cutoff ring region surrounding the voltage dividing region.

[0088] Multiple contact hole structures 260 are formed, and the contact hole structures 260 are electrically connected to the cut-off ring structure and the shielding grid structure respectively, forming a cut-off ring metal layer 270, which covers the cut-off ring structure, the shielding grid structure and the contact hole structures 260.

[0089] Furthermore, the number of shielding grid structures in the voltage divider region can be reduced based on the number of shielding grid structures in the cutoff ring region.

[0090] In this embodiment of the invention, the number of shielding gate structures in the voltage divider region can be reduced according to the number of shielding gate structures in the cutoff ring region. This allows the use of the shielding gate structures already provided in the cutoff ring region to reduce the number of shielding gate structures in the voltage divider region, which helps to further reduce the device area.

[0091] Furthermore, the number of shielding grid structures in the cutoff ring region can be equal to the sum of the number of shielding grid structures in the reduced voltage divider region, which is equal to the designed number of shielding grid structures in the voltage divider region.

[0092] For example in Figure 1 In the semiconductor device shown, the number of shielding gate structures in the voltage divider region is two. That is, even without a shielding gate structure in the cutoff ring region, the design number of shielding gate structures in the voltage divider region is two. Figure 9 In the semiconductor device shown, since a shielding gate structure is provided in the cutoff ring region, the number of shielding gate structures in the voltage divider region can be reduced to one.

[0093] In this embodiment of the invention, the shielding gate structure already set in the cutoff ring region can be used to reduce the number of shielding gate structures in the voltage divider region, which helps to further reduce the device area.

[0094] It is understandable that although the cutoff loop region is represented by volume region 251 and source region 252, and the cell region by cell region volume region 253 and cell region source region 254, in practice, the same process can be used to form volume region 251 and cell region volume region 253 together, and the same process can also be used to form source region 252 and cell region source region 254 together, in order to reduce process costs and improve production efficiency. (Refer to the reference...) Figure 8 and Figure 11 , Figure 11 This is a partial cross-sectional structural diagram of another semiconductor device in an embodiment of the present invention, showing another shielding gate structure and cutoff ring structure of the cutoff ring region.

[0095] exist Figure 8 In the illustrated semiconductor device, the shielding gate structure may be located outside the cutoff ring structure and offset to the outer side of the cutoff ring region; wherein, the outer side of the cutoff ring region is the side away from the cell region. Specifically, the source region 252 is located on one side of the shielding gate structure.

[0096] It should be noted that, in this embodiment of the invention, the shielding grid structure can also be located inside the source region 252. By utilizing the fact that the shielding grid structure in the cutoff ring region has better anti-penetration capability than the cutoff ring structure, the area occupied by the cutoff ring structure can be reduced.

[0097] exist Figure 11In the semiconductor device shown, the shielding gate structure can be located inside the cutoff ring structure. Specifically, the source region 352 is located on both sides of the shielding gate structure.

[0098] Furthermore, the position of the shielding grid structure inside the stop ring structure can be biased towards the outside of the stop ring region.

[0099] In this embodiment of the invention, the shielding gate structure is located inside the cutoff ring structure, or the shielding gate structure is located outside the cutoff ring structure and biased towards the outer side of the cutoff ring region. Since the shielding gate structure in the cutoff ring region has better breakdown resistance than the cutoff ring structure, compared to setting the shielding gate structure biased towards the inner side of the device and then relying on the cutoff ring structure as the last line of defense against breakdown, the solution of this embodiment of the invention can set the shielding gate structure with better breakdown resistance as the last line of defense against breakdown, and better play the role of isolation, cutoff and breakdown resistance at the periphery of the device. While obtaining better isolation effect, it can also further reduce the area occupied by the cutoff ring structure.

[0100] In this embodiment of the invention, by forming a shielding gate structure and a cutoff ring structure in the cutoff ring region, and electrically connecting the cutoff ring structure to the shielding gate structure, the shielding gate structure can be utilized to have smaller size and stronger breakdown resistance than the cutoff ring structure. This allows for improved isolation, cutoff, and breakdown resistance while maintaining the size of the cutoff ring structure. It also allows for maintaining similar isolation, cutoff, and breakdown effects and improving cutoff efficiency while reducing the size of the cutoff ring structure, thereby reducing the area occupied by the cutoff ring structure and meeting the need for smaller device size.

[0101] Furthermore, the sum of the cross-sectional width of the cutoff ring structure and the cross-sectional width of the shielding grid structure can be less than the designed cross-sectional width of the cutoff ring structure. It is understood that the designed cross-sectional width of the cutoff ring structure can be the design width without the shielding grid structure, thereby ensuring a reduction in the area occupied by the cutoff ring structure and improving cutoff efficiency and performance stability.

[0102] The direction of cross-section expansion is parallel to the surface of semiconductor substrate 200.

[0103] It should be particularly pointed out that, in Figure 1 , Figure 9 In the semiconductor devices shown, the shielding gate structure of the cell region is not limited to the structure shown in the figure. The embodiments of this application may not limit the specific cell region device structure.

[0104] In a non-limiting embodiment, the shielding gate structure of the cell region may include: a semiconductor substrate; a shielding gate trench located in the semiconductor substrate; a field oxide dielectric layer and a first electrode encapsulated within the field oxide dielectric layer, located at the bottom and lower sidewall surfaces of the shielding gate trench; a gate oxide dielectric layer located on the surface of a portion of the upper sidewall of the shielding gate trench; and a second electrode located on the surface of the field oxide dielectric layer within the shielding gate trench.

[0105] In this embodiment of the invention, a semiconductor device is also disclosed, with reference to... Figure 9 It may include: a semiconductor substrate 200, the semiconductor substrate 200 comprising a cell region and a cutoff ring region, wherein the cutoff ring region surrounds the cell region; a shielding gate structure and a cutoff ring structure, located within the semiconductor substrate 200 of the cutoff ring region; wherein the cutoff ring structure is electrically connected to the shielding gate structure.

[0106] Furthermore, the shielding gate structure is located inside the stop ring structure, or the shielding gate structure is located outside the stop ring structure and biased towards the outer side of the stop ring region; wherein, the outer side of the stop ring region is the side away from the cell region.

[0107] Furthermore, the shielding grid structure is positioned inside the stop ring structure towards the outer side of the stop ring region.

[0108] Further, the shielding gate structure includes: a shielding gate trench 211 located within the semiconductor substrate 200 of the cutoff ring region; a first dielectric layer 221 covering the bottom and sidewall surfaces of the shielding gate trench 211; and a first conductive material 222 filling the surface of the first dielectric layer 221 within the shielding gate trench 211; wherein the cutoff ring structure is located on one or both sides of the shielding gate trench 211.

[0109] Furthermore, the shielding gate structure further includes: an enlarged trench 231, obtained by removing a portion of the first conductive material 222, removing the first dielectric layer 221 surrounding the removed portion of the first conductive material 222, and removing a portion of the sidewall of the semiconductor substrate 200 surrounding the removed portion of the first dielectric layer 221, wherein the cross-sectional dimension of the enlarged trench 231 is larger than the cross-sectional dimension of the shielding gate trench 211; a second dielectric layer 241, covering the sidewall surface of the enlarged trench 231 and exposing at least a portion of the surface of the first conductive material 222, and the thickness of the second dielectric layer 241 is greater than the thickness of the first dielectric layer 221; and a second conductive material 242, filling the surface of the second dielectric layer 241 within the enlarged trench 231.

[0110] Furthermore, the cutoff ring structure includes a source region 252 and a body region 251, wherein the source region 252 covers at least a portion of the body region 251; the depth of the boundary line between the shielding trench 211 and the enlarged trench 231 is greater than the depth of the boundary line between the source region 252 and the body region 251.

[0111] Furthermore, the semiconductor device further includes: a plurality of contact hole structures 260, the contact hole structures 260 being electrically connected to the cutoff ring structure and the shielding gate structure respectively; and a metal layer 270, the cutoff ring metal layer 270 covering the cutoff ring structure, the shielding gate structure and the contact hole structures 260.

[0112] For the principles, specific implementation, and beneficial effects of this semiconductor device, please refer to the previous description of the semiconductor device formation method; it will not be repeated here.

[0113] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0114] In the embodiments of this application, "multiple" refers to two or more.

[0115] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0116] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate comprising a cell region and a stop ring region, wherein the stop ring region surrounds the cell region; A shielding gate structure and a cutoff ring structure are formed within the semiconductor substrate of the cutoff ring region; The cutoff ring structure is electrically connected to the shielding grid structure. Wherein, a shielding gate structure and a stop ring structure are formed within the semiconductor substrate of the stop ring region, including: A shielding gate trench is formed within the semiconductor substrate of the cutoff ring region; A first dielectric layer is formed, which covers the bottom and sidewall surfaces of the shielding trench; The surface of the first dielectric layer within the shielding trench is filled with a first conductive material; The cut-off ring structure is formed on one or both sides of the shielding grid trench; The method further includes, before forming the stop-loop structure on one or both sides of the shielding trench, the method prior to: A portion of the first conductive material is removed, a first dielectric layer surrounding the removed portion of the first conductive material is removed, and a portion of the sidewalls of the semiconductor substrate surrounding the removed portion of the first dielectric layer are removed to obtain an enlarged trench, wherein the cross-sectional dimension of the enlarged trench is larger than the cross-sectional dimension of the shielding gate trench. A second dielectric layer is formed within the enlarged trench, the second dielectric layer covering the sidewall surface of the enlarged trench and exposing at least a portion of the surface of the first conductive material, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer; A second conductive material is filled on the surface of the second dielectric layer within the enlarged trench.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The shielding grid structure is located inside the stop ring structure, or the shielding grid structure is located outside the stop ring structure and biased towards the outer side of the stop ring region; The outer side of the cutoff ring region is the side away from the cell region.

3. The method for forming a semiconductor device according to claim 2, characterized in that, The shielding grid structure is positioned inside the stop ring structure, offset from the outside of the stop ring region.

4. The method for forming a semiconductor device according to claim 1, characterized in that, The cutoff ring structure includes a source region and a body region, wherein the source region covers at least a portion of the body region; The depth of the boundary line between the shielding grid trench and the enlarged trench is greater than the depth of the boundary line between the source region and the body region.

5. The method for forming a semiconductor device according to claim 1, characterized in that, Also includes: Multiple contact hole structures are formed, and the contact hole structures are electrically connected to the cut-off ring structure and the shielding gate structure, respectively. A stop ring metal layer is formed, which covers the stop ring structure, the shielding gate structure, and the contact hole structure.

6. The method for forming a semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a voltage dividing region surrounding the cell region, and a cutoff ring region surrounding the voltage dividing region; The forming method further includes: The number of shielding grid structures in the voltage divider region is reduced based on the number of shielding grid structures in the cutoff ring region.

7. The method for forming a semiconductor device according to claim 6, characterized in that, The sum of the number of shielding grid structures in the cutoff ring region and the number of shielding grid structures in the reduced voltage divider region is equal to the designed number of shielding grid structures in the voltage divider region.

8. A semiconductor device, characterized in that, include: A semiconductor substrate comprising a cell region and a stop-loop region, wherein the stop-loop region surrounds the cell region; The shielding gate structure and the cutoff ring structure are located within the semiconductor substrate of the cutoff ring region; The cutoff ring structure is electrically connected to the shielding grid structure. The shielding grid structure includes: The shielding gate trench is located within the semiconductor substrate of the cutoff ring region; A first dielectric layer covers the bottom and sidewall surfaces of the shielding trench; A first conductive material is filled on the surface of the first dielectric layer within the shielding trench; The cut-off ring structure is located on one or both sides of the shielding grid trench; The shielding grid structure also includes: An enlarged trench is obtained by removing a portion of the first conductive material, removing a first dielectric layer surrounding the removed portion of the first conductive material, and removing a portion of the sidewalls of the semiconductor substrate surrounding the removed portion of the first dielectric layer, wherein the cross-sectional dimension of the enlarged trench is larger than the cross-sectional dimension of the shielding gate trench. A second dielectric layer covers the sidewall surface of the enlarged trench and exposes at least a portion of the surface of the first conductive material, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer. A second conductive material is filled on the surface of the second dielectric layer within the enlarged trench.

9. The semiconductor device according to claim 8, characterized in that, The shielding grid structure is located inside the stop ring structure, or the shielding grid structure is located outside the stop ring structure and biased towards the outer side of the stop ring region; The outer side of the cutoff ring region is the side away from the cell region.

10. The semiconductor device according to claim 9, characterized in that, The shielding grid structure is positioned inside the stop ring structure, offset from the outside of the stop ring region.

11. The semiconductor device according to claim 8, characterized in that, The cutoff ring structure includes a source region and a body region, wherein the source region covers at least a portion of the body region; The depth of the boundary line between the shielding grid trench and the enlarged trench is greater than the depth of the boundary line between the source region and the body region.

12. The semiconductor device according to claim 8, characterized in that, Also includes: Multiple contact hole structures are provided, wherein the contact hole structures are electrically connected to the cut-off ring structure and the shielding grid structure, respectively. A stop ring metal layer, which covers the stop ring structure, the shielding grid structure, and the contact hole structure.

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