Semiconductor structure and method of manufacturing the same
By forming an annular sacrificial barrier layer and an interconnecting hole structure with inclined sidewalls within the substrate, the problems of pre-sealing and voids during metal filling of high aspect ratio holes are solved, thus realizing a hole-free conductive structure.
CN116469831BActive Publication Date: 2026-07-03CHANGXIN MEMORY TECH INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-12
- Publication Date
- 2026-07-03
AI Technical Summary
Technical Problem
When filling high aspect ratio holes with metal, the small angle at the edge of the hole leads to a fast metal deposition rate, causing the hole to close prematurely and resulting in voids.
Method used
An annular sacrificial barrier layer is formed within the substrate, and an etched hole is formed on its inner side, making the upper width of the interconnect hole greater than the lower width, with inclined sidewalls, and the conductive structure fills the interconnect hole.
Benefits of technology
This avoids the conductive layer being sealed prematurely in subsequent processes, forming a pore-free conductive structure, thus improving the success rate of metal filling and the integrity of the structure.
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Smart Images
Figure CN116469831B_ABST
Abstract
This invention relates to a semiconductor structure and its fabrication method. The fabrication method includes providing a substrate; forming an annular sacrificial barrier layer within the substrate; forming an etched via within the substrate, the etched via being located inside the annular sacrificial barrier layer; and removing the annular sacrificial barrier layer to obtain interconnect vias, wherein the upper width of the interconnect via is greater than the lower width of the interconnect via. The semiconductor structure fabrication method provided by this invention sets the upper width of the interconnect via to be greater than the lower width. Such interconnect vias can avoid premature sealing during subsequent conductive layer filling processes, thereby obtaining a hole-free conductive structure.
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