An amplifier layout structure and an amplifier

Abstract

This invention discloses an amplifier layout structure and an amplifier. The amplifier layout structure includes an amplifier array composed of N transistors. The amplifier array is distributed in a semi-enclosed structure, including a first transistor layout area, a third transistor layout area, and a second transistor layout area arranged sequentially, and the first transistor layout area and the second transistor layout area are symmetrically arranged; wherein N is greater than or equal to 3. This invention optimizes the existing linear structure of amplifier layouts into a semi-enclosed structure, which can reduce the adverse effects of thermal effects on the amplifier circuit and improve the DC and RF performance of the amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated chip layout design technology, and in particular to an amplifier layout structure and an amplifier. Background Technology

[0002] With the development of communication technology, communication system terminals need to overcome transmission losses and interference, thus increasing the power requirements for output. High-power amplifiers also have higher requirements for system stability, one key method being to enhance their thermal stability. This prevents excessive thermal effects generated during system operation from affecting the amplifier's performance indicators.

[0003] There are many layout structures for traditional amplifier circuits, the most common being... Figure 1 The "one-line" structure shown. For example... Figure 2 The diagram shows an example layout of an existing "line" structure (using 12 HBT transistors as an example). The advantages of this existing example layout include: (a) a compact and orderly arrangement that is easy to lay out; and (b) symmetrical input and output nodes to the individual transistor ports, preventing the introduction of additional phase errors. However, the compact arrangement of the existing example layout leads to more concentrated amplifier heat generation, and excessively high junction temperatures degrade the high-frequency performance of the transistors. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and propose an amplifier layout structure and amplifier, which optimizes the existing linear structure of the amplifier layout into a semi-enclosed structure, thereby reducing the adverse effects of thermal effects on the amplifier circuit and improving the DC and RF performance of the amplifier.

[0005] The technical solution adopted by this invention to solve its technical problem is:

[0006] On one hand, an amplifier layout structure includes an amplifier array composed of N transistors; the amplifier array is distributed in a semi-enclosed structure, including a first transistor layout area, a third transistor layout area and a second transistor layout area arranged sequentially, and the first transistor layout area and the second transistor layout area are symmetrically arranged; wherein, N is greater than or equal to 3.

[0007] Preferably, the signal input terminals of each transistor in the first transistor layout area, each transistor in the second transistor layout area, and each transistor in the third transistor layout area all face the inside of the layout structure, and the signal output terminals all face the outside of the layout structure.

[0008] Preferably, the number of transistors disposed in the first transistor layout area and the second transistor layout area is equal.

[0009] Preferably, when N is a multiple of 3, the number of crystals in the first transistor layout area, the second transistor layout area, and the third transistor layout area are equal.

[0010] Preferably, the amplifier layout structure further includes: an input interconnection layout area disposed within the semi-enclosed structure, wherein the input interconnection layout area is located in the third conductive layer and is used to interconnect the signal input terminals of all transistors in the amplifier array.

[0011] Preferably, the amplifier layout structure further includes: an output interconnection layout area disposed outside the semi-enclosed structure, the output interconnection layout area including a superimposed area of ​​a first conductive layer, a second conductive layer and a third conductive layer, used to interconnect the signal output terminals of all transistors in the amplifier array; the first conductive layer, the second conductive layer and the third conductive layer are arranged sequentially from bottom to top and are insulated from each other.

[0012] Preferably, the amplifier layout structure further includes: a bias circuit layout area disposed within the semi-enclosed structure; the bias circuit layout area is located below the third conductive layer and is insulated from the third conductive layer.

[0013] Preferably, the amplifier layout structure further includes: a first pad layout area and a second pad layout area; the first pad layout area is located between the first transistor layout area and the third transistor layout area, and is used to connect the first excitation port of the bias circuit; the second pad layout area is located between the second transistor layout area and the third transistor layout area, and is used to connect the second excitation port of the bias circuit.

[0014] Preferably, the transistor is a heterojunction bipolar transistor.

[0015] On the other hand, there is an amplifier arranged according to the amplifier layout structure.

[0016] The present invention has the following beneficial effects:

[0017] (1) The present invention optimizes the existing amplifier layout into a semi-enclosed structure, and the two groups of transistors (the first transistor layout area and the second transistor layout area) are symmetrical in the layout structure. This structure allows the signal to remain phase symmetrical before and after being amplified by each part of the transistors, thus ensuring the stability of signal transmission.

[0018] (2) The input interconnection layout area of ​​the present invention is located in the third conductive layer, thereby reserving space for the vertical structure of the bias portion, and maintaining the electrical and reliability levels unchanged.

[0019] (3) The output interconnection layout area of ​​the present invention is configured as a superposition of a first conductive layer, a second conductive layer and a third conductive layer. The superposition of the three conductive layers can effectively reduce parasitic inductance and parasitic resistance, and reduce the loss of transistors in the first transistor layout area and the second transistor layout area to the output end after the layout structure changes.

[0020] (4) The bias circuit layout area of ​​the present invention is located below the third conductive layer, so the signal input terminal (third conductive layer) and the bias circuit will not affect each other, and a portion of the bias circuit area can be saved.

[0021] (5) The first pad layout area of ​​the present invention is located in the area between the first transistor layout area and the third transistor layout area, and the second pad layout area is located in the area between the second transistor layout area and the third transistor layout area, thereby further saving layout space.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments, but the amplifier layout structure and amplifier of the present invention are not limited to the embodiments. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an amplifier circuit structure in the prior art;

[0024] Figure 2 This is a layout diagram of an amplifier structure in the prior art;

[0025] Figure 3 This is a schematic diagram of the optimized amplifier circuit structure according to an embodiment of the present invention;

[0026] Figure 4 This is a circuit diagram of the optimized amplifier structure according to an embodiment of the present invention;

[0027] Figure 5 This is an optimized amplifier structure layout according to an embodiment of the present invention;

[0028] Figure 6 This is an optimized layout structure scheme for the main body of an embodiment of the present invention; wherein, (a) represents the layout structure of the main body in the prior art, and (b) represents the layout structure of the main body in this embodiment;

[0029] Figure 7 This is a schematic diagram of the metal interconnection between the input and output terminals in an embodiment of the present invention;

[0030] Figure 8 This is an optimized layout structure scheme for the offset portion according to an embodiment of the present invention; wherein, (a) represents the layout structure of the offset portion in the prior art, and (b) represents the layout structure of the offset portion in this embodiment;

[0031] Figure 9The DC characteristic curve of the amplifier structure layout in the prior art of this invention;

[0032] Figure 10 The DC characteristic curve of the amplifier structure layout in an embodiment of the present invention;

[0033] Figure 11 This is a comparison chart of the DC characteristic curves of the layout in this embodiment and the layout in the prior art;

[0034] Figure 12 This is a schematic diagram of a single-tone power scanning test system;

[0035] Figure 13 This is a comparison chart of the results of the single-tone large signal test item 1 between the layout of this embodiment and the layout of the prior art;

[0036] Figure 14 This is a comparison chart of the results of single-tone large signal test item two between the layout of this embodiment and the layout of the prior art;

[0037] Figure 15 This is a comparison chart of the results of single-tone large signal test item three between the layout of this embodiment and the layout of the prior art;

[0038] Figure 16 This is a comparison chart of the results of single-tone large signal test item four between the layout of this embodiment and the layout of the prior art. Detailed Implementation

[0039] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0040] In the description of this invention, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0043] See Figures 3-5 As shown in the figure, this embodiment of an amplifier layout structure includes an amplifier array composed of N transistors, the amplifier array being distributed in a semi-enclosed structure; wherein, N is greater than or equal to 3.

[0044] In this embodiment, a heterojunction bipolar transistor is used as an example for explanation, namely... Figure 3 The HBT shown is an example, but the application of this invention is not limited to HBT tubes. From Figure 3 As can be seen, the amplifier circuit structure of this embodiment includes: signal input terminal 11, signal output terminal 12, PA array 13 composed of N HBT transistors, bias circuit 14, first excitation port 15 and second excitation port 16.

[0045] Specifically, the signal input terminal 11 and signal output terminal 12 can be connected to the outside in the following ways:

[0046] 1) Set up port pads and perform on-wafer testing via GSG-type RF probes;

[0047] 2) Connect to the input matching circuit or output matching circuit via metal traces;

[0048] 3) Set up port pads and connect them to the pads of other chips via wire bonding, thereby connecting them to other chips.

[0049] See Figure 4 The diagram shown is a circuit diagram corresponding to the optimized amplifier structure of this embodiment. As can be seen from the diagram, in this embodiment, the ballast resistor connected to the base of each HBT transistor is connected to the bias circuit 14, the series capacitor at the base of each HBT transistor is connected to the signal input terminal 11, and the collector of each HBT transistor is connected to the signal output terminal 12. The first excitation port 15 and the second excitation port 16 are respectively connected to the bias circuit 14.

[0050] See Figure 5The diagram shown illustrates the optimized amplifier layout according to an embodiment of the present invention, specifically including: a first transistor layout area 21, a second transistor layout area 22, a third transistor layout area 23, an input interconnect layout area 24, an output interconnect layout area 25, a bias circuit layout area 26, a first pad layout area 27, and a second pad layout area 28. The optimized layout of this embodiment employs a three-layer conductive layer layout, specifically a metal layer.

[0051] See Figure 6 As shown, this is an optimized layout structure scheme for the main body of an embodiment of the present invention; wherein, (a) represents the layout structure of the main body in the prior art, and (b) represents the layout structure of the main body in this embodiment.

[0052] Specifically, from Figure 6 (a) It can be seen that the transistors in the prior art are arranged in a “line” structure, including a first region 211, a second region 221 and a third region 223, as well as a signal input terminal region 241 and a signal output terminal region 251.

[0053] from Figure 6 (b) It can be seen that the semi-enclosed structure described in this embodiment includes a first transistor layout area 21, a third transistor layout area 23 and a second transistor layout area 22 arranged sequentially; the signal input terminals of each transistor in the first transistor layout area 21, each transistor in the second transistor layout area 22 and each transistor in the third transistor layout area 23 are all facing the inside of the layout structure, and the signal output terminals are all facing the outside of the layout structure.

[0054] In this embodiment, the number of transistors in the first transistor layout area 21 and the second transistor layout area 22 is equal.

[0055] Specifically, when N is a multiple of 3, the number of transistors in the first transistor layout area 21, the second transistor layout area 22, and the third transistor layout area 23 are equal.

[0056] It should be noted that in this embodiment, the first transistor layout area 21 is located in the left area, the second transistor layout area 22 is located in the right area, and the third transistor layout area 23 is located in the bottom area. In actual applications, the position of each transistor layout area can be adjusted according to the layout requirements or different viewing angles. This embodiment does not impose specific restrictions.

[0057] In specific optimization, all existing HBTs arranged in a "line" are divided into three groups. If the total number of HBTs is N, then the number of HBTs in each group is N / 3. If the total number of HBTs is not a multiple of 3, the number of transistors in the first transistor layout area 21 and the second transistor layout area 22 can be kept the same, while adjusting the number of transistors in the third transistor layout area 23 to still satisfy the semi-enclosed structural distribution. Figure 6 (a) The HBT tube in the first region 211 is rotated 90° clockwise to obtain Figure 6 (b) The HBTs in the first transistor layout area 21 are rotated so that the signal input terminals 11 of each HBT face inwards and the signal output terminals 12 face outwards; Figure 6 (a) The HBT tube in the second region 221 is rotated 90° counterclockwise to obtain Figure 6 (b) The HBTs in the second transistor layout area 22 are rotated so that the signal input terminals 11 of each HBT face inwards and the signal output terminals 12 face outwards. After rotation, the HBTs in the first transistor layout area 21 and the HBTs in the second transistor layout area 22 must maintain left-right symmetry in the layout structure. This structure allows the signal to maintain phase symmetry before and after amplification by each HBT, ensuring the stability of signal transmission.

[0058] See Figure 6 As shown, the main part of the amplifier layout structure further includes: an input terminal interconnection layout area 24 disposed within the semi-enclosed structure. The input terminal interconnection layout area 24 is located in the third conductive layer and is used to interconnect the signal input terminals 11 of all transistors in the amplifier array.

[0059] Correspondingly, the main body of the amplifier layout structure further includes an output interconnection layout area 25 disposed outside the semi-enclosed structure. The output interconnection layout area 25 includes a superimposed area of ​​a first conductive layer, a second conductive layer, and a third conductive layer, used to interconnect the signal output terminals 12 of all transistors in the amplifier array. The first conductive layer, the second conductive layer, and the third conductive layer are arranged sequentially from bottom to top and are insulated from each other. In this embodiment, the output interconnection layout area 25 is configured as a semi-enclosed structure, surrounding the first transistor layout area 21, the third transistor layout area 23, and the second transistor layout area 22.

[0060] In this embodiment, the first conductive layer is a first metal layer, the second conductive layer is a second metal layer, and the third conductive layer is a third metal layer. The first, second, and third metal layers are stacked sequentially, with the first metal layer at the bottom. Silicon nitride and polyimide are typically used as separators between the first, second, and third metal layers. In specific connections... Figure 4The upper plate of the base capacitor of the HBT transistor shown is interconnected through the second metal layer (the upper plate of the base capacitor is set in the second metal layer, and the lower plate is set in the first metal layer). The traces are led out from the second metal layer and the vias from the first metal layer to the third metal layer are directly connected to the third metal layer.

[0061] Specifically, the existing input interconnection layout area 24 structure uses a first metal layer M1 (1μm thick) or a second metal layer M2 (2μm thick) to interconnect all HBT transistor signal input terminals 11. In this embodiment, the input interconnection layout area 24 structure is changed to use a third metal layer M3 (2μm thick). This structure optimization reserves space for the vertical structure in the bias portion, and since both M2 and M3 are 2μm thick, the electrical performance and reliability level can be maintained without change.

[0062] The existing output interconnection layout area 25 structure uses a first metal layer M1, a second metal layer M2, or a combination of both to interconnect all HBT transistor signal output terminals 12. In this embodiment, the output interconnection layout area 25 structure is changed to a three-layer metal layer M1+M2+M3. This three-layer metal layer stacking effectively reduces parasitic inductance and resistance, and reduces the losses from the HBT transistors in the first transistor layout area 21 and the second transistor layout area 22 to the output terminal after the layout structure change. See the schematic diagram of the input / output interconnection metal in this embodiment. Figure 7 As shown.

[0063] See Figure 8 As shown, this is an optimized layout structure scheme for the offset portion according to an embodiment of the present invention; wherein, (a) represents the layout structure of the offset portion in the prior art, and (b) represents the layout structure of the offset portion in this embodiment.

[0064] Specifically, from Figure 8 (a) It can be seen that the bias region 261, the first pad region 271 and the second pad region 281 of the prior art are located in the right region of the entire layout structure.

[0065] from Figure 8 (b) It can be seen that, in this embodiment, the structure of the amplifier layout bias portion includes a bias circuit layout area 26 disposed within a semi-enclosed structure; the bias circuit layout area 26 is located below the third conductive layer and is insulated from the third conductive layer.

[0066] Furthermore, the structure of the amplifier layout bias portion further includes: a first pad layout area 27 and a second pad layout area 28; the first pad layout area 27 is disposed in the region between the first transistor layout area 21 and the third transistor layout area 23, and is used to connect the first excitation port 15 of the bias circuit 14; the second pad layout area 28 is disposed in the region between the second transistor layout area 22 and the third transistor layout area 23, and is used to connect the second excitation port 16 of the bias circuit 14. In this embodiment, the first pad layout area 27 is disposed between the region surrounded by the first transistor layout area 21, the third transistor layout area 23 and the output interconnect layout area 25, and correspondingly, the second pad layout area 28 is disposed between the region surrounded by the second transistor layout area 22, the third transistor layout area 23 and the output interconnect layout area 25.

[0067] In this embodiment, the bias circuit 14 in the bias circuit layout area 26 is an emitter follower, composed of a capacitor, three HBT transistors, several thin-film resistors, and other components. In the optimized structure, it is placed under the third metal layer M3 used to interconnect the signal input terminals 11 of each HBT transistor. Because the components used in the bias circuit 14 are all located under the third metal layer M3 in the vertical structure, the signal input terminals 11 and the bias circuit 14 will not interfere with each other, and a portion of the area of ​​the bias circuit 14 can be saved. The PADs (V1, V2) at the first pad layout area 27 and the second pad layout area 28 are used to connect the two external excitation ports of the bias circuit 14 (the first excitation port 15 and the second excitation port 16, specifically the voltage / current excitation provided by other chips / devices). After the structural change, their positions are placed in the area between the three sets of HBT transistors to further save space in the entire layout area.

[0068] It should be noted that, in addition to the emitter follower, the bias circuit 14 can also be a current mirror or an optimized structure of both emitter follower and current mirror circuits. This embodiment does not impose any specific restrictions.

[0069] The DC characteristics of the original structure of the HBT amplifier with an area of ​​3600μm2 and the amplifier with the optimized structure in this embodiment will be tested under the same conditions.

[0070] See Figure 9 The diagram shows the DC characteristic curves of a traditional HBT amplifier layout. Taking the collector current Icc under the collector voltage Vcc shown in m1, m2, and m3 as an example, Trace0 to 7 represent the DC characteristic curves of the amplifier under eight different bias voltages:

[0071] When Vcc = 3.4V, the measured Icc values ​​were 38mA, 67mA, 99mA, 131mA, 164mA, 196mA, 227mA, and 256mA, respectively.

[0072] When Vcc = 5.0V, the measured Icc values ​​were 43mA, 82mA, 131mA, 190mA, 250mA, 301mA, 339mA, and 368mA, respectively.

[0073] When Vcc = 5.5V, the measured Icc values ​​were 46mA, 89mA, 151mA, 226mA, 286mA, 328mA, 357mA, and 378mA, respectively.

[0074] See Figure 10 The diagram shows the DC characteristic curves of the HBT amplifier layout in this embodiment. Taking the collector current Icc under the collector voltage Vcc shown in m1, m2, and m3 as an example, Trace0 to 7 represent the DC characteristic curves of the amplifier under 8 different bias voltages:

[0075] When Vcc = 3.4V, the measured Icc values ​​were 36mA, 63mA, 91mA, 119mA, 145mA, 171mA, 196mA, and 219mA, respectively.

[0076] When Vcc = 5.0V, the measured Icc values ​​were 40mA, 72mA, 108mA, 146mA, 185mA, 224mA, 261mA, and 296mA, respectively.

[0077] When Vcc = 5.5V, the measured Icc values ​​were 42mA, 76mA, 116mA, 160mA, 206mA, 253mA, 294mA, and 328mA, respectively.

[0078] Depend on Figure 11 It is clear that as the bias voltage increases, the corresponding Icc values ​​of the two structures will differ even more. The optimized structure in this embodiment can significantly suppress thermal coupling, making the Icc more stable, i.e., the slope of the IV curve is smaller under the same bias voltage.

[0079] The following section will perform RF performance tests on the original structure of the HBT amplifier and the amplifier with the optimized structure in this embodiment.

[0080] In this embodiment, the performance evaluation uses a single-tone large signal-load traction test system. See the test items and system diagram below. Figure 12 As shown.

[0081] During specific testing, at a frequency of 5.8 GHz, the amplifier configured according to the layout structure of this embodiment was subjected to single-tone large signal power scanning under different static operating currents and different impedances. The gain (Gain) of the linear amplification operating region, the output power (Pout) of the gain compression operating region, and the maximum power-added efficiency (PAE) were evaluated.

[0082] See Figure 13 As shown, the test was conducted under a static bias of 3 kA / cm², according to the 50 ohm test procedure. The gain range of the existing structure is 8.6–9.5 dB (Δ = 0.9 dB), while the gain range of the optimized structure proposed in this embodiment is 8.3–8.5 dB (Δ = 0.2 dB). The maximum power-added efficiency of the two structures differs by approximately 3.6%.

[0083] See Figure 14 As shown, the test was conducted under a static bias of 5 kA / cm², according to the 50 ohm test procedure. The gain range of the existing structure is 9.4–9.7 dB (Δ = 0.3 dB), while the gain range of the optimized structure proposed in this embodiment is 9.1–9.2 dB (Δ = 0.1 dB). The maximum power-added efficiency of the two structures differs by approximately 3.3%.

[0084] See Figure 15 As shown, under a static bias of 3 kA / cm², the MaxPout test was performed. The gain range of the existing structure is 12.6–13.1 dB (Δ = 0.5 dB), while the gain range of the optimized structure proposed in this embodiment is 12.5–12.4 dB (Δ = 0.1 dB). The maximum power-added efficiency of the two structures differs by approximately 0.6%.

[0085] See Figure 16 The test was conducted under a static bias of 5 kA / cm², according to the MaxPout test item. The gain range of the existing structure is 13.4–13.6 dB (Δ = 0.2 dB), while the gain range of the optimized structure proposed in this embodiment is 12.8–13.3 dB (Δ = 0.5 dB). The maximum power-added efficiency of the two structures differs by approximately 1%.

[0086] have Figures 13-16 It can be seen that the gain flatness of the optimized structure proposed in this embodiment is similar to that of the original structure. In the above two test items, it can also be found that the structure of this embodiment improves the maximum value index of PAE.

[0087] In summary, the amplifier layout structure of this embodiment and the amplifier configured according to the amplifier layout structure can reduce the thermal coupling between HBT transistors, improve the thermal stability of the circuit, and avoid the risk of thermal effects such as current gain collapse. In certain application environments (in broadband circuit design with operating frequencies below 6GHz), it can effectively improve PAE without introducing additional defects, and the overall circuit gain and output power can be maintained at almost the same level as the original structure.

[0088] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements can be made without departing from the principle of the present invention, and these improvements should also be considered within the scope of protection of the present invention.

Claims

1. An amplifier layout structure, characterized in that, It includes an amplifier array consisting of N transistors; the amplifier array is distributed in a semi-enclosed structure, including a first transistor layout area, a third transistor layout area and a second transistor layout area arranged sequentially, and the first transistor layout area and the second transistor layout area are symmetrically arranged; wherein, N is greater than or equal to 3.

2. The amplifier layout structure according to claim 1, characterized in that, The signal input terminals of each transistor in the first transistor layout area, each transistor in the second transistor layout area, and each transistor in the third transistor layout area all face the inside of the layout structure, and the signal output terminals all face the outside of the layout structure.

3. The amplifier layout structure according to claim 1, characterized in that, The number of transistors disposed in the first transistor layout area and the second transistor layout area is equal.

4. The amplifier layout structure according to claim 1, characterized in that, When N is a multiple of 3, the number of transistors in the first transistor layout area, the second transistor layout area, and the third transistor layout area are equal.

5. The amplifier layout structure according to claim 1, characterized in that, Also includes: An input interconnect layout area is disposed within the semi-enclosed structure and is located on the third conductive layer, for interconnecting the signal input terminals of all transistors in the amplifier array.

6. The amplifier layout structure according to claim 1, characterized in that, Also includes: The output interconnection layout area is located outside the semi-enclosed structure. The output interconnection layout area includes a superimposed area of ​​a first conductive layer, a second conductive layer, and a third conductive layer, which is used to interconnect the signal output terminals of all transistors in the amplifier array. The first conductive layer, the second conductive layer, and the third conductive layer are arranged sequentially from bottom to top and are insulated from each other.

7. The amplifier layout structure according to claim 6, characterized in that, Also includes: The bias circuit layout area is located within the semi-enclosed structure; The bias circuit layout area is located below the third conductive layer and is insulated from the third conductive layer.

8. The amplifier layout structure according to claim 1, characterized in that, Also includes: A first pad layout area and a second pad layout area; the first pad layout area is located between the first transistor layout area and the third transistor layout area, and is used to connect the first excitation port of the bias circuit; the second pad layout area is located between the second transistor layout area and the third transistor layout area, and is used to connect the second excitation port of the bias circuit.

9. The amplifier layout structure according to claim 1, characterized in that, The transistor is a heterojunction bipolar transistor.

10. An amplifier, characterized in that, The amplifier is configured according to the amplifier layout structure described in any one of claims 1 to 9.

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