Semiconductor structure and method of manufacturing the same

Abstract

The application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate of a first doping type, at least two same units in the substrate, each of the units comprising a first well region of a second doping type extending from an upper surface of the substrate to an inner portion of the substrate, a first doped region of the second doping type extending from an upper surface of the first well region to an inner portion of the first well region, and a second doped region of the first doping type at least partially in the first doped region, wherein two adjacent units form a series-connected parasitic thyristor and diode. The semiconductor structure of the application reduces the area of the device and improves the robustness of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] The structure of a thyristor (Silicon Controlled Rectifier, SCR) is composed of PNPN transistors. Due to the positive feedback effect of the internally coupled PNP and NPN bipolar transistors, traditional SCR devices have extremely low sustaining voltage, usually 1 to 2V, which makes them prone to latch-up risks. Currently, some methods to improve the sustaining voltage are to increase the width or density of the base region of the parasitic bipolar transistor and reduce the amplification factor of the bipolar transistor.

[0003] like Figure 1 The cross-sectional view of a conventional high-sustaining-voltage bidirectional SCR shown depicts SCR1 connected in series with diode D2 from the first input / output terminal I / O_1 to the second input / output terminal I / O_2, and SCR2 connected in series with diode D1 from the second input / output terminal I / O_2 to the first input / output terminal I / O_1. SCR1 and SCR2, and D1 and D2, are perfectly symmetrical. Both the SCR and the diode are small capacitors, connected in series to achieve low capacitance. The high sustaining voltage of the SCR is achieved by increasing the base region width W2 of the NPN (N+-PW-NW) and simultaneously increasing the base region PW concentration to reduce current gain. Similarly, increasing the base region width W1 of the PNP (P+-NW-Psub) and the base region NW concentration reduces the PNP current gain. Ultimately, this reduces the positive feedback effect of the NPN and PNP SCRs, increasing the SCR's turn-on current to improve the sustaining voltage. This approach has two drawbacks: firstly, the increased layout area leads to increased chip cost; secondly, the high sustaining current reduces the device's robustness. Summary of the Invention

[0004] In summary, the present invention provides a semiconductor structure and its manufacturing method to solve the problems existing in the prior art.

[0005] According to a first aspect of the present invention, a semiconductor structure is provided, comprising: a substrate of a first doping type; at least two identical cells located in the substrate, each cell including a first well region of a second doping type extending from an upper surface of the substrate into its interior, a first doped region of a second doping type extending from an upper surface of the first well region into its interior, and a second doped region of a first doping type at least partially located in the first doped region, wherein adjacent cells form a parasitic thyristor and a diode connected in series.

[0006] Preferably, the junction depth of the first doped region is greater than that of the second doped region, and the two sides of the second doped region are not surrounded by the first doped region.

[0007] Preferably, a first region of a first doping type is included between two adjacent units.

[0008] Preferably, the distance between two adjacent first well regions is greater than or equal to 5 μm and less than or equal to 6 μm.

[0009] Preferably, the distance between the first region and the first well region is greater than or equal to 2 μm.

[0010] Preferably, the first region extends from the upper surface of the substrate to at least the lower surface of the first well region.

[0011] Preferably, it further includes a third doped region having a first doping type, located in the first region and extending from the upper surface of the first region into its interior.

[0012] Preferably, it further includes a third well region of a first doping type located in the substrate, the third well region being located below the first well region.

[0013] Preferably, in each pair of adjacent units, the second doped region of the first unit is connected to the first input / output terminal, and the second doped region of the second unit is connected to the second input / output terminal.

[0014] Preferably, when the voltage at the first input / output terminal is greater than the voltage at the second input / output terminal, the second doped region, the first well region, the substrate in the first unit, and the first well region in the second unit form the parasitic thyristor, and the first doped region and the second doped region in the second unit form the diode, and the current flowing from the first unit to the second unit flows sequentially through the parasitic thyristor and the diode.

[0015] Preferably, when the voltage at the second input / output terminal is greater than the voltage at the first input / output terminal, the second doped region, the first well region, the substrate in the second unit, and the first well region in the first unit form the parasitic thyristor, and the first doped region and the second doped region in the first unit form the diode, and the current flowing from the second unit to the first unit flows sequentially through the parasitic thyristor and the diode.

[0016] According to a second aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate of a first doping type; forming at least two identical cells in the substrate, wherein the method of forming at least two identical cells comprises: forming a first well region of a second doping type extending from an upper surface of the substrate into its interior, forming a first doped region of a second doping type extending from an upper surface of the first well region into its interior, and forming a second doped region of a first doping type at least partially located in the first doped region, wherein two adjacent cells form a parasitic thyristor and a diode connected in series.

[0017] Preferably, the junction depth of the first doped region is greater than that of the second doped region, and the two sides of the second doped region are not surrounded by the first doped region.

[0018] Preferably, a first region of a first doping type is formed between two adjacent units.

[0019] Preferably, the distance between the first region and the first well region is greater than or equal to 2 μm.

[0020] Preferably, the first region extends from the upper surface of the substrate to at least the lower surface of the first well region.

[0021] Preferably, the first region is formed by high-energy multiple injections.

[0022] Preferably, it further includes a third doped region having a first doping type, located in the first region and extending from the upper surface of the first region into its interior.

[0023] Preferably, the method further includes forming a third well region of a first doping type in the substrate, the third well region being located below the first well region.

[0024] Preferably, in every two adjacent cells, the second doped region of one cell is connected to the first input / output terminal, and the second doped region of the other cell is connected to the second input / output terminal.

[0025] The semiconductor structure provided by this invention places the second doped region within the first doped region, thereby forming a series connection of parasitic thyristors and diodes between adjacent identical units, reducing the device area. Furthermore, since the sustaining voltage is borne by the diode's breakdown voltage, rather than being passively pulled up under high sustaining current, the sustaining current is reduced, which enhances the device's robustness. Further, the junction depth of the first doped region is greater than that of the second doped region, and the sides of the second doped region are not surrounded by the first doped region, resulting in a breakdown junction below the planar junction of the second doped region, further improving the device's robustness. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0027] Figure 1 A cross-sectional view of a semiconductor structure according to the prior art is shown;

[0028] Figure 2 A cross-sectional view of a semiconductor structure according to a first embodiment of the present invention is shown;

[0029] Figure 3 An equivalent circuit diagram of a semiconductor structure according to a first embodiment of the present invention is shown;

[0030] Figure 4 A cross-sectional view of a semiconductor structure according to a second embodiment of the present invention is shown. Detailed Implementation

[0031] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0032] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0033] To describe a situation where A is directly above another layer or region, this document will use the expressions "A is directly above B" or "A is above and adjacent to B". In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0034] In this application, the term "wire punching" refers to the phenomenon where adjacent wires short-circuit due to the impact of the encapsulant during the injection of encapsulant after the chip is fixed on the lead frame and wire bonding is performed.

[0035] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0036] The present invention provides a semiconductor structure comprising: a substrate of a first doping type; at least two identical cells located in the substrate, each cell including a first well region of a second doping type extending from the upper surface of the substrate into its interior, a first doped region of a second doping type extending from the upper surface of the first well region into its interior, and a second doped region of a first doping type at least partially located in the first doped region, wherein adjacent cells form a parasitic thyristor and a diode connected in series.

[0037] Figure 2 A cross-sectional view of a semiconductor structure according to a first embodiment of the present invention is shown.

[0038] Please refer to Figure 2 The substrate 201 is, for example, composed of silicon and is of a first doping type. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. In this embodiment, the substrate 201 is preferably a high-resistivity substrate. If the doping concentration of the substrate 201 is too low, leakage may occur; if the doping concentration of the substrate 201 is too high, it will affect the capacitance of the device. Therefore, the resistivity of the substrate 201 is preferably 200 to 300 ohm·cm.

[0039] At least two identical units 202 are located in the substrate 201. Each unit 202 includes a first well region 210 extending from the upper surface of the substrate 201 into the substrate, a first doped region 211 extending from the upper surface of the first well region 210 into the substrate, and a second doped region 212 located at least partially in the first doped region 211. The second doped region 212 is of a first doping type, and the first well region 210 and the first doped region 211 are of a second doping type. It should be noted that if adjacent first well regions 210 are too close, there is a risk of punch-through leading to increased leakage current; if they are too far apart, the substrate 201 resistance between adjacent first well regions 210 will lead to increased clamping voltage. Therefore, in this embodiment, the distance between adjacent first well regions 210 is set to be greater than or equal to 4 μm and less than or equal to 6 μm; preferably, the distance between adjacent first well regions 210 is set to be greater than or equal to 5 μm and less than or equal to 6 μm. In this embodiment, the substrate 201 of the semiconductor structure includes three identical units, but is not limited to three; it may include two or more, depending on specific design specifications and needs.

[0040] In each pair of adjacent units, the second doped region 212 of one unit is connected to the first input / output terminal I / O_1, and the second doped region 212 of the other unit is connected to the second input / output terminal I / O_2. In this embodiment, from left to right, the first and third units of the semiconductor structure are connected to the first input / output terminal I / O_1, and the second unit located between the first and third units is connected to the second input / output terminal I / O_2. For example, when the first input / output terminal I / O_1 is at a high voltage and the second input / output terminal I / O_2 is at a low voltage, the second doped region 212 and the first well region 210 in the first unit, the substrate 201, and the first well region 210 in the second unit form a parasitic SCR, and the first doped region 211 and the second doped region 212 in the second unit form a reverse diode, wherein the parasitic SCR and the reverse diode are connected in series, and the corresponding equivalent circuit is as follows. Figure 3 As shown, the current flowing from the first unit to the second unit flows sequentially through the parasitic thyristor and the diode. When the first input / output terminal I / O_1 is at a low voltage and the second input / output terminal I / O_2 is at a high voltage, the second doped region 212 and the first well region 210 in the second unit, the substrate 201, and the first well region 210 in the first unit form a parasitic SCR. The first doped region 211 and the second doped region 212 in the first unit form a reverse diode. The parasitic SCR and the reverse diode are connected in series, and their corresponding equivalent circuit is shown below. Figure 3 As shown, the current flowing from the first unit to the second unit flows sequentially through the parasitic thyristor and the diode. Therefore, the semiconductor structure is bidirectional. Before the parasitic SCR is turned on, the turn-on voltage is the sum of the breakdown voltage between the first well region 210 and the substrate 201 and the breakdown voltage between the first doped region 211 and the second doped region 212. After the parasitic SCR is turned on, the sustaining voltage is mainly the breakdown voltage between the first doped region 211 and the second doped region 212.

[0041] In this embodiment, the junction depth of the first doped region 211 is greater than that of the second doped region 212, and the sides of the second doped region 212 are not surrounded by the first doped region 211. This allows the bottom surface of the second doped region 212 to contact the first doped region 211, and the side surface of the second doped region to contact the first well region. Because the doping concentration of the first doped region 211 is greater than that of the first well region 210, the bottom surface of the second doped region 212 will break down first, and the current will flow out from the bottom surface of the second doped region 212, rather than the side surface, thereby reducing the accumulation of charge at the corners of the side surface of the second doped region 212 and enhancing the performance of the device. Of course, in other embodiments, the second doped region 212 may also be completely located within the first doped region 211, that is, the first doped region 211 completely surrounds the bottom surface and side surface of the second doped region, without any limitation.

[0042] Additionally, the semiconductor structure further includes a first region 214 with a first doping type, located between adjacent first well regions. This first region 214 increases the doping concentration of the base region (substrate 201) in the parasitic SCR, thereby reducing the gain of the parasitic transistor (first well region 210 / substrate 201 / first well region 210) and preventing excessive turn-on leakage current. In this embodiment, the first region 214 extends from the upper surface of the substrate 201 to at least the lower surface of the first well region 210. The distance between the first region 214 and the first well region is set to be greater than or equal to 2 μm. In other embodiments, the first region 214 may also extend from the upper surface of the substrate to below the lower surface of the first well region, as long as the first region 214 is located between the first well regions 210 and meets the defined distance between them; its specific area is not limited.

[0043] In another embodiment, such as Figure 4 As shown, the system also includes a third doped region 316 located in the first region. The third doped region 316 is located on the surface of the substrate 201 and is of the first doping type. It is mainly used to adjust the turn-on voltage of the parasitic SCR and reduce the turn-on voltage of the parasitic SCR. The distance between the third doped region 316 and the first well region 210 is less than or equal to 1 μm; preferably, the distance is less than or equal to 0.5 μm.

[0044] In another embodiment, such as Figure 4As shown, the first region further includes a third well region 317 with a first doping type (p-type) located in the substrate. The third well region 317 is located below the first well region 210 and is used to isolate two adjacent cells 202 to prevent leakage. The third well region 317 is contactible with the first region. When the semiconductor structure includes the third well region 317, the substrate includes a substrate and an epitaxial layer located on the substrate. The cell 202, the first region 214, and the third doped region 316 are all located in the epitaxial layer. The third well region 317 is located in the substrate and extends from the upper surface of the substrate into its interior. The epitaxial layer is an intrinsic epitaxial layer or a lightly doped epitaxial layer of the first doping type.

[0045] The semiconductor structure also includes an isolation structure 215 located at the edge of the device, which can be filled with insulating material in the isolation trench.

[0046] Compared to existing technologies, the I / O terminals in existing technologies connect to both the N+ and P+ regions simultaneously, requiring a large current to establish the diode's turn-on voltage. Therefore, the holding current in existing technologies is relatively large, reducing the device's robustness. In contrast, the I / O terminals in this application only connect to the second doped region. When current flows, only a small current is needed to turn on the diode, resulting in a small holding current and increased device robustness. Furthermore, the structure of this application is simpler, reducing the device area.

[0047] The present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate of a first doping type; forming at least two identical cells in the substrate, wherein the method of forming at least two identical cells comprises: forming a first well region of a second doping type extending from the upper surface of the substrate into its interior, forming a first doped region of a second doping type extending from the upper surface of the first well region into its interior, and forming a second doped region of a first doping type at least partially located in the first doped region, wherein two adjacent cells form a parasitic thyristor and a diode connected in series.

[0048] Specifically, with Figure 2 Taking the semiconductor structure shown as an example, the manufacturing method includes:

[0049] Step 1: Using an ion implantation process, a first well region 210 of the second doped type is formed in the substrate 201, extending from the upper surface of the substrate into it. The junction depth of the first well region 210 should not be too deep, as excessive depth will affect the area of ​​the first well region 210 and thus its capacitance. It is important to note that if adjacent first well regions 210 are too close, there is a risk of punch-through, leading to increased leakage current; if they are too far apart, the resistance of the substrate 201 between adjacent first well regions 210 will increase the clamping voltage. Therefore, in this embodiment, the distance between adjacent first well regions 210 is set to be greater than or equal to 4 μm and less than or equal to 6 μm. Preferably, the distance between adjacent first well regions 210 is set to be greater than or equal to 5 μm and less than or equal to 6 μm.

[0050] Step 2: Using a high-energy ion implantation process, a first doped region 211 and a second doped region 212 of the second doping type are formed in the first well region 210. The second doped region 212 is at least partially located within the first doped region 211. Preferably, the junction depth of the first doped region 211 is greater than the junction depth of the second doped region 212, and the sides of the second doped region 212 are not surrounded by the first doped region 211. This allows the bottom surface of the second doped region 212 to contact the first doped region 211, and the side surface of the second doped region to contact the first well region. Because the doping concentration of the first doped region 211 is greater than that of the first well region 210, the bottom surface of the second doped region 212 will break down first, allowing current to flow out from the bottom surface of the second doped region 212, rather than the side surface, thereby reducing surface leakage current and improving device performance.

[0051] Step 3: Using a high-energy ion implantation process, a first region 214 with a first doping type is formed in the substrate. The first region 214 is located between adjacent first well regions to increase the doping concentration of the base region (substrate 201) in the parasitic SCR, thereby reducing the gain of the parasitic transistor (first well region 210 / substrate 201 / first well region 210) and preventing excessive turn-on leakage current. In this embodiment, the implantation energy range for forming the first region is 500–1000 keV, and multiple implantations can be selected to form the region, ensuring that the first region 214 has impurities of the first doping type from the surface of the substrate to the lower surface of the first well region, thus forming good isolation. The distance between the first region 214 and the first well region is set to be greater than or equal to 2 μm.

[0052] Step 4: Form an isolation structure 215 at the edge of the semiconductor structure. Specifically, form a trench at the edge of the semiconductor structure and then fill the trench with insulating material.

[0053] Step 5: Perform back-end processes to form interlayer dielectric layers, metal layers, passivation layers, and input / output terminals, etc.

[0054] In another embodiment, such as Figure 4 As shown, the method further includes using an ion implantation process to form a third doped region 316 with a first doping type in the substrate. The third doped region 316 is located on the surface of the substrate 201 between adjacent first well regions. The third doped region 316 is of the first doping type and is mainly used to adjust the turn-on voltage of the parasitic SCR, reducing the turn-on voltage of the parasitic SCR. The distance between the third doped region 316 and the first well region 210 is less than or equal to 1 μm; preferably, the distance is less than or equal to 0.5 μm. The doping concentration of the third doped region 316 is greater than the doping concentration of the second well region 214.

[0055] In another embodiment, such as Figure 4 As shown, the method further includes using an ion implantation process to form a third well region 317 with a first doping type (p-type) on the substrate. The third well region 317 is located below the first well region 210 and is used to isolate the two adjacent cells 202 to prevent leakage. The third well region 317 is contactible with the first region. Specifically, when the semiconductor structure includes the third well region 317, the substrate includes a substrate and an epitaxial layer located on the substrate. The third well region 317 is implanted to form on the upper surface of the substrate, and then the epitaxial layer is grown on the substrate. The cell 202, the first region 214, and the third doped region 316 are all located in the epitaxial layer. The epitaxial layer is an intrinsic epitaxial layer or a lightly doped epitaxial layer of the first doping type.

[0056] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0057] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, wherein, include: First type of doped substrate; At least two identical cells are located in the substrate, each cell including a first well region of a second doped type extending from the upper surface of the substrate into its interior, a first doped region of the second doped type extending from the upper surface of the first well region into its interior, and a second doped region of the first doped type located at least partially within the first doped region. Wherein, the junction depth of the first doped region is greater than that of the second doped region, and the two sides of the second doped region are not surrounded by the first doped region; In this configuration, two adjacent units form a parasitic thyristor and a diode connected in series.

2. The semiconductor structure according to claim 1, wherein, The first region of the first doping type is included between two adjacent units.

3. The semiconductor structure according to claim 1, wherein, The distance between two adjacent first well regions is greater than or equal to 5 μm and less than or equal to 6 μm.

4. The semiconductor structure according to claim 2, wherein, The distance between the first region and the first well region is greater than or equal to 2 μm.

5. The semiconductor structure according to claim 2, wherein, The first region extends from the upper surface of the substrate to at least the lower surface of the first well region.

6. The semiconductor structure according to claim 2, wherein, It also includes a third doped region of the first doping type located in the first region and extending from the upper surface of the first region into its interior.

7. The semiconductor structure according to claim 1, wherein, It also includes a third well region of a first doping type located in the substrate, the third well region being located below the first well region.

8. The semiconductor structure according to claim 1, wherein, In each pair of adjacent cells, the second doped region of the first cell is connected to the first input / output terminal, and the second doped region of the second cell is connected to the second input / output terminal.

9. The semiconductor structure according to claim 8, wherein, When the voltage at the first input / output terminal is greater than the voltage at the second input / output terminal, the second doped region, the first well region, the substrate in the first unit, and the first well region in the second unit form the parasitic thyristor, and the first doped region and the second doped region in the second unit form the diode. The current flowing from the first unit to the second unit flows sequentially through the parasitic thyristor and the diode.

10. The semiconductor structure according to claim 8, wherein, When the voltage at the second input / output terminal is greater than the voltage at the first input / output terminal, the second doped region, the first well region, the substrate in the second unit, and the first well region in the first unit form the parasitic thyristor, and the first doped region and the second doped region in the first unit form the diode. The current flowing from the second unit to the first unit flows sequentially through the parasitic thyristor and the diode.

11. A method for manufacturing a semiconductor structure, wherein, include: Provide a substrate of the first doping type; At least two identical units are formed in the substrate. The method of forming at least two identical units includes: forming a first well region of a second doped type extending from the upper surface of the substrate into its interior; forming a first doped region of a second doped type extending from the upper surface of the first well region into its interior; and forming a second doped region of a first doped type at least partially located within the first doped region. Wherein, the junction depth of the first doped region is greater than that of the second doped region, and the two sides of the second doped region are not surrounded by the first doped region; In this configuration, two adjacent units form a parasitic thyristor and a diode connected in series.

12. The method according to claim 11, wherein, A first region of the first doping type is formed between two adjacent units.

13. The method according to claim 12, wherein, The distance between the first region and the first well region is greater than or equal to 2 μm.

14. The method according to claim 12, wherein, The first region extends from the upper surface of the substrate to at least the lower surface of the first well region.

15. The method according to claim 14, wherein, The first region is formed by high-energy multiple injections.

16. The method of claim 14, wherein, It also includes a third doped region of the first doping type located in the first region and extending from the upper surface of the first region into its interior.

17. The method according to claim 11, wherein, It also includes forming a third well region of a first doping type in the substrate, the third well region being located below the first well region.

18. The method according to claim 11, wherein, In each pair of adjacent cells, the second doped region of one cell is connected to the first input / output terminal, and the second doped region of the other cell is connected to the second input / output terminal.

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