Image sensor and method of manufacturing the same

Abstract

An image sensor and a method of manufacturing the same are disclosed. The image sensor includes a silicon substrate having a first and a second surface, an insulating layer, a first silicon layer, a first isolation structure, a doped region, a second silicon layer, a transistor, an interconnection structure, a second isolation structure, a passivation layer, and a microlens. The insulating layer and the first silicon layer are sequentially on the first surface. The first isolation structure is in the first silicon layer to define an active region. The doped region is in a portion of the first silicon layer in the active region and a portion of the silicon substrate under the doped region. The second silicon layer is in a portion of the first silicon layer outside the doped region in the active region and extends into the silicon substrate. The transistor is on the first silicon layer in the active region. The interconnection structure is on the first silicon layer and electrically connected with the transistor. The second isolation structure is in the silicon substrate under the first isolation structure and connected with the insulating layer. The passivation layer is between the silicon substrate and the second isolation structure and surrounds the silicon substrate and is connected with the doped region. The microlens is on the second surface.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an image sensor and a method for manufacturing the same. Background Technology

[0002] With the continuous development and growth of products such as digital cameras and electronic scanners, the market demand for image sensing components continues to increase. Currently, commonly used image sensing components include two main categories: charge-coupled devices (CCDs) and complementary metal-oxide-semiconductor image sensors (CMOS image sensors, CIS). Among them, CMOS image sensors have advantages such as low operating voltage, low power consumption, high operating efficiency, and the ability to perform random access as needed. They also have the advantage of being able to be integrated into current semiconductor technology for mass production, so their application range is very wide.

[0003] To avoid image distortion of fast-moving objects, a global shutter (GS) image sensor has been developed, which mainly consists of transistors and photodiodes (PDs).

[0004] When external light enters the image sensor, the pixel performance is affected by the amount of light entering the photodiodes. Furthermore, adjacent photodiodes can easily experience light interference, which can affect their electrical signals. This, in turn, impacts the image sensor's performance. Summary of the Invention

[0005] The present invention provides an image sensor in which the photodiode has a large light-receiving area and uses a silicon-on-insulator (SOI) substrate to have a small parasitic capacitance.

[0006] The present invention provides a method for manufacturing an image sensor, which is used to form the image sensor described above.

[0007] The image sensor of the present invention includes a silicon substrate of a first conductivity type, an insulating layer, a first silicon layer, a first isolation structure, a first doped region of a second conductivity type, a second silicon layer of the first conductivity type, a transistor, an interconnect structure, a second isolation structure, a passivation layer, and a microlens. The silicon substrate of the first conductivity type has a first surface and a second surface opposite to each other. The insulating layer is disposed on the first surface of the silicon substrate. The first silicon layer is disposed on the insulating layer. The first isolation structure is disposed in the first silicon layer to define a first active region. The first doped region of the second conductivity type is disposed in a portion of the first silicon layer in the first active region and in a portion of the silicon substrate below it. The second silicon layer of the first conductivity type is disposed in a portion of the first silicon layer outside the first doped region in the first active region and extends through the insulating layer into the silicon substrate. The transistor is disposed on the first silicon layer in the first active region. The interconnect structure is disposed on the first silicon layer and electrically connected to the transistor. The second isolation structure is located in the silicon substrate below the first isolation structure and is connected to the insulating layer. The passivation layer is disposed between the silicon substrate and the second isolation structure, and surrounds the silicon substrate and is connected to the first doped region. The microlens is disposed on the second surface of the silicon substrate.

[0008] In an embodiment of the image sensor of the present invention, the bottom surface of the second silicon layer is not lower than the bottom surface of the first doped region in the silicon substrate.

[0009] In an embodiment of the image sensor of the present invention, a second doped region of a second conductivity type is further included, disposed on the surface of the second silicon layer.

[0010] In an embodiment of the image sensor of the present invention, the passivation layer includes a third doped region of a second conductivity type.

[0011] In an embodiment of the image sensor of the present invention, the passivation layer includes an aluminum oxide (Al2O3) layer, a hafnium oxide (HfO2) layer, or a combination thereof.

[0012] In an embodiment of the image sensor of the present invention, an anti-reflective layer and a color filter layer are further included. The anti-reflective layer is disposed between the silicon substrate and the microlens. The color filter layer is disposed between the anti-reflective layer and the microlens.

[0013] In an embodiment of the image sensor of the present invention, a light-shielding layer is further included. The light-shielding layer is disposed between the silicon substrate and the microlens, and partially overlaps with the silicon substrate.

[0014] In an embodiment of the image sensor of the present invention, the interconnect structure includes a dielectric layer and a circuit structure. The dielectric layer is disposed on the first silicon layer and covers the transistor and the first isolation structure. The circuit structure is disposed in the dielectric layer and is electrically connected to the transistor.

[0015] In an embodiment of the image sensor of the present invention, the first isolation structure further defines a second active region, and the image sensor further includes a fourth doped region of a second conductivity type, a third silicon layer of a second conductivity type, and a third isolation structure. The fourth doped region of the second conductivity type is disposed in a portion of the silicon substrate below the second active region. The third silicon layer of the second conductivity type is disposed in the first silicon layer in the second active region and extends through the insulating layer to connect with the fourth doped region, and the bottom surface of the third silicon layer is not lower than the bottom surface of the fourth doped region in the silicon substrate. The third isolation structure is located in the silicon substrate below the first isolation structure defining the second active region and is connected to the insulating layer. The passivation layer is further disposed between the silicon substrate and the third isolation structure, surrounds the silicon substrate, and is connected to the fourth doped region.

[0016] In an embodiment of the image sensor of the present invention, the interconnect structure is further electrically connected to the third silicon layer.

[0017] The method for manufacturing an image sensor according to the present invention includes the following steps: Providing a semiconductor substrate, wherein the semiconductor substrate includes a silicon substrate having a first conductivity type having a first surface and a second surface opposite to each other, an insulating layer located on the first surface, and a first silicon layer located on the insulating layer. Forming a first doped region of a second conductivity type in a portion of the first silicon layer and in a portion of the silicon substrate below it. Forming a first isolation structure in the first silicon layer to define a first active region, wherein the first doped region in the first silicon layer is located in the first active region. Forming a second silicon layer of the first conductivity type in a portion of the first silicon layer outside the first doped region in the first active region, wherein the second silicon layer extends through the insulating layer into the silicon substrate. Forming a transistor on the first silicon layer in the first active region. Forming an interconnect structure on the first silicon layer, wherein the interconnect structure is electrically connected to the transistor. Forming a second isolation structure in the silicon substrate below the first isolation structure, wherein the second isolation structure is connected to the insulating layer. Forming a passivation layer between the silicon substrate and the second isolation structure, wherein the passivation layer surrounds the silicon substrate and is connected to the first doped region. Forming a microlens on a second surface of the silicon substrate.

[0018] In an embodiment of the image sensor manufacturing method of the present invention, the bottom surface of the second silicon layer is not lower than the bottom surface of the first doped region in the silicon substrate.

[0019] In an embodiment of the method for manufacturing an image sensor according to the present invention, after forming the second silicon layer and before forming the transistor, a second doped region of a second conductivity type is further formed on the surface of the second silicon layer.

[0020] In an embodiment of the method for manufacturing an image sensor according to the present invention, the passivation layer includes a third doped region of a second conductivity type.

[0021] In an embodiment of the method for manufacturing an image sensor according to the present invention, the passivation layer includes an aluminum oxide layer, a hafnium oxide layer, or a combination thereof.

[0022] In an embodiment of the method for manufacturing the image sensor of the present invention, after forming the passivation layer and before forming the microlens, the method further includes the following steps: An anti-reflective layer is formed on the second surface of the silicon substrate. A color filter layer is formed on the anti-reflective layer.

[0023] In an embodiment of the method for manufacturing an image sensor according to the present invention, after forming the passivation layer and before forming the microlens, a light-shielding layer is further formed on the second surface of the silicon substrate, and the light-shielding layer partially overlaps with the silicon substrate.

[0024] In an embodiment of the image sensor manufacturing method of the present invention, the first isolation structure further defines a second active region, and the image sensor manufacturing method further includes the following steps: A fourth doped region of a second conductivity type is formed in a portion of the silicon substrate below the second active region. A third silicon layer of a second conductivity type is formed in the first silicon layer in the second active region, wherein the third silicon layer extends through the insulating layer and connects to the fourth doped region, and the bottom surface of the third silicon layer is not lower than the bottom surface of the fourth doped region in the silicon substrate. A third isolation structure is formed in the silicon substrate below the first isolation structure defining the second active region, wherein the third isolation structure is connected to the insulating layer. The passivation layer is further formed between the silicon substrate and the third isolation structure, and surrounds the silicon substrate and connects to the fourth doped region.

[0025] In an embodiment of the method for manufacturing the image sensor of the present invention, the interconnect structure is further electrically connected to the third silicon layer.

[0026] In an embodiment of the method for manufacturing an image sensor according to the present invention, after forming the interconnect structure and before forming the second isolation structure and the passivation layer, the method further includes thinning the silicon substrate.

[0027] In summary, in the image sensor of the present invention, the photodiode is composed of a silicon substrate having a first conductivity type and a doped region 104a of a second conductivity type within the silicon substrate. Therefore, the photodiode can have a relatively large light-receiving area and a high full-well capacity (FWC). Furthermore, in the present invention, an insulator-coated silicon substrate is used to fabricate the image sensor, thus enabling a small parasitic capacitance and allowing the photodiode to have a high conversion gain. As a result, the image sensor of the present invention can exhibit superior pixel performance.

[0028] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0029] Figures 1A to 1H This is a cross-sectional schematic diagram illustrating the manufacturing process of an image sensor according to an embodiment of the present invention.

[0030] Symbol Explanation

[0031] 10: Image sensor

[0032] 100: Semiconductor substrate

[0033] 100_1: Zone 1

[0034] 100_2: Second District

[0035] 100a: Silicon substrate

[0036] 100a_1: First surface

[0037] 100a_2: Second surface

[0038] 100b: Insulation layer

[0039] 100c: First silicon layer

[0040] 102: Silicon oxide layer

[0041] 104, 104a, 104b, 124: Doped regions

[0042] 106a, 106b, 134a, 134b: Isolation structures

[0043] 108a: First Active Region

[0044] 108b: Second Active Region

[0045] 110a, 110b, 130a, 130b: Grooves

[0046] 112: Second silicon layer

[0047] 114: Third silicon layer

[0048] 116: Silicon oxide layer

[0049] 118, 120: Gate

[0050] 122: Doped region

[0051] 126: Internal Wiring Structure

[0052] 126a: Dielectric layer

[0053] 126b: Window plug

[0054] 126c: Circuit pattern

[0055] 126d: Interlaminar window plug

[0056] 128: Carrier chip

[0057] 132: Passivation layer

[0058] 136: Anti-reflective layer

[0059] 138: Light-shielding layer

[0060] 140: Color filter layer

[0061] 142: Microlenses Detailed Implementation

[0062] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same elements will be designated with the same symbols in the following description.

[0063] The terms "includes," "includes," and "has" used in the text are all open-ended, meaning they "include but are not limited to."

[0064] When using terms such as "first" and "second" to describe elements, it is only for distinguishing these elements from one another and does not limit the order or importance of these elements. Therefore, in some cases, a first element may also be called a second element, and a second element may also be called a first element, without departing from the scope of this invention.

[0065] Furthermore, directional terms used in this document, such as "upper" and "lower," are merely for reference to the directions in the accompanying drawings and are not intended to limit the invention. Therefore, it should be understood that "upper" and "lower" can be used interchangeably, and when a layer or film is placed "on" another element, the element can be placed directly on the other element, or there may be an intermediate element. Conversely, when an element is said to be placed "directly" on another element, there is no intermediate element between them.

[0066] Figures 1A to 1H This is a cross-sectional schematic diagram illustrating the manufacturing process of an image sensor according to an embodiment of the present invention. In this embodiment, the first conductivity type is one of P-type and N-type, and the second conductivity type is the other of P-type and N-type.

[0067] First, refer to Figure 1A A semiconductor substrate 100 is provided. The semiconductor substrate 100 has a first region 100_1 and a second region 100_2. In this embodiment, the first region 100_1 and the second region 100_2 are different regions within the same pixel region. In this embodiment, the semiconductor substrate 100 includes a silicon substrate 100a, an insulating layer 100b, and a first silicon layer 100c. The silicon substrate 100a has a first conductivity type. In this embodiment, the silicon substrate 100a is, for example, an epitaxial silicon substrate, but the invention is not limited thereto. The silicon substrate 100a has a first surface 100a_1 and a second surface 100a_2 opposite to each other. The insulating layer 100b is disposed on the first surface 100a_1 of the silicon substrate 100a. In this embodiment, the insulating layer 100b is, for example, a silicon oxide layer, but the invention is not limited thereto. The thickness of the insulating layer 100b is, for example, between 100 nm and 200 nm. The first silicon layer 100c is disposed on the insulating layer 100b. The thickness of the first silicon layer 100c is, for example, between 70 nm and 3 μm. In other words, in this embodiment, the semiconductor substrate 100 is a commonly known silicon-on-insulator substrate.

[0068] Next, a silicon oxide layer 102 may be selectively formed on the first silicon layer 100c. The silicon oxide layer 102 may be formed, for example, by a chemical vapor deposition (CVD) process. Afterward, an ion implantation process may be performed to implant a dopant of the second conductivity type into the first silicon layer 100c and the silicon substrate 100a. In this embodiment, since the silicon oxide layer 102 is formed on the first silicon layer 100c, the channeling effect caused by ion implantation can be avoided. In other embodiments, the silicon oxide layer 102 may be omitted, and the channeling effect can be prevented by adjusting the ion implantation angle. This forms a doped region 104 of the second conductivity type. The doped region 104 is located in a portion of the first silicon layer 100c and the portion of the silicon substrate 100a below it. The detailed formation steps of the doped region 104 are well known to those skilled in the art and will not be described further here.

[0069] Then, refer to Figure 1B Isolation structures 106a and 106b are formed in the first silicon layer 100c. In this embodiment, isolation structures 106a and 106b are shallow trench isolation (STI) structures. Isolation structure 106a defines a first active region 108a, and isolation structure 106b defines a second active region 108b, such that the doped region 104 can be divided into a doped region 104a located in the first active region 108a and a doped region 104b located in the second active region 108b. In the first active region 108a, the doped region 104a is located in a portion of the first silicon layer 100c. In the second active region 108b, the doped region 104b is located in the entire first silicon layer 100c.

[0070] In this embodiment, the thickness of isolation structures 106a and 106b is the same as the thickness of the first silicon layer 100c, meaning that isolation structures 106a and 106b penetrate the first silicon layer 100c, effectively isolating adjacent active regions. In other embodiments, the thickness of isolation structures 106a and 106b may be greater than the thickness of the first silicon layer 100c, meaning that isolation structures 106a and 106b penetrate the first silicon layer 100c, and the top surface of isolation structures 106a and 106b may be higher than the top surface of the first silicon layer 100c. The methods for forming isolation structures 106a and 106b are well known to those skilled in the art and will not be described further here.

[0071] In this embodiment, after forming the doped region 104, the isolation structure 106a, and the isolation structure 106b, the silicon oxide layer 102 remains on the first silicon layer 100c. In other embodiments, after forming the doped region 104, the isolation structure 106a, and the isolation structure 106b, the silicon oxide layer 102 may be damaged or even completely consumed due to ion implantation and the etching process used to form the isolation structures 106a and 106b. Therefore, another silicon oxide layer may be formed on the first silicon layer 100c.

[0072] A trench 110a is formed in the silicon oxide layer 102, the first silicon layer 100c, the insulating layer 100b, and the silicon substrate 100a in the first active region 108a, and a trench 110b is formed in the silicon oxide layer 102, the first silicon layer 100c (doped 104b), the insulating layer 100b, and the silicon substrate 100a in the second active region 108b. In this embodiment, the bottom surface of the trench 110a is not lower than the bottom surface of the doped region 104a in the silicon substrate 100a, and the bottom surface of the trench 110b is not lower than the bottom surface of the doped region 104b in the silicon substrate 100a. In other embodiments, trenches 110a and 110b may expose the first surface 100a_1 of the silicon substrate 100a by penetrating only the insulating layer 100b. That is, the bottom surface of trenches 110a and 110b may be coplanar with the first surface 100a_1 of the silicon substrate 100a (the bottom surface of the insulating layer 100b).

[0073] Furthermore, in this embodiment, trench 110a and trench 110b are formed in the same fabrication process step, therefore trench 110a and trench 110b have the same depth, but the invention is not limited thereto. In other embodiments, trench 110a and trench 110b may have different depths, as long as trench 110b is not lower than the bottom surface of the doped region 104b in the silicon substrate 100a.

[0074] Next, refer to Figure 1CA second silicon layer 112 of a first conductivity type is formed in trench 110a, and a third silicon layer 114 of the first conductivity type is formed in trench 110b. The second silicon layer 112 and the third silicon layer 114 are formed by, for example, epitaxial fabrication or chemical vapor deposition, and the first conductivity type dopant is simultaneously (in-situ) doped. In this embodiment, the second silicon layer 112 is located in the first silicon layer 100c in the first active region 108a and extends through the insulating layer 100b into the silicon substrate 100a, while the third silicon layer 114 is located in the first silicon layer 100c (doped region 104b) in the second active region 108b and extends through the insulating layer 100b into the silicon substrate 100a, so as to connect with the doped region 104b in the silicon substrate 100a. Then, the silicon oxide layer 102 is removed. Next, a silicon oxide layer 116 is formed on the first silicon layer 100c. The silicon oxide layer 116 is used as the gate dielectric layer of the subsequently formed transistor. The silicon oxide layer 116 is formed, for example, by a thermal oxidation process.

[0075] Gates 118 and 120 are formed on the silicon oxide layer 116 in the first active region 108a. The material of gates 118 and 120 is, for example, doped polysilicon, and the formation method is well known to those skilled in the art and will not be described further here. In this embodiment, gate 118 can be used as a transfer gate, and gate 120 can be used as a reset gate, but the present invention is not limited thereto.

[0076] Then, refer to Figure 1D A doped region 122 of a second conductivity type is formed on the surface of the first silicon layer 100c and the second silicon layer 112 in the first active region 108a. The doped region 122 serves as a pinned layer. A dopant of the second conductivity type is implanted into the third silicon layer 114 and the first silicon layer 100c (doped region 104b) in the second active region 108b, so that both the third silicon layer 114 and the first silicon layer 100c (doped region 104b) in the second active region 108b have the second conductivity type. A dopant of the first conductivity type is implanted into a portion of the doped region 104a in the first active region 108a, forming a doped region 124 in the doped region 104a adjacent to the gate 118 and the gate 120. In this way, a transfer transistor and a reset transistor are formed on the first silicon layer 100c in the first active region 108a. The above doping steps are well known to those skilled in the art and will not be described further here. Furthermore, the order of the doping steps described above can be adjusted according to the actual situation, and the present invention does not impose any restrictions on this.

[0077] Next, refer to Figure 1EAn interconnect structure 126 is formed on the first silicon layer. The interconnect structure 126 is electrically connected to the aforementioned transfer transistor and reset transistor, and is also electrically connected to the third silicon layer 114 in the second active region 108b. The interconnect structure 126 includes a dielectric layer 126a formed on the third silicon layer 114 and a circuit structure formed in the dielectric layer 126a and electrically connected to the aforementioned transfer transistor, reset transistor, and third silicon layer 114. The circuit structure includes a contact plug 126b, a circuit pattern 126c, and a via plug 126d. The contact plug 126b connects the circuit pattern 126c to the aforementioned transfer transistor, reset transistor, and third silicon layer 114, while the via plug 126d connects the circuit patterns 126c of each layer. In this embodiment, a two-layer circuit pattern 126c is shown, but the invention is not limited thereto. In other embodiments, the interconnect structure 126 may include more or fewer layers of circuit patterns 126c. The detailed structure and formation method of the interconnect structure 126 are well known to those skilled in the art and will not be described further here.

[0078] Then, refer to Figure 1F The silicon substrate 100a is selectively thinned to reduce the thickness of the semiconductor substrate 100 from the second surface 100a_2 of the silicon substrate 100a. In this embodiment, a chemical mechanical polishing (CMP) process is performed on the second surface 100a_2 to remove a portion of the substrate 100, thereby reducing the thickness of the substrate 100. In this embodiment, a carry wafer 128 is bonded to the dielectric layer 126a before reducing the thickness of the semiconductor substrate 100, but the invention is not limited thereto.

[0079] A trench 130a is formed in the silicon substrate 100a in the first region 100_1, and a trench 130b is formed in the silicon substrate 100a in the second region 100_2. The trenches 130a and 130b penetrate the silicon substrate 100a and expose the insulating layer 100b. In this embodiment, the trench 130a is located directly below the isolation structure 106a, and the trench 130b is located directly below the isolation structure 106b, but the invention is not limited thereto.

[0080] Next, refer to Figure 1GA passivation layer 132 is formed around the silicon substrate 100a in the first region 100_1 and around the silicon substrate 100a in the second region 100_2. In the first region 100_1, the passivation layer 132 surrounds the silicon substrate 100a and is connected to a first doped region 104a in the silicon substrate 100a. In the second region 100_2, the passivation layer 132 surrounds the silicon substrate 100a and is connected to a doped region 104b in the silicon substrate 100a. In one embodiment, the passivation layer 132 may be a doped region of a second conductivity type, formed, for example, by plasma doping the exposed surface of the silicon substrate 100a. Alternatively, in another embodiment, the passivation layer 132 may be a high dielectric constant film, formed, for example, by chemical vapor deposition. In some embodiments, the high dielectric constant film is, for example, an aluminum oxide layer, a hafnium oxide layer, or a combination thereof, but the invention is not limited thereto.

[0081] An isolation structure 134a is formed in trench 130a, and an isolation structure 134b is formed in trench 130b. In this embodiment, isolation structures 134a and 134b are deep trench isolation (DTI) structures. Thus, isolation structure 134a is located in the silicon substrate 100a below isolation structure 106a and connected to insulating layer 100b, while isolation structure 134b is located in the silicon substrate 100a below isolation structure 106b and connected to insulating layer 100b. Therefore, isolation structures 134a and 134b penetrate the silicon substrate 100a. Furthermore, based on layout design, isolation structures 134a and 134b in the silicon substrate 100a can be designed to surround the entire pixel region, thus effectively isolating adjacent pixel regions and effectively reducing crosstalk between pixel regions. The methods for forming isolation structures 134a and 134b are well known to those skilled in the art and will not be described separately here.

[0082] Then, refer to Figure 1H An anti-reflective layer 136 is formed on the second surface 100a_2 of the silicon substrate 100. Next, a light-shielding layer 138 is formed on the anti-reflective layer 136. In this embodiment, the light-shielding layer 138 does not overlap with the silicon substrate 100a, but the invention is not limited thereto. In other embodiments, the light-shielding layer 138 may partially overlap with the silicon substrate 100a. Then, a color filter layer 140 is formed on the anti-reflective layer 136. Afterward, a microlens 142 is formed on the color filter layer 140 to complete the fabrication of the image sensor 10 of this embodiment.

[0083] In the image sensor 10, the silicon substrate 100a of the semiconductor substrate 100 has a first conductivity type, and the doped region 104a in the silicon substrate 100a has a second conductivity type. Therefore, the silicon substrate 100a and the doped region 104a constitute a photodiode. In this embodiment, the photodiode is composed of almost the entire silicon substrate 100a of the semiconductor substrate 100, thus having a relatively large light-receiving area, which improves the fill factor of the photodiode and provides a high potential well capacity. Furthermore, in this embodiment, an insulator-coated silicon substrate is used to fabricate the image sensor 10, thus enabling a smaller parasitic capacitance and allowing the photodiode to have a high conversion gain. As a result, the image sensor 10 can exhibit better pixel performance.

[0084] Furthermore, in the image sensor 10, the passivation layer 132 in the second region 100_2 surrounds the silicon substrate 100a and is connected to the doped region 104b in the silicon substrate 100a. In this way, the doped region of the second conductivity type in the photodiode can be grounded through the third silicon layer 114 in the second region 100_2.

[0085] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. An image sensor, comprising: A silicon substrate of a first conductivity type has a first surface and a second surface that are opposite to each other; An insulating layer is disposed on the first surface of the silicon substrate; as well as A first silicon layer is disposed on the insulating layer; A first isolation structure is disposed in the first silicon layer to define a first active region; The first doped region of the second conductivity type is disposed in a portion of the first silicon layer in the first active region and in a portion of the silicon substrate below it; A second silicon layer of a first conductivity type is disposed in a portion of the first silicon layer outside the first doped region in the first active region and extends through the insulating layer into the silicon substrate; A transistor is disposed on the first silicon layer in the first active region; An interconnect structure is disposed on the first silicon layer and electrically connected to the transistor; The second isolation structure is located in the silicon substrate below the first isolation structure and is connected to the insulating layer; A passivation layer is disposed between the silicon substrate and the second isolation structure, and surrounds the silicon substrate and is connected to the first doped region; as well as A microlens is disposed on the second surface of the silicon substrate.

2. The image sensor of claim 1, wherein the bottom surface of the second silicon layer is not lower than the bottom surface of the first doped region in the silicon substrate.

3. The image sensor of claim 1, further comprising a second doped region of a second conductivity type, disposed on the surface of the second silicon layer.

4. The image sensor of claim 1, wherein the passivation layer includes a third doped region of a second conductivity type.

5. The image sensor of claim 1, wherein the passivation layer comprises an aluminum oxide layer, a hafnium oxide layer, or a combination thereof.

6. The image sensor of claim 1, further comprising: An anti-reflective layer is disposed between the silicon substrate and the microlens; as well as A color filter layer is disposed between the anti-reflective layer and the microlens.

7. The image sensor of claim 1, further comprising a light-shielding layer disposed between the silicon substrate and the microlens, and partially overlapping the silicon substrate.

8. The image sensor of claim 1, wherein the interconnect structure comprises: A dielectric layer is disposed on the first silicon layer and covers the transistor and the first isolation structure; as well as The circuit structure is disposed in the dielectric layer and electrically connected to the transistor.

9. The image sensor of claim 1, wherein the first isolation structure further defines a second active region, and the image sensor further comprises: A fourth doped region of the second conductivity type is disposed in a portion of the silicon substrate below the second active region; A third silicon layer of the second conductivity type is disposed in the first silicon layer in the second active region and extends through the insulating layer to connect with the fourth doped region, and the bottom surface of the third silicon layer is not lower than the bottom surface of the fourth doped region in the silicon substrate; as well as A third isolation structure is located in the silicon substrate below the first isolation structure defining the second active region, and is connected to the insulating layer. The passivation layer is further disposed between the silicon substrate and the third isolation structure, and surrounds the silicon substrate and is connected to the fourth doped region.

10. The image sensor of claim 9, wherein the interconnect structure is further electrically connected to the third silicon layer.

11. A method for manufacturing an image sensor, comprising: A semiconductor substrate is provided, wherein the semiconductor substrate includes a silicon substrate having a first conductivity type having a first surface and a second surface opposite to each other, an insulating layer on the first surface, and a first silicon layer on the insulating layer; A first doped region of a second conductivity type is formed in a portion of the first silicon layer and in a portion of the silicon substrate below it; A first isolation structure is formed in the first silicon layer to define a first active region, wherein the first doped region in the first silicon layer is located in the first active region; A second silicon layer of a first conductivity type is formed in a portion of the first silicon layer outside the first doped region in the first active region, wherein the second silicon layer extends through the insulating layer into the silicon substrate; A transistor is formed on the first silicon layer in the first active region; An interconnect structure is formed on the first silicon layer, wherein the interconnect structure is electrically connected to the transistor; A second isolation structure is formed in the silicon substrate below the first isolation structure, wherein the second isolation structure is connected to the insulating layer; A passivation layer is formed between the silicon substrate and the second isolation structure, wherein the passivation layer surrounds the silicon substrate and is connected to the first doped region; as well as Microlenses are formed on the second surface of the silicon substrate.

12. The method of manufacturing an image sensor as claimed in claim 11, wherein the bottom surface of the second silicon layer is not lower than the bottom surface of the first doped region in the silicon substrate.

13. The method of manufacturing an image sensor as claimed in claim 11, wherein after forming the second silicon layer and before forming the transistor, the method further includes forming a second doped region of a second conductivity type at the surface of the second silicon layer.

14. The method of manufacturing an image sensor as claimed in claim 11, wherein the passivation layer includes a third doped region of a second conductivity type.

15. The method of manufacturing an image sensor as claimed in claim 11, wherein the passivation layer comprises an aluminum oxide layer, a hafnium oxide layer, or a combination thereof.

16. The method of manufacturing an image sensor as claimed in claim 11, further comprising, after forming the passivation layer and before forming the microlens: An anti-reflective layer is formed on the second surface of the silicon substrate; as well as A color filter layer is formed on the anti-reflective layer.

17. The method of manufacturing an image sensor as claimed in claim 11, wherein after forming the passivation layer and before forming the microlens, a light-shielding layer is further formed on the second surface of the silicon substrate, and the light-shielding layer partially overlaps the silicon substrate.

18. The method of manufacturing an image sensor as claimed in claim 11, wherein the first isolation structure further defines a second active region, and the method of manufacturing the image sensor further comprises: A fourth doped region of a second conductivity type is formed in the portion of the silicon substrate below the second active region; A third silicon layer of a second conductivity type is formed in the first silicon layer in the second active region, wherein the third silicon layer extends through the insulating layer and connects to the fourth doped region, and the bottom surface of the third silicon layer is not lower than the bottom surface of the fourth doped region in the silicon substrate; as well as A third isolation structure is formed in the silicon substrate beneath the first isolation structure defining the second active region, wherein the third isolation structure is connected to the insulating layer. The passivation layer is further formed between the silicon substrate and the third isolation structure, and surrounds the silicon substrate and is connected to the fourth doped region.

19. The method of manufacturing an image sensor as claimed in claim 18, wherein the interconnect structure is further electrically connected to the third silicon layer.

20. The method of manufacturing an image sensor as claimed in claim 11, wherein after forming the interconnect structure and before forming the second isolation structure and the passivation layer, the method further includes thinning the silicon substrate.

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