A topcon cell structure and a preparation method thereof
By setting a multi-layer doped polycrystalline silicon structure on the back of the TOPCon cell and optimizing the process, the problems of reduced cell efficiency and increased contact resistance were solved, achieving high-efficiency photoelectric conversion and low-loss cell performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHUZHOU JIETAI NEW ENERGY TECH CO LTD
- Filing Date
- 2023-05-29
- Publication Date
- 2026-07-21
AI Technical Summary
Existing TOPCon cells struggle to balance the thickness of the doped polycrystalline silicon in the metal contact region with the photoparasitic absorption in the non-metal region, resulting in reduced cell efficiency and issues such as paste collapse and increased contact resistance during the printing process.
A first doped polysilicon layer and a second doped polysilicon layer are set on the back side of the monocrystalline silicon wafer, below the back metal region and the back non-metal region. The polysilicon layer with optimized thickness and doping concentration is formed by combining PECVD and RVD processes to ensure good contact and low recombination current. At the same time, the structure of the metal region and the non-metal region is optimized by local blocking polishing and printing technology.
It improves the photoelectric conversion efficiency of the battery, reduces series resistance and recombination current, reduces light absorption loss, achieves high aspect ratio metal grid lines and good contact, and improves open circuit voltage and fill factor.
Smart Images
Figure CN116469947B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of battery processing technology, specifically to a TOPCon battery structure and its preparation method. Background Technology
[0002] Existing TOPCon (tunneling oxide passivated contact) solar cells typically consist of a 1-2 nm ultrathin tunneling oxide layer fabricated on the back side of a silicon wafer, followed by the deposition of an 80-200 nm thick doped polycrystalline silicon layer on the oxide layer surface, and finally, silicon nitride deposited on the doped polycrystalline silicon layer. This structure provides excellent surface and field passivation for the back side of the silicon wafer. The ultrathin oxide layer allows electrons to tunnel into the polycrystalline silicon layer while blocking hole transport, reducing recombination current. The lateral transport characteristics of the doped polycrystalline silicon layer reduce series resistance. These two characteristics together improve the cell's open-circuit voltage, fill factor, and conversion efficiency.
[0003] On the back of TOPCon cells, Ag paste is typically used to burn through the SiNx dielectric film to form an ohmic contact with doped polycrystalline silicon. In crystalline silicon solar cells, the grid lines act as collectors of photogenerated charge carriers. The amount of charge carriers generated (short-circuit current) and the amount of carrier loss during collection (series resistance) largely determine the electrical performance of the cell. Printing can lead to issues such as incomplete grid lines, broken grids, and rough edges on the silicon wafer, thus requiring improvements in the EL (efficiency level) of the silicon wafer. Higher grid line height and narrower width (i.e., a larger aspect ratio) help increase the short-circuit current and decrease the series resistance of the cell; therefore, improving the cell efficiency can improve the grid line aspect ratio. If the metal grid lines are made thinner and taller, the printed paste is prone to collapse, thus its performance is limited by factors such as the screen printing plate, the paste itself, and the sheet resistance of the silicon wafer. Furthermore, during the sintering process, metallic Ag grains may penetrate the doped polycrystalline silicon film, disrupting the passivation effect of the interface oxide layer. To address the issues of gate line resistance, contact resistance, and passivation, a high aspect ratio and good contact performance are required, along with a high doped polycrystalline silicon thickness, typically 100-150 nm. To ensure good field passivation and low ohmic contact, the doped polycrystalline silicon needs a sufficient doping concentration, typically >1e20 cm⁻¹. -3 .
[0004] However, excessive thickness and doping concentration of the polycrystalline silicon film in the aforementioned passivation structure can cause severe Auger recombination on the surface, leading to a deterioration in the short-wavelength response of the battery and an increase in saturation current. Simultaneously, parasitic absorption of back-incident light by the doped polycrystalline silicon reduces the bifaciality of the battery. Typically, balancing the aspect ratio of the grid lines, the thickness of the doped polycrystalline silicon film, and the doping concentration is difficult, requiring careful consideration of printing parameters, recombination, resistive losses, and optical losses. Currently, the main approach is to minimize the thickness of the polycrystalline silicon film while ensuring that the metal electrode paste does not burn through the tunneling oxide layer and that the metal electrode forms a good ohmic contact with the polycrystalline silicon film, thereby reducing parasitic absorption of photons within the highly doped polycrystalline silicon layer. Alternatively, the passivation structure can be used only in the metal electrode region of the battery, making it difficult to simultaneously achieve both light absorption and passivation effects. Summary of the Invention
[0005] To address the shortcomings of existing technologies, this invention provides a TOPCon battery structure and its fabrication method, which can ensure the thickness of doped polycrystalline silicon in the metal contact region, avoid damage to the tunneling oxide layer during sintering of the slurry, and reduce recombination current and contact resistance; at the same time, it can reduce photoparasitic absorption in the non-metallic region, especially reducing free carrier absorption.
[0006] To achieve the above objectives, the technical solution of the present invention is implemented through the following technical solution:
[0007] A TOPCon cell structure includes a monocrystalline silicon wafer, a diffusion layer, a passivation layer, a front antireflection layer, and a front metal electrode sequentially disposed on the front side of the monocrystalline silicon wafer, and a tunneling layer, a doped polycrystalline silicon layer, a back antireflection layer, and a back metal electrode sequentially disposed on the back side of the monocrystalline silicon wafer. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon layer located below the back metal region and a second doped polycrystalline silicon layer located below the back non-metal region; the first doped polycrystalline silicon layer is a phosphorus-doped polycrystalline silicon layer disposed on a textured surface, with a thickness of 100-150 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The second doped polysilicon layer is a phosphorus-doped polysilicon layer disposed on the polished surface, with a thickness of 100-150 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 .
[0008] Preferably, the single-crystal silicon wafer is a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1-10 Ωcm and a thickness of 150-200 μm.
[0009] Preferably, the diffusion layer is a boron-doped P-type layer with a sheet resistance of 100-300 Ω / □, formed by using pure hydrogen and diborane as boron precursors for doping.
[0010] Preferably, the passivation layer is aluminum oxide with a thickness of 2-6 nm, obtained by ALD deposition.
[0011] Preferably, the front antireflection layer and the back antireflection layer are composite films composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.
[0012] Preferably, the front metal electrode is an Ag / Al gate electrode, and the back metal electrode is an Ag gate electrode.
[0013] Preferably, the tunneling layer is silicon oxide with a thickness of 1-2 nm, and is formed by thermal oxidation, wet chemical oxidation, ozone oxidation, or plasma oxidation.
[0014] The preparation method of TOPCon battery includes the following steps:
[0015] S1. Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, and a surface texture is formed on the surface of silicon wafers to increase the absorption of sunlight and reduce reflection.
[0016] S2, PECVD SiOx: A silicon oxide diffusion barrier layer with a thickness of 50-100nm is grown on the back of a silicon wafer using PECVD technology. The purpose is to prevent the silicon substrate of the printed barrier paste from being contaminated and to prepare for the local barrier polishing step.
[0017] S3, Printing barrier paste: The paste is printed on the metal area on the back of the silicon wafer using a screen printing machine and then dried to protect the silicon oxide diffusion barrier layer.
[0018] S4. Localized barrier polishing: Hydrofluoric acid is used to clean and remove the silicon dioxide diffusion barrier layer of the printing paste in the non-metallic area on the back side, while hydrofluoric acid will not corrode the paste; the non-metallic area on the back side is polished by etching with an alkaline solution and the printing paste area is cleaned away, and then the silicon dioxide diffusion barrier layer in the paste area is washed away by HF.
[0019] S5, Front-side RVD: P-type doped emitters are formed using rapid vapor phase doping (RVD). This is mainly achieved by using diborane (B2H6) in an H2 environment as a dopant precursor in a CVD reactor. During the RVD doping process, dopants are directly incorporated into the silicon wafer without forming silicate glass. To prevent recombination caused by defects in the silicon substrate, a 100nm-275nm thermal oxide is grown by annealing during the process, while simultaneously blocking the diffusion of excess boron.
[0020] S6, Backside POPAID: A stacked structure of an ultrathin oxide layer and a 100nm-150nm phosphorus-doped amorphous silicon (a-Si) layer is deposited on the polished surface through plasma oxidation and magnetron sputtering (POPAID) processes; during plasma oxidation, the silicon wafer surface is oxidized by plasma excitation via radio frequency (RF) of O2 precursor gas, and the thickness of the SiOx layer is 1-2nm; for phosphorus-doped a-Si deposition, the plasma is excited by introducing Ar and PH3 precursor gases to increase the phosphorus content, and the flow rates of Ar and PH3 gases can be independently controlled by radio frequency (RF), temperature, and flow rate;
[0021] S7. Annealing activation: After thermal annealing in a dry N2 environment through a tube annealing furnace, amorphous silicon is recrystallized into polycrystalline silicon, and phosphorus is activated into an ionic state.
[0022] S8. Oxidation removal cleaning: Hydrofluoric acid cleaning is used to remove the hot oxide layer on the front side and the hot annealed oxide layer on the back side;
[0023] S9, ALD: A dense AlO layer is deposited on the front side of the substrate using ALD atomic layer deposition. X film;
[0024] S10, Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD;
[0025] S11, Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate by PECVD;
[0026] S12, Printing / Sintering / Photoinjection: The negative electrode Ag / Al paste is printed on the front side, and the electrode Ag paste is printed on the back side; co-sintering is performed to form a good ohmic contact; photoinjection repairs defects in the cell body and on the surface.
[0027] This invention provides a TOPCon battery structure and its fabrication method, which has the following advantages compared with the prior art:
[0028] (1) The present invention provides a first doped polysilicon layer below the back metal region and a second doped polysilicon layer located in the back non-metal region on the back side of an N-type single-crystal silicon wafer. The first doped polysilicon layer is textured phosphorus-doped polysilicon with a thickness of 100-150 nm and a doping concentration of not less than 1e20 cm⁻¹. -3On the one hand, the first doped polysilicon layer is placed on the textured surface, which can ensure good contact and low contact resistance of the paste in the metal contact area; it can make the metal grid lines thinner and taller, and the printed paste is not easy to collapse, reducing the light-shielding area of the grid lines and the consumption of silver paste; at the same time, it solves the problems of ohmic contact and line resistance, reduces the series resistance of the battery, and improves the photoelectric conversion efficiency of the battery; on the other hand, since the first doped polysilicon layer is textured, its internal junction depth is greater than that of the second doped polysilicon layer. The first doped polysilicon layer below the back metal region has a deeper back field, which can effectively prevent the electrode metal from penetrating into the junction region, reduce the recombination current density of the back metal region, improve the open circuit voltage and fill factor of the battery, and thus improve the battery efficiency.
[0029] (2) This invention prints a blocking paste in the metal region and performs local blocking polishing to retain the textured surface of the back metal region and form a polished surface in the non-metal region. Then, a boron-doped layer is formed using RVD. This is mainly achieved by using diborane (B2H6) in an H2 environment as a dopant precursor in the CVD reactor. During the RVD doping process, dopant atoms are directly incorporated into the silicon wafer without forming silicate glass. The silicon wafer is placed in a large quartz carrier in a quartz tube parallel to the main gas flow, and the optical heating furnace only covers the middle part of the quartz tube where the sample is placed. Therefore, no torsion is formed during the RVD doping process. POPAID forms a tunneled oxidation and phosphorus-doped polycrystalline silicon layer through plasma oxidation and magnetron sputtering processes. After polishing, an ultrathin oxide layer and a phosphorus-doped amorphous silicon layer are deposited on the surface in a stacked structure. During the plasma oxidation process, the silicon wafer surface is oxidized by plasma through radio frequency (RF) excitation of the O2 precursor gas. X The layer thickness is 1-2 nm; phosphorus doping deposition is achieved by introducing Ar and PH3 precursor gases and exciting plasma to increase the phosphorus content, and the flow rates of Ar and PH3 gases can be independently controlled by radio frequency (RF), temperature, and flow rate. The thickness of the phosphorus-doped polycrystalline silicon layer is 100-150 nm; the first doped polycrystalline silicon layer is obtained with a doping concentration of 5e19-6e20 cm⁻¹. -3 The thickness is 100-150 nm; the second doped polycrystalline silicon layer has a doping concentration of 5e19~6e20 cm⁻¹. -3The thickness is 100-150nm. On the one hand, the junction depth of the metal contact region of the first polycrystalline silicon layer is greater than that of the second doped polycrystalline silicon layer, which helps to prevent the electrode metal from penetrating into the junction region and reduces the probability of the electrode metal introducing impurity energy levels in the bandgap. In addition, the formation of the lateral high and low junction depths on the front surface can reduce the contact resistance while ensuring good passivation, so that the recombination current densities Jo1 and Jo2 in the metal region are reduced, and the Voc and pFF of the battery are improved. On the other hand, the metal contact region of the first doped polycrystalline silicon layer is textured, so there is good contact between the metal grid line and the semiconductor, which can achieve a high aspect ratio of the metal grid line, and the printed paste is not easy to collapse, thereby reducing the light-shielding area of the grid line and reducing the consumption of silver paste, increasing the short-circuit current of the battery cell and reducing the series resistance of the battery cell. In addition, the preparation method of the present invention is simple and easy to implement. Attached image description:
[0030] Figure 1 This is a flowchart of the TOPCon battery manufacturing process of the present invention;
[0031] Figure 2 This is a structural diagram of the TOPCon battery of the present invention;
[0032] Figure 3 This is a comparative example of the existing TOPCon battery structure diagram.
[0033] 1. Monocrystalline silicon wafer; 2. Diffusion layer; 3. Passivation layer; 4. Front antireflection layer; 5. Front metal electrode; 6. Tunneling layer; 7. Doped polycrystalline silicon layer; 7-1. First doped polycrystalline silicon layer; 7-2. Second doped polycrystalline silicon layer; 8. Back antireflection layer; 9. Back metal electrode. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] Example 1:
[0036] A TOPCon cell structure includes a monocrystalline silicon wafer 1, a diffusion layer 2, a passivation layer 3, a front antireflection layer 4, and a front metal electrode 5 sequentially disposed on the front side of the monocrystalline silicon wafer 1, and a tunneling layer 6, a doped polycrystalline silicon layer 7, a back antireflection layer 8, and a back metal electrode 9 sequentially disposed on the back side of the monocrystalline silicon wafer 1. The doped polycrystalline silicon layer 7 includes a first doped polycrystalline silicon layer 7-1 located below the back metal region and a second doped polycrystalline silicon layer 7-2 located below the back non-metal region; the first doped polycrystalline silicon layer 7-1 is a phosphorus-doped polycrystalline silicon layer disposed on a textured surface; the second doped polycrystalline silicon layer 7-2 is a phosphorus-doped polycrystalline silicon layer disposed on a polished surface.
[0037] The specific manufacturing process of the TOPCon battery is as follows:
[0038] S1. Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, and a surface texture is formed on the surface of silicon wafers to increase the absorption of sunlight and reduce reflection.
[0039] S2, PECVD SiO X The purpose of growing a silicon oxide diffusion barrier layer with a thickness of 80nm on the back side of a silicon wafer using PECVD technology is to prevent the silicon substrate from being contaminated by the printed barrier paste and to prepare for the local barrier polishing step.
[0040] S3, Printing barrier paste: The paste is printed on the metal area on the back of the silicon wafer using a screen printing machine and then dried to protect the silicon oxide diffusion barrier layer;
[0041] S4. Localized barrier polishing: Hydrofluoric acid is used to clean and remove the silicon dioxide diffusion barrier layer of the printing paste in the non-metallic area on the back side, while hydrofluoric acid will not corrode the paste; the non-metallic area on the back side is polished by etching with an alkaline solution and the printing paste area is cleaned away, and then the silicon dioxide diffusion barrier layer in the paste area is washed away by HF.
[0042] S5, Front-side RVD: The diffusion layer is formed using the emitter diffusion method of rapid vapor phase doping (RVD). In a chemical vapor deposition (CVD) reactor, diborane (B2H6) is used as a dopant precursor in an H2 environment. During the RVD doping process, dopant atoms are directly incorporated into the silicon wafer without forming silicate glass. To prevent recombination caused by defects in the silicon substrate, a 200nm thermal oxide is grown by annealing during the process, which also blocks excess boron diffusion.
[0043] S6, Backside POPAID: A stacked structure of an ultrathin oxide layer and a 130nm phosphorus-doped amorphous silicon layer is deposited on the polished surface through plasma oxidation and magnetron sputtering processes; during plasma oxidation, the silicon wafer surface is oxidized by plasma excitation via radio frequency (RF) of O2 precursor gas, resulting in SiO2. XThe layer thickness is 2nm; phosphorus-doped a-Si deposition is achieved by introducing Ar and PH3 precursor gases, exciting plasma to increase phosphorus content, and the flow rates of Ar and PH3 gases can be independently controlled by radio frequency (RF), temperature, and flow rate.
[0044] S7. Annealing activation: After thermal annealing in a dry N2 environment through a tubular annealing furnace, amorphous silicon is recrystallized into polycrystalline silicon, and phosphorus is activated into an ionic state.
[0045] S8. Oxidation removal cleaning: Hydrofluoric acid cleaning is used to remove the hot oxide layer on the front side and the hot annealed oxide layer on the back side;
[0046] S9, ALD: A dense AlOx film is deposited on the front side of the substrate using ALD atomic layer deposition.
[0047] S10, Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD;
[0048] S11, Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate by PECVD;
[0049] S12, Printing / Sintering / Photoinjection: The negative electrode Ag / Al paste is printed on the front side, and the electrode Ag paste is printed on the back side; co-sintering is performed to form a good ohmic contact; photoinjection repairs defects in the cell body and on the surface.
[0050] Comparative Example 1:
[0051] As a comparative example, the battery structure is as follows: Figure 3 As shown, compared with Example 1, the difference is that the back side of the silicon wafer uses single-doped polycrystalline silicon with a thickness of 120 nm and a doping concentration of 3e20cm. -3 .
[0052] Detection:
[0053] The electrical performance parameters of the TOPCon batteries obtained in Example 1 and Comparative Example 1 are shown in the table below:
[0054]
[0055] Comparing the TOPCon cells prepared in Example 1 with those prepared in Comparative Example 1, it can be seen that the TOPCon cells prepared in Example 1 have higher conversion efficiency and open-circuit voltage.
[0056] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A TOPCon battery structure, comprising a monocrystalline silicon wafer (1), a diffusion layer (2), a passivation layer (3), a front antireflection layer (4), and a front metal electrode (5) sequentially disposed on the front side of the monocrystalline silicon wafer (1), and a tunneling layer (6), a doped polycrystalline silicon layer (7), a back antireflection layer (8), and a back metal electrode (9) sequentially disposed on the back side of the monocrystalline silicon wafer (1), characterized in that, The doped polysilicon layer (7) includes a first doped polysilicon layer (7-1) located below the back metal region and a second doped polysilicon layer (7-2) located below the back non-metal region. The first doped polysilicon layer (7-1) is a phosphorus-doped polysilicon layer disposed on the textured surface, with a thickness of 100-150 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The second doped polycrystalline silicon layer (7-2) is a phosphorus-doped polycrystalline silicon layer disposed on the polished surface, with a thickness of 100-150 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 ; The method for preparing the TOPCon battery structure includes the following steps: S1. Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, and a surface texture is formed on the surface of silicon wafers to increase the absorption of sunlight and reduce reflection. S2, PECVD SiOx: A silicon oxide diffusion barrier layer with a thickness of 50-100nm is grown on the back side of a silicon wafer using PECVD technology. S3, Printing barrier paste: The paste is printed on the metal area on the back of the silicon wafer using a screen printing machine and then dried to protect the silicon oxide diffusion barrier layer; S4. Localized barrier polishing: Hydrofluoric acid is used to clean and remove the silicon dioxide diffusion barrier layer of the printing paste in the non-metallic area on the back side; the non-metallic area on the back side is polished by alkaline etching and the printing paste area is cleaned away, and then the silicon dioxide diffusion barrier layer in the paste area is washed away by HF. S5, Front RVD: The diffusion layer is formed by emitter diffusion using rapid vapor phase doping (RVD). This is mainly achieved in a chemical vapor deposition (CVD) reactor using diborane in an H2 environment as a dopant precursor. During the RVD doping process, dopant atoms are directly incorporated into the silicon wafer without forming silicate glass. To prevent recombination caused by defects in the silicon substrate, a 100nm-275nm thermal oxide is grown by annealing during the process, which also blocks excess boron diffusion. S6, Backside POPAID: Through plasma oxidation and magnetron sputtering (POPAID) processes, an ultrathin oxide layer and a stacked structure of 100nm-150nm phosphorus-doped amorphous silicon (a-Si) layer are deposited on the polished surface; during the plasma oxidation process, the silicon wafer surface is oxidized by plasma through radio frequency excitation of O2 precursor gas, the SiOx layer is 1-2 nm thick, phosphorus-doped a-Si is deposited, and the plasma is excited by introducing Ar and PH3 precursor gases to increase the phosphorus content; S7. Annealing activation: After thermal annealing in a dry N2 environment through a tube annealing furnace, amorphous silicon is recrystallized into polycrystalline silicon, and phosphorus is activated into an ionic state. S8. Oxidation removal cleaning: Hydrofluoric acid cleaning is used to remove the hot oxide layer on the front side and the hot annealed oxide layer on the back side; S9, ALD: A dense AlOX film is deposited on the front side of the substrate using ALD atomic layer deposition. S10, Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD; S11, Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate by PECVD; S12, Printing / Sintering / Photoinjection: The negative electrode Ag / Al paste is printed on the front side, and the electrode Ag paste is printed on the back side; co-sintering is performed to form a good ohmic contact; photoinjection repairs defects in the cell body and on the surface.
2. The TOPCon battery structure according to claim 1, characterized in that: The single-crystal silicon wafer (1) is a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1-10 Ωcm and a thickness of 150-200 μm.
3. The TOPCon battery structure according to claim 1, characterized in that: The diffusion layer (2) is a P-type doped layer formed by boron doping, with a sheet resistance of 100-300 Ω / □, and is formed by using pure hydrogen and diborane as boron precursors for doping.
4. The TOPCon battery structure according to claim 1, characterized in that: The passivation layer (3) is aluminum oxide with a thickness of 2-6 nm, obtained by ALD deposition.
5. A TOPCon battery structure according to claim 1, characterized in that: The front antireflective layer (4) and the back antireflective layer (8) are both composite films composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.
1.
6. A TOPCon battery structure according to claim 1, characterized in that: The front metal electrode (5) is an Ag / Al gate electrode, and the back metal electrode (9) is an Ag gate electrode.
7. A TOPCon battery structure according to claim 1, characterized in that: The tunneling layer (6) is silicon oxide with a thickness of 1-2 nm, and is formed by thermal oxidation, wet chemical oxidation, ozone oxidation, and plasma oxidation.
8. A TOPCon battery structure according to claim 1, characterized in that: In step S5, silicon is epitaxially deposited using a chemical vapor deposition reactor RTCVD160.