Capacitor equivalent circuit and electronic device

Abstract

The application provides a capacitor equivalent circuit and an electronic device. The capacitor equivalent circuit comprises an OSC circuit, a comparator, an operational amplifier, a first charge-discharge circuit, a second charge-discharge circuit, a resistor and a capacitor. The input ends of the OSC circuit are respectively connected to the two ends of the resistor, and the output end of the OSC circuit is connected to one input end of the first charge-discharge circuit and one input end of the second charge-discharge circuit. The two ends of the resistor are also respectively connected to two input ends of the comparator, and the two output ends of the comparator are respectively connected to another input end of the first charge-discharge circuit and another input end of the second charge-discharge circuit. The output end of the first charge-discharge circuit and the output end of the second charge-discharge circuit are both connected to one end of the capacitor and the positive input end of the operational amplifier. The negative input end of the operational amplifier is connected to the output end of the operational amplifier and the negative input end of the comparator. The positive input end of the comparator is connected to an input current. The application can provide a capacitor equivalent circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology or chip technology, specifically to a capacitor equivalent circuit and electronic device. Background Technology

[0002] In practical applications, the importance of capacitors as a fundamental circuit component is self-evident. RC series circuits are also frequently used in filtering and compensation circuits. However, in current integrated circuit applications, the large capacitance and large size of capacitors make it difficult to integrate them inside the chip. Often, a separate pin is needed to connect capacitors placed externally to the chip, increasing actual production costs. Summary of the Invention

[0003] This application provides a capacitance equivalent circuit and an electronic device, which can realize a capacitance equivalent circuit and can be integrated into a chip.

[0004] In a first aspect, embodiments of this application provide a capacitor equivalent circuit, which includes: an OSC circuit, a comparator, an operational amplifier, a first charging / discharging circuit, a second charging / discharging circuit, a resistor, and a capacitor; wherein,

[0005] The input terminals of the OSC circuit are respectively connected to the two ends of the resistor, and the output terminal of the OSC circuit is connected to one input terminal of the first charge-discharge circuit and one input terminal of the second charge-discharge circuit; the two ends of the resistor are also respectively connected to two input terminals of the comparator, and the two output terminals of the comparator are also respectively connected to the other input terminal of the first charge-discharge circuit and the other input terminal of the second charge-discharge circuit.

[0006] The output terminals of the first charge-discharge circuit and the second charge-discharge circuit are both connected to one end of the capacitor and the positive input terminal of the operational amplifier; the other end of the capacitor is grounded; the negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and the negative input terminal of the comparator; the positive input terminal of the comparator is connected to the input current.

[0007] Secondly, embodiments of this application provide an electronic device, which includes the capacitor equivalent circuit described in the first aspect.

[0008] Implementing the embodiments of this application has the following beneficial effects:

[0009] Based on the capacitance equivalent circuit and electronic device provided in the embodiments of this application, the capacitance equivalent circuit includes: an OSC circuit, a comparator, an operational amplifier, a first charging / discharging circuit, a second charging / discharging circuit, a resistor, and a capacitor. The input terminals of the OSC circuit are connected to both ends of the resistor, and the output terminal of the OSC circuit is connected to one input terminal of the first charging / discharging circuit and one input terminal of the second charging / discharging circuit. The two ends of the resistor are also connected to two input terminals of the comparator, and the two output terminals of the comparator are also connected to the other input terminal of the first charging / discharging circuit and the other input terminal of the second charging / discharging circuit. The output terminals of the first and second charging / discharging circuits are both connected to one end of the capacitor and the positive input terminal of the operational amplifier. The other end of the capacitor is grounded. The negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and the negative input terminal of the comparator. The positive input terminal of the comparator is connected to the input current. Therefore, the above capacitance equivalent circuit uses a small capacitor (small volume capacitor) to achieve the effect of a large capacitor, thereby effectively integrating a large capacitor inside the chip. This reduces the number of external devices and lowers system production costs. Furthermore, it reduces the impact of aging-induced capacitance reduction in external capacitors. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of an RC series circuit in a conventional integrated circuit provided in an embodiment of this application;

[0012] Figure 2 This is a schematic diagram of a capacitor equivalent circuit provided in an embodiment of this application;

[0013] Figure 3 This is a schematic diagram of another capacitor equivalent circuit provided in an embodiment of this application;

[0014] Figure 4 This is a schematic diagram of another capacitor equivalent circuit provided in an embodiment of this application;

[0015] Figure 5 This is a schematic diagram of the waveforms related to a capacitor equivalent circuit provided in an embodiment of this application. Detailed Implementation

[0016] To help those skilled in the art better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the description of the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, software, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but also includes steps or units not listed, or other steps or units inherent to such processes, methods, products, or apparatus.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] The embodiments of this application are described below with reference to the accompanying drawings. In the drawings, the intersection of intersecting wires is indicated by dots, and the absence of dots indicates that the wires are not connected.

[0020] Related technologies, such as Figure 1 As shown, when a large capacitance value is required (above the nF level), integrating the capacitor inside the chip requires significant chip resources or may not be feasible. In this case, a dedicated pin is typically needed to connect the large capacitor externally. However, this dedicated pin consumes internal chip resources, and the external capacitor increases the system size and manufacturing cost.

[0021] Please see Figure 2 , Figure 2 This is a schematic diagram of a capacitor equivalent circuit provided in an embodiment of this application. The capacitor equivalent circuit includes: an OSC circuit, a comparator, an operational amplifier, a first charging / discharging circuit, a second charging / discharging circuit, a resistor R, and a capacitor C. p ;in,

[0022] The input terminals of the OSC circuit are respectively connected to the two ends of the resistor R, and the output terminal of the OSC circuit is connected to one input terminal of the first charge-discharge circuit and one input terminal of the second charge-discharge circuit; the two ends of the resistor R are also respectively connected to the two input terminals of the comparator, and the two output terminals of the comparator are also respectively connected to the other input terminal of the first charge-discharge circuit and the other input terminal of the second charge-discharge circuit.

[0023] The output terminals of the first charge-discharge circuit and the second charge-discharge circuit are both connected to the capacitor C. p One end of the capacitor and the positive input terminal of the operational amplifier; the capacitor C p The other end is grounded; the negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and the negative input terminal of the comparator; the positive input terminal of the comparator is connected to the input current I. in .

[0024] Optionally, in a specific implementation, the capacitor equivalent circuit in the embodiments of this application can achieve the following functions:

[0025] The OSC circuit is used to generate a clock signal based on the voltage across the resistor R.

[0026] The comparator is used to determine the voltage direction of the resistor R and generate a corresponding enable signal based on the voltage direction;

[0027] The first charge-discharge circuit is used to discharge the capacitor based on the clock signal and the first preset enable signal when the enable signal is the first preset enable signal;

[0028] The second charge-discharge circuit is used to charge the capacitor based on the clock signal and the second preset enable signal when the enable signal is the second preset enable signal.

[0029] The first and second preset enable signals can both be preset or set by system default. The first and second preset enable signals are opposite to each other. The first preset enable signal can be denoted as the Down enable signal, and the second preset enable signal can be denoted as the Up enable signal. The clock signal can be denoted as CLK.

[0030] The capacitor equivalent circuit in this application embodiment uses a small capacitor (small volume capacitor) to achieve the effect of a large capacitor, thereby effectively integrating a large capacitor inside the chip. On the one hand, this reduces the number of external devices and lowers the system production cost; on the other hand, it reduces the impact of the capacitance value of external capacitors decreasing due to aging.

[0031] Please see Figure 3 , Figure 3This is a schematic diagram of a capacitor equivalent circuit provided in an embodiment of this application. The first charging / discharging circuit includes: a first switch control unit 4, a first pulse generating circuit 8, and a first controlled current source 7; the second charging / discharging circuit includes: a second switch control unit 5, a second pulse generating circuit 9, and a second controlled current source 6; the first switch control unit 4 is connected to one end of the first pulse generating circuit 8, and the other end of the first pulse generating circuit 8 is connected to the control terminal of the first controlled current source 7; the second switch control unit 5 is connected to one end of the second pulse generating circuit 9, and the other end of the second pulse generating circuit 9 is connected to the control terminal of the second controlled current source 6; the current input terminal of the first controlled current source 7 is connected to the current output terminal of the second controlled current source 6; the current output terminal of the first controlled current source 7 is grounded; the current input terminal of the second controlled current source 6 is connected to the power supply VCC; the current output terminal of the second controlled current source 6 is also connected to the capacitor C. p And the positive input terminal of the operational amplifier 3.

[0032] In its specific implementation, the capacitor equivalent circuit includes: OSC circuit 1, comparator 2, operational amplifier 3, first switch control unit 4, second switch control unit 5, first pulse generation circuit 8, second pulse generation circuit 9, first controlled current source 7, second controlled current source 6, and capacitor C. p The OSC circuit has its input terminals connected to both ends of a resistor R, and its output terminal connected to one input terminal of the first switch control unit 4 and the second switch control unit 5. The two ends of the resistor R are also connected to the input terminal of the comparator 2. The inverting output terminal of the comparator 2 is connected to the other input terminal of the first switch control unit 4, and the non-inverting output terminal is connected to the other input terminal of the second switch control unit 5. The input terminals of the first pulse generation circuit 8 and the second pulse generation circuit 9 are connected to the output terminals of the first switch control unit 4 and the second switch control unit 5, respectively. The output terminals of the first pulse generation circuit 8 and the second pulse generation circuit 9 are connected to the control terminals of the first controlled current source 7 and the second controlled current source 6, respectively. The current input terminal of the first controlled current source 7 is connected to the current output terminal of the second controlled current source 6, and the current input terminal of the first controlled current source 7 is also connected to the capacitor C. p One end of the capacitor is connected to the positive input terminal of the operational amplifier 3; the current output terminal of the first controlled current source 7 is grounded, and the current input terminal of the second controlled current source 6 is connected to the power supply VCC; the capacitor C p The other end is grounded; the inverting input terminal of the operational amplifier 3 is connected to its output terminal, and the output terminal of the operational amplifier 3 is also connected to the negative terminal of the resistor R.

[0033] The first switch control unit 4 may include an AND gate or a switch device, and the second switch control unit 5 may include an AND gate or a switch device.

[0034] Furthermore, when both the first switch control unit 4 and the second switch control unit 5 are AND gates, such as Figure 4 As shown, that is Figure 3 The switch control units in the circuit can all be replaced with AND gates. Resistor R is the corresponding series resistor, equivalent to resistor R in an RC circuit.

[0035] Optionally, the OSC circuit 1 is used to sample the resistor voltage of the resistor R and output a clock signal whose frequency is positively correlated with the absolute value of the voltage.

[0036] In its implementation, the input terminals of OSC circuit 1 are connected to both ends of resistor R, and its output terminal is connected to one input terminal of AND gates 4 and 5. Specifically, OSC circuit 1 is based on the voltage V across resistor R. R This generates a clock signal CLK whose frequency is related to the voltage.

[0037] Optionally, the comparator 2 is used to determine the direction of the voltage across the resistor R, and the first switch control unit 4 and the second switch control unit 5 control the path of the clock signal based on the output of the comparator 2.

[0038] In a specific implementation, taking the example where both the first switch control unit 4 and the second switch control unit 5 are AND gates, the two ends of the resistor R are also connected to the input terminals of comparator 2. The positive output terminal of comparator 2 is connected to one input terminal of AND gate 5, and the negative output terminal is connected to one input terminal of AND gate 4. Specifically, comparator 2 is based on voltage V. R The polarity generates corresponding enable signals Up and Down. AND gates 4 and 5 control the path of the clock signal based on enable signals Up and Down.

[0039] Optionally, both the first pulse generation circuit 8 and the second pulse generation circuit 9 generate corresponding pulse signals based on the input clock signal, and the pulse signals control the opening and closing of the first controlled current source 7 and the second controlled current source 6.

[0040] In specific implementation, when V R When the condition is positive, Up is set high and Down is set to zero, and AND gate 5 outputs a clock signal; otherwise, Up is set to zero, Down is set high, and AND gate 4 outputs a clock signal.

[0041] Optionally, the pulse duration of the pulse signal is constant;

[0042] The current of the first controlled current source 7 is constant, and the turn-on or turn-off time is equal to the pulse time of the pulse signal;

[0043] And / or,

[0044] The current of the second controlled current source 6 is constant, and the turn-on or turn-off time is equal to the pulse time of the pulse signal.

[0045] Optionally, when the first controlled current source 7 is turned on, the capacitor C p Discharge; when the second controlled current source 6 is turned on, the capacitor C p Charge.

[0046] In a specific implementation, taking the example where both the first switch control unit 4 and the second switch control unit 5 are AND gates, the input terminals of the first pulse generation circuit 8 and the second pulse generation circuit 9 are respectively connected to the output terminals of AND gates 4 and 5, and their output terminals are respectively connected to the control terminals of the first controlled current source 7 and the second controlled current source 6. Specifically, the first pulse generation circuit 8 and the second pulse generation circuit 9 generate a pulse signal with a fixed pulse duration based on the rising edge of the valid clock signal at the input terminal, thereby controlling the opening and closing of the first controlled current source 7 and the second controlled current source 6.

[0047] In specific implementation, the current output terminal of the second controlled current source 6 is connected to the current input terminal of the first controlled current source 7, and the current input terminal of the first controlled current source 7 is also connected to a capacitor C. p One end of the first controlled current source 7 is connected to the positive input terminal of the operational amplifier 3; the current input terminal of the second controlled current source 6 is connected to the power supply VCC, and the current output terminal of the first controlled current source 7 is grounded; capacitor C p The other end is grounded.

[0048] Specifically, when the pulse signal arrives at the control terminal of the second controlled current source 6 or the first controlled current source 7, the corresponding current source turns on and generates a fixed current as capacitor C. p The charging or discharging cycle is synchronized with the pulse signal duration; for example, when the up-pulse signal is generated, the second controlled current source 6 is turned on for a fixed time, which is equal to the capacitance C. p Charge a fixed amount of charge.

[0049] Optionally, the operational amplifier 3 forms a voltage follower circuit, and the capacitor C p The voltage at the negative terminal of the resistor R is equal to the voltage at the negative terminal of the resistor R.

[0050] In the specific implementation, the inverting input terminal of operational amplifier 3 is connected to its output terminal, and then connected to the negative terminal of resistor R. Specifically, the operational amplifier forms a voltage follower circuit, causing capacitor C to... p voltage V cpVoltage V at the negative terminal of the resistor cz equal.

[0051] In this embodiment of the application, the specific capacitance equivalence principle is as follows: In such... Figure 1 In the conventional RC series circuit shown, the voltage V across the capacitor is... c With the current I in the series circuit in Related, and also due to current I in And the voltage V across resistor R R Therefore, we can obtain the following formula (1):

[0052]

[0053] And in Figure 4 In the capacitor equivalent circuit proposed in the embodiment of this application shown, the frequency f of the output clock CLK of OSC circuit 1 is related to the resistor voltage V of the input resistor R. R The absolute values ​​are positively correlated, as follows:

[0054] f=K·|V R | (2)

[0055] Among them, comparator 2 detects the resistor voltage V R It is used to detect the direction of voltage. When the current I... in When it is in the positive direction, V R If the signal is positive, the positive output signal Up of comparator 2 is set high; otherwise, the negative output signal Down of comparator 2 is set high.

[0056] AND gates 4 and 5 are used to select the path of the clock signal. When the Up signal is valid, AND gate 5 will output the clock signal; when the Down signal is valid, AND gate 4 will output the clock signal.

[0057] The first pulse generation circuit 8 and the second pulse generation circuit 9 receive the clock signal from the input terminal and generate corresponding pulse signals. In this embodiment, the first pulse generation circuit 8 and the second pulse generation circuit 9 are used to generate pulse signals Up-pulse and Down-pulse with fixed pulse times based on the rising edge of the clock signal, with a pulse time of t. pulse .

[0058] In addition, the pulse signal is used to control the first controlled current source 7 and the second controlled current source 6. The currents of the first controlled current source 7 and the second controlled current source 6 are constant, and the current magnitude is I. p When the pulse signal is generated, either the first controlled current source 7 or the second controlled current source 6 is turned on for a time t. pulse And for capacitor C p Charging or discharging. For a single pulse signal, capacitor C...p Voltage change ΔV cp It can be represented by formula (3).

[0059] Specifically, when an up-pulse occurs, the capacitor C p voltage V cp Increase ΔV cp When a down-pulse occurs, capacitor C p voltage V cp Decrease ΔV cp The details are as follows:

[0060]

[0061] In this embodiment, the frequencies of the pulse signals Up-pulse and Down-pulse are equal to the clock signal CLK, and therefore also equal to the voltage V across the series resistor. R The absolute values ​​are positively correlated, and the capacitance C p The rate of change of voltage is related to the frequency of the pulse signal, from which the voltage V can be derived. cp The rate of change of voltage V R The absolute value is related; on the other hand, the voltage V when a single pulse signal is generated... cp The direction of change (increase or decrease) is related to the voltage V. R Direction-dependent, i.e., voltage V R When positive, V cp An increase indicates an increase, and a decrease indicates a decrease. Therefore, the capacitor voltage V is obtained. cp The rate of change of V R The absolute value is related to V, and the direction of change is related to V. R The direction is related. In summary, the capacitor voltage V... cp It can be represented by formula (4), as follows:

[0062] V cp =ΔV cp K∫V R dt (4)

[0063] Furthermore, the voltage follower formed by operational amplifier 3 will convert the voltage V cp The synchronous switch is applied to the negative terminal of resistor R, i.e., the voltage V. cz With voltage V cp equal.

[0064] Compare the capacitor voltage V in the conventional RC series circuit shown in formula (1) c When formula (5) holds true, the voltage V cz and Figure 1 The capacitor voltage V in c They are equal. Therefore, in Figure 4In the diagram, viewed from the negative terminal of resistor R, a capacitor with a capacitance of [value missing] is effectively connected in series. Figure 1 For a large capacitor with the same capacitance C, formula (5) is as follows:

[0065]

[0066] Furthermore, the waveform diagram of the relevant signal is as follows: Figure 5 As shown.

[0067] For example, in this embodiment of the application, the resistance R is 100kΩ, and the capacitor C... p The capacitance is 16pF, and the current source current I p The pulse duration t is 0.2uA. pulse Since the pulse duration is 20ns, according to Equation 3, the capacitance C corresponding to a single pulse is... p Voltage change ΔV cp It is 0.25mV.

[0068] According to Equation 5, when the ratio K between the clock frequency and the absolute value of the resistor voltage is 20,000,000 (i.e., 0.1V voltage corresponds to a 2MHz frequency), the equivalent series capacitance is 2nF. Changing the ratio K adjusts the size of the equivalent capacitance, and similarly, changing the capacitance C... p Current I p Pulse time t pulse Related parameters can also change the value of the equivalent capacitance.

[0069] In this embodiment, the equivalent capacitance is achieved based on the voltage across the series resistor. Specifically, the magnitude of the voltage determines the clock frequency, i.e., the small capacitor C. p The charging and discharging speed; the direction of the voltage determines whether charging or discharging.

[0070] The capacitance equivalent circuit provided in this application embodiment includes: an OSC circuit 1, a comparator 2, an operational amplifier 3, a first switch control unit 4, a second switch control unit 5, a first pulse generation circuit 8, a second pulse generation circuit 9, a first controlled current source 7, a second controlled current source 6, and a capacitor C. pThe OSC circuit has its input terminals connected to both ends of resistor R and its output terminal connected to one input terminal of the first switch control unit 4 and the second switch control unit 5. Resistor R is also connected to the input terminal of comparator 2. The inverting output terminal of comparator 2 is connected to the other input terminal of the first switch control unit 4, and the non-inverting output terminal is connected to the other input terminal of the second switch control unit 5. The input terminals of the first pulse generation circuit 8 and the second pulse generation circuit 9 are connected to the output terminals of the first switch control unit 4 and the second switch control unit 5, respectively. The output terminals of the first pulse generation circuit 8 and the second pulse generation circuit 9 are connected to the control terminals of the first controlled current source 7 and the second controlled current source 6, respectively. The current input terminal of the first controlled current source 7 is connected to the current output terminal of the second controlled current source 6. The current input terminal of the first controlled current source 7 is also connected to capacitor C. p One end of the capacitor is connected to the positive input terminal of operational amplifier 3; the current output terminal of the first controlled current source 7 is grounded, and the current input terminal of the second controlled current source 6 is connected to power supply VCC; capacitor C p The other end is grounded; the inverting input of operational amplifier 3 is connected to its output, and the output of operational amplifier 3 is also connected to the negative end of resistor R. Thus, a small capacitor (small volume capacitor) is used to achieve the effect of a large capacitor, thereby effectively integrating a large capacitor inside the chip. On the one hand, this reduces the number of external devices and lowers the system production cost; on the other hand, it reduces the impact of the capacitance value of external capacitors decreasing due to aging.

[0071] In this application embodiment, an electronic device may also be provided, which includes the above-described capacitor equivalent circuit. The electronic device may include any device that includes the above-described capacitor equivalent circuit or chip. For example, the electronic device may include at least one of the following: charger, mobile phone, laptop, desktop computer, chip, in-vehicle equipment, wearable device, server, etc., without limitation. Furthermore, by using a small capacitor (small volume capacitor) to achieve the effect of a large capacitor, a large capacitor is effectively integrated inside the chip. This reduces the number of external components and lowers system production costs; on the other hand, it reduces the impact of the capacitance value decreasing due to aging of external capacitors.

[0072] The above are the implementation methods of the embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the embodiments of this application, and these improvements and modifications are also considered to be within the protection scope of this application.

Claims

1. A capacitance equivalent circuit characterized by, The capacitor equivalent circuit includes: an OSC circuit, a comparator, an operational amplifier, a first charging / discharging circuit, a second charging / discharging circuit, a resistor, and a capacitor; wherein, The input terminals of the OSC circuit are respectively connected to the two ends of the resistor, and the output terminal of the OSC circuit is connected to one input terminal of the first charge-discharge circuit and one input terminal of the second charge-discharge circuit; the two ends of the resistor are also respectively connected to two input terminals of the comparator, and the two output terminals of the comparator are also respectively connected to the other input terminal of the first charge-discharge circuit and the other input terminal of the second charge-discharge circuit. The output terminals of the first charge-discharge circuit and the second charge-discharge circuit are both connected to one end of the capacitor and the positive input terminal of the operational amplifier; the other end of the capacitor is grounded; the negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and the negative input terminal of the comparator; the positive input terminal of the comparator is connected to the input current.

2. The capacitor equivalent circuit according to claim 1, characterized in that, The OSC circuit is used to generate a clock signal based on the voltage across the resistor. The comparator is used to determine the voltage direction of the resistor and generate a corresponding enable signal based on the voltage direction; The first charge-discharge circuit is used to discharge the capacitor based on the clock signal and the first preset enable signal when the enable signal is the first preset enable signal; The second charge-discharge circuit is used to charge the capacitor based on the clock signal and the second preset enable signal when the enable signal is the second preset enable signal; The first preset enable signal and the second preset enable signal are enable signals that are opposite to each other.

3. The capacitance equivalent circuit according to claim 2, characterized in that, The first charge-discharge circuit includes: a first switch control unit, a first pulse generation circuit, and a first controlled current source; the second charge-discharge circuit includes: a second switch control unit, a second pulse generation circuit, and a second controlled current source. The first switch control unit is connected to one end of the first pulse generation circuit, and the other end of the first pulse generation circuit is connected to the control terminal of the first controlled current source. The second switch control unit is connected to one end of the second pulse generation circuit, and the other end of the second pulse generation circuit is connected to the control terminal of the second controlled current source; The current input terminal of the first controlled current source is connected to the current output terminal of the second controlled current source; the current output terminal of the first controlled current source is grounded; the current input terminal of the second controlled current source is connected to a power supply; the current output terminal of the second controlled current source is also connected to the capacitor and the positive input terminal of the operational amplifier.

4. The capacitance equivalent circuit according to claim 3, characterized in that, The frequency of the clock signal is positively correlated with the absolute value of the voltage.

5. The capacitance equivalent circuit according to claim 4, characterized in that, Both the first switch control unit and the second switch control unit control the path of the clock signal based on the output of the comparator.

6. The capacitance equivalent circuit according to any one of claims 3 to 5, characterized in that, Both the first pulse generation circuit and the second pulse generation circuit generate corresponding pulse signals based on the input clock signal, and the pulse signals control the opening and closing of the first controlled current source and the second controlled current source.

7. The capacitance equivalent circuit according to claim 6, characterized in that, The pulse duration of the pulse signal is constant; The current of the first controlled current source is constant, and the turn-on or turn-off time is equal to the pulse time of the pulse signal; And / or, The current of the second controlled current source is constant, and the turn-on or turn-off time is equal to the pulse time of the pulse signal.

8. The capacitance equivalent circuit according to any one of claims 3 to 5, characterized by The operational amplifier forms a voltage follower circuit, and the voltage of the capacitor is equal to the voltage at the negative terminal of the resistor.

9. The capacitor equivalent circuit according to any one of claims 3-5, characterized in that, The first switch control unit includes an AND gate or a switching device; And / or, The second switch control unit includes an AND gate or a switch device.

10. An electronic device, characterized in that, The electronic device includes the capacitor equivalent circuit as described in any one of claims 1-9.

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