A semiconductor structure manufacturing method, a semiconductor structure and a memory

Abstract

The present disclosure provides a semiconductor structure manufacturing method, a semiconductor structure and a memory. The semiconductor structure manufacturing method comprises: providing a substrate, the substrate is formed with an active region and a shallow trench isolation structure adjacent to the active region; forming a contact hole on the substrate, the bottom of the contact hole exposes at least part of the active region and at least part of the shallow trench isolation structure; forming a conductive plug in the contact hole, the bottom of the conductive plug is electrically connected with the active region; forming a first isolation structure, the first isolation structure fills the contact hole and directly contacts with the conductive plug; wherein the first isolation structure comprises a first laminated structure. The present disclosure can reduce the formation of leakage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random data writing and reading. It consists of multiple memory cells, each including a transistor and a capacitor. As the feature size of semiconductor integrated circuit devices continues to shrink, parasitic capacitance easily exists between the semiconductor structure and the contact conductors. In the semiconductor structure, the parasitic capacitance between the BL (Bit Line) and SNC (Storage Node Contact) accounts for a large portion of the BL's parasitic capacitance and is prone to GIDL (Gated-Induce-Drain Leakage) leakage.

[0003] Therefore, how to solve the above problems has become an urgent issue for those skilled in the art. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate in which an active region and a shallow trench isolation structure adjacent to the active region are formed; forming a contact hole on the substrate, the bottom of the contact hole exposing at least a portion of the active region and at least a portion of the shallow trench isolation structure; forming a conductive plug in the contact hole, the bottom of the conductive plug being electrically connected to the active region; and forming a first isolation structure that fills the contact hole and is in direct contact with the conductive plug; wherein the first isolation structure includes a first stacked structure.

[0005] In some embodiments, the step of forming a conductive plug in the contact hole further includes: forming a bit line structure located on the conductive plug.

[0006] In some embodiments, the step of forming the first isolation structure includes the following steps: forming an initial first oxide layer, the initial first oxide layer covering the surface of the bit line structure, the sidewall of the conductive plug, the inner wall of the contact hole, and the surface of the substrate; forming an initial insulating layer, the initial insulating layer covering the surface of the initial first oxide layer and filling the contact hole; removing a portion of the initial insulating layer, the remaining initial insulating layer constituting an insulating layer, the insulating layer and the initial first oxide layer in contact with the insulating layer constituting the first isolation structure.

[0007] In some embodiments, after forming the first isolation structure, a second isolation structure is also formed on the sidewall of the bit line structure, the second isolation structure including a second stacked structure.

[0008] In some embodiments, the step of forming a second stacked structure includes: forming an initial second oxide layer covering the surfaces of the partially exposed initial first oxide layer and insulating layer; removing a portion of the initial second oxide layer and a portion of the initial first oxide layer to obtain an oxide layer comprising a first oxide layer and a second oxide layer located on the sidewalls of the bit line structure, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer; and forming a nitride layer to obtain a second stacked structure comprising the oxide layer and the nitride layer.

[0009] In some embodiments, before removing a portion of the initial insulating layer, an annealing process is further included.

[0010] In some embodiments, removing a portion of the initial insulating layer includes: removing a portion of the initial insulating layer using thermal phosphoric acid etching to form the insulating layer.

[0011] In some embodiments, the annealing treatment lasts for 1-2 hours and the annealing temperature is 400℃-550℃.

[0012] In some embodiments, the first stacked structure includes an insulating layer, the top of which is higher than the top of the substrate and lower than the top of the conductive plug.

[0013] A second aspect of this disclosure also provides a semiconductor structure, comprising: a substrate, an active region located in the substrate, and a shallow trench isolation structure adjacent to the active region; a contact hole located in the substrate, the bottom of the contact hole exposing at least a portion of the active region and at least a portion of the shallow trench isolation structure; a conductive plug located in the contact hole, the bottom of the conductive plug being electrically connected to the active region; and a first isolation structure filling the contact hole and directly contacting the conductive plug; wherein the first isolation structure comprises a first stacked structure.

[0014] In some embodiments, the semiconductor structure further includes: a bit line structure located on the conductive plug; a second isolation structure located on the sidewall of the bit line structure; and the second isolation structure includes a second stacked structure.

[0015] In some embodiments, the second stacked structure includes an oxide layer-nitride layer structure.

[0016] In some embodiments, the oxide layer includes a first oxide layer and a second oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer.

[0017] In some embodiments, the top of the conductive plug is higher than the top of the substrate.

[0018] In some embodiments, the first stacked structure includes an insulating layer, the top of which is higher than the top of the substrate and lower than the top of the conductive plug.

[0019] In some embodiments, the top width of the insulating layer is greater than the bottom width of the second oxide layer.

[0020] According to a third aspect of the present disclosure, a memory is provided, including the semiconductor structure described above.

[0021] The above-disclosed technical solution has at least the following beneficial technical effects:

[0022] In this embodiment of the present disclosure, by forming a first isolation structure in the contact hole, wherein the first isolation structure includes a first stacked structure, the first stacked structure in the contact hole has only one Nitride / Oxide interface. Accordingly, the reduction of the Nitride / Oxide interface will reduce the influence of the presence of interface charge on the electric field distribution in the active region of the substrate, thereby reducing the GIDL leakage phenomenon. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0025] Figures 2-8 This is a schematic diagram illustrating the structure presented in the flowchart of a semiconductor structure fabrication method according to an exemplary embodiment.

[0026] Figure label:

[0027] 10. Substrate; 20. Bit line structure; 21. Barrier layer; 22. Conductive layer; 23. Dielectric layer; 30. Initial first oxide layer; 31. First oxide layer; 40. Initial insulating layer; 41. Insulating layer; 50. Initial second oxide layer; 51. Second oxide layer; 60. Nitride layer; 11. Contact hole; 12. Active region; 13. Shallow trench isolation structure; 70. Conductive plug. Detailed Implementation

[0028] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0030] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0031] The parasitic capacitance of the BL (Bluerpiece) directly affects the sensing margin, and the parasitic capacitance between the BL and the SNC (Self-Nutrient Controller) accounts for a large portion of the BL's parasitic capacitance. In related technologies, dielectric material is typically filled between the SNC and BL to reduce the BL's parasitic capacitance. One method to reduce the BL's parasitic capacitance is to reduce the dielectric constant of the material between the SNC and BL, because oxides have a smaller dielectric constant than nitrides. Replacing the previous Nitride structure with a NON (Nitride-Oxide-Nitride) structure can significantly reduce the BL's parasitic capacitance.

[0032] However, current NON structures generate several Nitride / Oxide interfaces, which typically contain interface charges. Particularly in NON structures within BLC (Bitline Contact) vias, these interface charges, due to their proximity to the substrate's active region, can affect the electric field distribution within the substrate's active region and increase GIDL leakage.

[0033] Therefore, how to solve the above problems has become an urgent issue for those skilled in the art.

[0034] This disclosure provides a method for fabricating a semiconductor structure, including:

[0035] S101. A substrate is provided, wherein an active region and a shallow trench isolation structure adjacent to the active region are formed in the substrate.

[0036] S103. A contact hole is formed on the substrate, the bottom of the contact hole exposing at least a portion of the active region and at least a portion of the shallow trench isolation structure.

[0037] refer to Figure 2 In this embodiment, the substrate 10 includes active regions 12 and shallow trench isolation (STI) structures 13. The shallow trench isolation structures 13 isolate the spaced-apart active regions 12 within the substrate 10. Specifically, isolation trenches are formed within the substrate 10, and shallow trench isolation structures 13 are formed within these isolation trenches to prevent current leakage between adjacent semiconductor device components. The shallow trench isolation structures 13 are made of insulating materials, including any one or any combination of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The active region 12 is made of a semiconductor material. The semiconductor material can be silicon, or it can include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as one or any combination of silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide phosphide (GaInAsP).

[0038] Specifically, a dry etching process is used to etch away part of the structure of the active region 12 and part of the structure of the shallow trench isolation structure 13 to form a contact hole 11 on the substrate 10. The bottom of the contact hole 11 exposes at least part of the active region 12 and at least part of the shallow trench isolation structure 13.

[0039] S105. A conductive plug is formed in the contact hole, and the bottom of the conductive plug is electrically connected to the active area.

[0040] Continue reading Figure 2 The conductive plug 70 is formed in the contact hole 11, and the bottom of the conductive plug 70 is electrically connected to the active region 12.

[0041] In the step of forming the conductive plug 70, a bit line structure 20 is also formed, such as Figure 2 As shown, the bit line structure 20 is located on the conductive plug 70. The bit line 20 includes a barrier layer 21, a conductive layer 22, and a dielectric layer 23. Specifically, a barrier material layer, a conductive material layer, a dielectric material layer, and a mask layer (not shown) are stacked on a substrate 10 where the contact hole 11 is formed. The mask layer is patterned, and the barrier material layer, conductive material layer, and dielectric material layer are sequentially etched using the patterned mask layer as a mask to form the barrier layer 21, conductive layer 22, and dielectric layer 23, thus obtaining the bit line 20. Figure 2 As shown. Bit line 20 achieves electrical connection with the corresponding active region 12 through conductive plug 70.

[0042] In some embodiments, the conductive plug 70 is made of doped polycrystalline silicon, the barrier layer 21 is made of any one or a combination of titanium nitride (TiN), silicon titanium nitride (SiTiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN), the conductive layer 22 is made of any one or a combination of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co), and the dielectric layer 23 is made of any one or a combination of silicon nitride (SiN) or silicon oxynitride (SiON). Exemplarily, the conductive plug 70 comprises polycrystalline silicon, the barrier layer 21 comprises titanium nitride, the conductive layer 22 comprises tungsten, and the dielectric layer 23 comprises silicon nitride.

[0043] S107. A first isolation structure is formed, wherein the first isolation structure fills the contact hole and is in direct contact with the conductive plug; wherein the first isolation structure includes a first stacked structure.

[0044] Specifically, the first isolation structure fills the contact hole 11 and directly contacts the conductive plug 70. Furthermore, the first isolation structure includes a first stacked structure with only one Nitride / Oxide interface. This reduction in the number of interfaces also reduces the impact of interface charge on the electric field distribution in the active region 12. As a protective layer, the first isolation structure isolates the contact plug 70 from the adjacent active region 12, effectively reducing leakage current between the contact plug 70 and subsequently formed node contact plugs.

[0045] In some embodiments, the step of forming the first isolation structure further includes:

[0046] S117. An initial first oxide layer is formed, the initial first oxide layer covering the surface of the bit line structure, the sidewall of the conductive plug, the inner wall of the contact hole, and the surface of the substrate.

[0047] refer to Figure 3 An initial first oxide layer 30 is formed, which covers the surface of the bit line structure 20, the sidewalls of the conductive plug 70, the inner wall of the contact hole 11, and the surface of the substrate 10. The initial first oxide layer 30 covers the surface of the bit line structure 20, that is, it covers the exposed surfaces of the barrier layer 21, the conductive layer 22, and the dielectric layer 23. Figure 2 As shown, the contact hole 11 also exposes a portion of the isolation structure 13 adjacent to the exposed portion of the active region 12, such that when the initial first oxide layer 30 is formed to cover the inner wall of the contact hole 11, the initial first oxide layer 30 also contacts the exposed portion of the isolation structure 13. Exemplarily, the material of the initial first oxide layer 30 includes silicon oxide.

[0048] In some embodiments, the formation process of the initial first oxide layer 30 includes an atomic layer deposition (ALD) process. The ALD process utilizes its advantages of high step coverage, fast deposition rate, and low deposition time to obtain a high-quality thin film layer, thereby obtaining a high-quality initial first oxide layer 30.

[0049] S127. Form an initial insulating layer, which covers the surface of the initial first oxide layer and fills the contact hole.

[0050] S137. Remove part of the initial insulating layer, and the remaining initial insulating layer constitutes an insulating layer. The insulating layer and the initial first oxide layer in contact with the insulating layer constitute a first isolation structure.

[0051] refer to Figures 4-5 An initial insulating layer 40 is deposited on the surface of the initial first oxide layer 30. The deposition process of the initial insulating layer 40 includes one of atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The initial insulating layer 40 fills the contact hole 11.

[0052] Continue reading Figures 4-5By removing a portion of the initial insulating layer 40, specifically the initial insulating layer 40 on the initial first oxide layer 30 outside the contact hole 11, the initial insulating layer 40 remaining in the contact hole 11 constitutes an insulating layer 41. The insulating layer 41 and the initial first oxide layer 30 in contact with the insulating layer 41 constitute a first isolation structure. The first isolation structure includes a first stacked structure with only one Nitride / Oxide interface. Compared to the conventional NON (Nitride-Oxide-Nitride) structure, the number of interfaces is reduced, thereby reducing the electric field distribution of interface charge in the active region of the substrate, and consequently reducing GIDL leakage.

[0053] For example, the material of the insulating layer 41 is different from the material of the initial first oxide layer 30. For instance, the material of the insulating layer 41 includes silicon nitride, and the material of the initial first oxide layer 30 includes silicon oxide. Of course, the materials of the insulating layer 41 and the initial first oxide layer 30 can also be formed from other different materials, which is not limited in this disclosure.

[0054] In some embodiments, after the first isolation structure is formed, a second isolation structure is also formed on the sidewall of the bit line structure 20, the second isolation structure including a second stacked structure.

[0055] The second isolation structure is formed on the sidewall of the bit line structure 20, which protects the bit line structure 20 and isolates adjacent bit line structures 20. At the same time, it can also reduce the parasitic capacitance between the bit line structure 20 and the subsequently formed node contact plug.

[0056] refer to Figures 6-8 The steps for forming the second layered structure include:

[0057] An initial second oxide layer 50 is formed, which covers the partially exposed surfaces of the initial first oxide layer 30 and the insulating layer 41;

[0058] A portion of the initial second oxide layer 50 and a portion of the initial first oxide layer 30 are removed to obtain an oxide layer, the oxide layer comprising a first oxide layer 31 and a second oxide layer 51 located on the sidewall of the bit line structure, wherein the thickness of the second oxide layer 51 is greater than the thickness of the first oxide layer 31.

[0059] A nitride layer 60 is formed to obtain a second stacked structure including the oxide layer and the nitride layer 60.

[0060] The deposition process for forming the initial second oxide layer 50 includes one of atomic layer deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition. An oxide layer is obtained by etching away a portion of the initial second oxide layer 50 and a portion of the initial first oxide layer 30, with the thickness of the second oxide layer 51 being greater than the thickness of the first oxide layer 31. Exemplarily, the oxide layer is made of silicon oxide, and the nitride layer 60 is made of silicon nitride, such that the dielectric constant of the oxide layer is less than that of the nitride layer 60. This reduces parasitic capacitance while protecting the bit line structure 20, thus protecting the performance of the semiconductor structure. In some embodiments, annealing is performed before removing a portion of the initial insulating layer.

[0061] As described above, the semiconductor structure obtained by the above semiconductor structure fabrication method contains a Nitride / Oxide interface. This interface contains defects or dangling bonds, including vacancies, interstitial atoms, dislocations, grain boundaries, and phase boundaries. These defects or dangling bonds typically trap charges. During the subsequent formation of node contact plugs (not shown in the figure), these charges alter the electric field near the node contact plugs, thereby increasing GIDL leakage current. Therefore, after forming the initial first oxide layer 30 and the initial insulating layer 40, annealing is performed to neutralize the charges at the interface, reducing the impact on the electric field near the node contact plugs and also reducing the impact on the electric field distribution in the active region of the substrate, thus reducing the formation of GIDL leakage current.

[0062] In some embodiments, annealing is performed, including:

[0063] The annealing process lasts for 1-2 hours and is carried out at a temperature of 400℃-550℃.

[0064] The semiconductor structure in the process is annealed at 400℃-550℃. It is understood that in some embodiments, the annealing temperature can be set to 400℃. In some embodiments, the annealing temperature can be set to 500℃. In still other embodiments, the annealing temperature can be set to 550℃. It should be understood that in the semiconductor fabrication process of this disclosure, the annealing temperature value can be configured as needed, including but not limited to the temperature values ​​listed above. The duration of the annealing treatment is 1h-2h. It is understood that in some embodiments, the duration of the annealing treatment is 1h. In some embodiments, the duration of the annealing treatment is 1.5h. In still other embodiments, the duration of the annealing treatment is 2h. It should be understood that in the semiconductor fabrication process of this disclosure, the duration of the annealing treatment can be configured as needed, including but not limited to the time values ​​listed above.

[0065] In this embodiment of the disclosure, the annealing temperature for annealing the semiconductor structure being fabricated is controlled within the range of 400°C to 550°C, and the annealing duration is within the range of 1 hour to 2 hours. This neutralizes the charge present at the interface in the semiconductor structure obtained by the above semiconductor structure fabrication method, reduces the influence on the electric field near the subsequently formed node contact plug (not shown in the figure), and also reduces the influence on the electric field distribution in the active region of the substrate, thereby reducing the formation of GIDL leakage.

[0066] In some embodiments, removing a portion of the initial insulating layer 40 includes:

[0067] The initial insulating layer 40 is partially removed by cleaning with hot phosphoric acid cleaning solution to form the insulating layer 41.

[0068] In this embodiment, a portion of the initial insulating layer 40 is removed using hot phosphoric acid etching. Specifically, the initial insulating layer 40 on the initial first oxide layer 30 outside the contact hole 11 is removed using hot phosphoric acid etching. The etching rate of the initial insulating layer 40 using the hot phosphoric acid cleaning solution is greater than the etching rate of the initial first oxide layer 30. For example, the initial insulating layer 40 is silicon nitride, and the initial first oxide layer 30 is silicon oxide. The hot phosphoric acid cleaning solution reacts only with silicon nitride and not with silicon oxide, ensuring that when removing the initial insulating layer 40 on the initial first oxide layer 30 outside the bit line contact hole 11, the initial first oxide layer 30 protects the bit line structure 20 and the substrate 10.

[0069] In this embodiment of the present disclosure, the first stacked structure includes an insulating layer 41, the top of which is higher than the top of the substrate 10 and smaller than the top of the conductive plug 70.

[0070] See Figure 5 A portion of the initial insulating layer 40 is removed using thermal phosphoric acid etching, forming an insulating layer 41 whose top is higher than the top of the substrate 10 but lower than the top of the conductive plug 70. The top of the insulating layer 41 is higher than the top of the substrate 10, ensuring that the first isolation structure on the sidewall of the conductive plug 70 has only one Nitride / Oxide interface. Annealing neutralizes the charge at the interface, reducing the impact on the electric field near the node contact plug (not shown) and also reducing the impact on the electric field near the conductive plug 70. Furthermore, the top of the insulating layer 41 is lower than the top of the conductive plug 70, meaning the top of the insulating layer 41 is lower than the bottom of the conductive layer 22. This allows the sidewall of the conductive layer 22 to form a second isolation structure, and the thickness of the oxide layer in the second isolation structure is increased, reducing the parasitic capacitance between the conductive layer 22 and the subsequently formed node contact plug. This ensures the performance of the semiconductor structure.

[0071] According to a second aspect of the present disclosure, a semiconductor structure is provided, with reference to... Figure 8 The semiconductor structure includes a substrate 10, an active region 12 located in the substrate 10, and a shallow trench isolation structure 13 adjacent to the active region 12; a contact hole 11 located in the substrate 10, with the bottom of the contact hole 11 exposing at least a portion of the active region 12 and at least a portion of the shallow trench isolation structure 13; a conductive plug 70 located in the contact hole 11, with the bottom of the conductive plug 70 electrically connected to the active region 12; and a first isolation structure filling the contact hole 11 and directly contacting the conductive plug 70; wherein the first isolation structure includes a first stacked structure.

[0072] In this embodiment of the present disclosure, the first stacked structure formed in the contact hole 11 has only one Nitride / Oxide interface. Accordingly, the reduction of the Nitride / Oxide interface, and the use of the annealing process, will reduce the defects at the Nitride / Oxide interface, neutralize the charge at the interface, thereby reducing the impact on the electric field distribution in the active region of the substrate, and thus reducing the GIDL leakage phenomenon.

[0073] In some embodiments, the active region 12 is made of a semiconductor material. The semiconductor material may be silicon, or it may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0074] Continue to refer to Figure 8 The semiconductor structure further includes a bit line structure 20 located on the conductive plug 70; a second isolation structure located on the sidewall of the bit line structure 20; and the second isolation structure includes a second stacked structure.

[0075] Bitline structure 20 includes a barrier layer 21, a conductive layer 22, and a dielectric layer 23. The barrier layer 21 is made of any one or a combination of titanium nitride (TiN), silicon titanium nitride (SiTiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The conductive layer 22 is made of any one or a combination of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co). The dielectric layer 23 is made of any one or a combination of silicon nitride (SiN) or silicon oxynitride (SiON). For example, the barrier layer 21 may include titanium nitride, the conductive layer 22 may include tungsten, and the dielectric layer 23 may include silicon nitride.

[0076] In some embodiments, the second stacked structure includes an oxide layer-nitride layer structure. The second isolation structure of the oxide layer-nitride layer structure has a nitride / oxide interface, which protects the bit line structure 20 while effectively reducing the parasitic capacitance between the bit line structure 20 and the adjacent subsequently formed node contact plug.

[0077] Continue reading Figure 8 The oxide layer includes a first oxide layer 31 and a second oxide layer 51, wherein the thickness of the second oxide layer 51 is greater than the thickness of the first oxide layer 31. In this embodiment, the second oxide layer 51 and the first oxide layer 31 are located together between the conductive layer 22 and the subsequently formed dielectric contact plug (not shown in the figure). Since the dielectric constants of the second oxide layer 51 and the first oxide layer 31 are less than the dielectric constant of the nitride layer 60, by making the thickness of the second oxide layer 51 greater than the thickness of the first oxide layer 31, the leakage current between the conductive layer 22 and the dielectric contact plug is effectively reduced or prevented, thereby improving the performance of the semiconductor structure.

[0078] In some embodiments of this disclosure, the top of the conductive plug 70 is higher than the top of the substrate 10. See also Figure 8 The bit line structure 20 is located on the conductive plug 70, wherein the bit line structure 20 includes a conductive layer 22. The top of the conductive plug 70 is higher than the top of the substrate 10, so that the bottom of the conductive layer 22 is higher than the top of the substrate 10, so that the conductive layer 22 is far away from the devices in the active region 12, effectively reducing the generation of leakage current between the conductive layer 22 and the devices in the active region 12, and ensuring the performance of the semiconductor structure.

[0079] In some embodiments of this disclosure, the first stacked structure includes an insulating layer 41, the top of which is higher than the top of the substrate 10 and smaller than the top of the conductive plug 70.

[0080] See Figure 8The first stacked structure includes an insulating layer 41, and the insulating layer 41 and an initial first oxide layer 30 in contact with the insulating layer 41 constitute a first isolation structure. The top of the insulating layer 41 is higher than the top of the substrate 10, so that the first isolation structure located on the sidewall of the conductive plug 70 has only one Nitride / Oxide interface. Annealing neutralizes the charge at the interface, reducing the impact on the electric field near the node contact plug (not shown) and also reducing the impact on the electric field near the conductive plug 70. Furthermore, the top of the insulating layer 41 is lower than the top of the conductive plug 70, i.e., the top of the insulating layer 41 is lower than the bottom of the conductive layer 22, so that the sidewall of the conductive layer 22 forms a second isolation structure. The thickness of the oxide layer in the second isolation structure is increased, reducing the parasitic capacitance between the conductive layer 22 and the subsequently formed node contact plug. This ensures the performance of the semiconductor structure.

[0081] In some embodiments of this disclosure, the top width of the insulating layer 41 is greater than the bottom width of the second oxide layer 51.

[0082] See also Figure 8 The sidewall of the bit line structure 20 is formed with a second isolation structure, which in turn includes a second stacked structure of oxide layer-nitride layer. The top width of the insulating layer 41 is greater than the bottom width of the second oxide layer 51. By controlling the thickness of the second oxide layer 51, the overall thickness of the second isolation structure is not too large, leaving enough space for subsequent formation of node contact plugs.

[0083] The semiconductor structure manufactured according to the embodiments described above can be applied to the fabrication of various integrated circuits (ICs). The integrated circuits according to this disclosure are, for example, memory circuits, such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or read-only memory (ROM), etc. The integrated circuits according to this disclosure can also be logic devices, such as programmable logic arrays (PLAs), application-specific integrated circuits (ASICs), integrated DRAM logic integrated circuits (buried DRAM), radio frequency circuits, or any other circuit devices. The IC chips according to this disclosure can be used in, for example, user electronic products, such as personal computers, portable computers, game consoles, cellular phones, personal digital assistants, cameras, digital cameras, mobile phones, and various other electronic products.

[0084] According to a third aspect of the present disclosure, a memory is provided, including the semiconductor structure described above.

[0085] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided in which an active region is formed and a shallow trench isolation structure adjacent to the active region is formed; A contact hole is formed on the substrate, the bottom of the contact hole exposing at least a portion of the active region and at least a portion of the shallow trench isolation structure; A conductive plug and a bit line structure located on the conductive plug are formed in the contact hole, and the bottom of the conductive plug is electrically connected to the active region. A first isolation structure is formed, which fills the contact hole and directly contacts the conductive plug; wherein, the first isolation structure includes a first stacked structure; Annealing is performed to form a second isolation structure, which is located on the sidewall of the bit line structure; wherein, the second isolation structure includes a second stacked structure; the second stacked structure includes an oxide layer and a nitride layer structure, wherein the oxide layer includes a first oxide layer and a second oxide layer located on the sidewall of the bit line structure, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The step of forming the first isolation structure includes: An initial first oxide layer is formed, which covers the surface of the bit line structure, the sidewall of the conductive plug, the inner wall of the contact hole, and the surface of the substrate; An initial insulating layer is formed, which covers the surface of the initial first oxide layer and fills the contact hole; A portion of the initial insulating layer is removed, and the remaining initial insulating layer constitutes an insulating layer. The insulating layer and the initial first oxide layer in contact with the insulating layer constitute a first isolation structure.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The step of forming the second stacked structure includes: An initial second oxide layer is formed, which covers the surface of the partially exposed initial first oxide layer and insulating layer; By removing a portion of the initial second oxide layer and a portion of the initial first oxide layer, an oxide layer is obtained; A nitride layer is formed to obtain a second stacked structure comprising the oxide layer and the nitride layer.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The annealing process is performed before removing part of the initial insulating layer.

5. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Removing part of the initial insulating layer includes: A portion of the initial insulating layer is removed by thermal phosphoric acid etching to form the insulating layer.

6. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The annealing process lasts for 1-2 hours and is performed at a temperature of 400°C-550°C.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first stacked structure includes an insulating layer, the top of which is higher than the top of the substrate and lower than the top of the conductive plug.

8. A semiconductor structure, characterized in that, include: A substrate, and an active region located in the substrate and a shallow trench isolation structure adjacent to the active region; A contact hole is located in the substrate, and the bottom of the contact hole exposes at least a portion of the active region and at least a portion of the shallow trench isolation structure; A conductive plug is located in the contact hole and its bottom is electrically connected to the active region; a first isolation structure fills the contact hole and is in direct contact with the conductive plug; wherein the first isolation structure includes a first stacked structure; The bit line structure is located on the conductive plug; A second isolation structure is located on the sidewall of the bit line structure; wherein the second isolation structure includes a second stacked structure; the second stacked structure includes an oxide layer and a nitride layer structure, the oxide layer includes a first oxide layer and a second oxide layer located on the sidewall of the bit line structure, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer.

9. The semiconductor structure according to claim 8, characterized in that, The top of the conductive plug is higher than the top of the substrate.

10. The semiconductor structure according to claim 8, characterized in that, The first stacked structure includes an insulating layer, the top of which is higher than the top of the substrate and lower than the top of the conductive plug.

11. The semiconductor structure according to claim 10, characterized in that, The top width of the insulating layer is greater than the bottom width of the second oxide layer.

12. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 10-11.

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