An in-plane ultra-high density ferroelectric memory array and its fabrication method

Abstract

This invention belongs to the field of storage technology, specifically an in-plane ultra-high density ferroelectric memory array and its fabrication method. The in-plane close-packed ferroelectric memory cells and electrodes of this invention are arranged periodically. The electrodes are led out through three-dimensional interconnected conductive pillars. The three-dimensional interconnected word lines, including the first and second word line layers outside the plane, are connected to the first and third conductive pillar arrays, respectively. The three-dimensional interconnected bit lines, including the first and second bit line layers outside the plane, are connected to the second and fourth conductive pillar arrays, respectively. Parallel electrodes are distributed within the word line and bit line layers, perpendicular to each other, forming a crossbar array. The in-plane intersection points are ferroelectric memory cells located in the gap region between adjacent electrodes, enabling high-density data reading and writing. The in-plane close-packed ferroelectric memory array of this invention can improve storage density, reaching up to 2F. 2 F represents the characteristic process dimension of semiconductor manufacturing, which is suitable for manufacturing ultra-high density memory devices and is simple and low-cost to prepare.

Description

Technical Field

[0001] This invention belongs to the field of storage technology, specifically relating to an in-plane ultra-high density ferroelectric memory array and its fabrication method. Background Technology

[0002] Since Tarui and Moll first proposed the concept of ferroelectric memory in 1963, traditional ferroelectric memories are mainly divided into two categories: one is a transistor-capacitor interconnect structure (1T1C), and the other is a field-effect transistor (FeFET) with ferroelectric material as the gate dielectric layer. Both rely on the two polarization states of the ferroelectric material to store information. In recent years, Jiang Anquan et al., based on their research on two-dimensional ferroelectric domain walls, invented a ferroelectric memory based on erasable and rewritable conductive domain walls (Chinese patent applications CN201510036526.X, CN201510036586.1, CN201610098138.9 and US Patent Publication No. 9685216B2). The domain wall is the interface between electric domains with different polarization directions in the ferroelectric material, and has optical, electrical, and magnetic physical properties that are completely different from the bulk material. Due to the changes in band structure at the domain wall, its resistance is much smaller than that of the ferroelectric insulating block. By applying an electric field between electrodes, the polarization direction of the domains between the electrodes can be controlled to form a parallel or antiparallel domain structure with the surrounding non-reversed domains, thereby writing or erasing the conductive domain walls. The written domain walls are retained even after the external field is removed, thus achieving non-volatile storage of the written information. At the same time, a switching domain wall current is generated to achieve non-destructive current reading of the information.

[0003] Based on this ferroelectric memory with domain wall conductivity and in-plane read / write capability, Jiang Anquan et al. later invented a 4F... 2 A close-packed in-plane read / write ferroelectric memory array and its manufacturing method (Chinese Patent Application No. CN202011234815.8) describes a memory array comprising a word line layer located within the plane of the memory structure unit, and a first bit line layer and a second bit line layer disposed outside the word line layer. The word line layer has multiple parallel line electrodes arranged alternately along a first direction, with ferroelectric memory cells and bit line arrays distributed between the parallel lines. The bit line array is connected to the out-of-plane first bit line array and second bit line array respectively via conductive pillars. The first bit line layer is disposed above the first conductive pillar array, and the second bit line layer is disposed above or below the second conductive pillar array. Both the first bit line layer and the second bit line layer consist of bit lines arranged along a second direction, which is perpendicular to the first direction. The intersection of the word line and the bit line represents the selected in-plane ferroelectric memory cell, allowing for information reading and writing. If the feature size of the process is F, then the minimum size of this in-plane read / write ferroelectric memory is 4F. 2 This achieves high-density in-plane information storage, as illustrated in the diagram below. Figure 1As shown in the diagram, in this structure, the memory devices are all located at the intersection of the conductive pillar bit line array and the word line. The gap regions between them are divided into a first gap group and a second gap group, which are arranged alternately and filled with ferroelectric dielectric. Not all of these gaps can be used as memory devices. Furthermore, the polarization direction of the ferroelectric substrate in this structure is parallel to the electric field direction, meaning that the read and write directions can only follow the second direction of the bit line arrangement in the bit line layer. Therefore, the storage density of this structure can be further improved. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide an in-plane ultra-high density ferroelectric memory array and its fabrication method, wherein the in-plane close-packed ferroelectric memory array and electrodes are periodically arranged, and all electrodes are led out through three-dimensional interconnected conductive pillars. This in-plane close-packed ferroelectric memory array and its three-dimensional interconnection structure can improve the in-plane storage density, reaching up to 2F. 2 It can be used to manufacture ultra-high density storage devices, and its preparation is simple and low cost.

[0005] The in-plane ultra-high density ferroelectric memory array provided by the present invention comprises: a ferroelectric material substrate, two word line layers, two bit line layers, four sets of conductive pillar arrays, four sets of conductive plugs, and four sets of ferroelectric memory cells.

[0006] The two word line layers are the first word line layer and the second word line layer; the two bit line layers are the first bit line layer and the second bit line layer; the four sets of conductive pillar arrays are the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array; the four sets of conductive plugs are the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug; and the four sets of ferroelectric memory cells are the first memory device, the second memory device, the third memory device, and the fourth memory device.

[0007] The in-plane storage cell is composed of ferroelectric storage cells with closely packed conductive plugs in each row and column and the gap regions between them. The direction of the close packing of the conductive plugs in each row and column is not parallel to the direction of the spontaneous polarization of the ferroelectric storage material substrate projected in the plane. That is, the angle between the direction of the ferroelectric polarization of the substrate projected in the plane and the direction of each row and column of the conductive plug is greater than 0 degrees and less than 90 degrees.

[0008] The conductive plugs are arranged in a periodic manner in the plane according to the order of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, and every four consecutive conductive plugs constitute an arrangement cycle.

[0009] A first word line layer is disposed above a first conductive pillar array, the word line layer having a plurality of word lines arranged along a first direction; the first conductive pillars are connected to a first conductive plug in the plane;

[0010] The first bit layer is disposed above or below the second conductive pillar array and has a plurality of bit lines arranged along the second direction, the number of which is a multiple of 4. The second direction is perpendicular to the first direction. The second conductive pillar is connected to the second conductive plug in the plane. The gap region between the second conductive plug and the adjacent first conductive plug is provided with a first storage device.

[0011] The second word line layer is disposed above or below the third conductive pillar array and has multiple word lines arranged along the first direction. The third conductive pillar is connected to the third conductive plug in the plane, and a second storage device is disposed in the gap area between the third conductive plug and the adjacent second conductive plug.

[0012] The second bit line layer is disposed above or below the fourth conductive pillar array and has multiple bit lines arranged along the second direction. The fourth conductive pillar is connected to the fourth conductive plug in the plane. A third storage device is disposed in the gap region between the fourth conductive plug and the adjacent third conductive plug. A fourth storage device is disposed in the gap region between the fourth conductive plug and the adjacent first conductive plug.

[0013] The read / write signal is biased in the memory cell region between a selected word line and bit line intersection point in the first word line layer, the second word line layer, the first bit line layer, and the second bit line layer.

[0014] The ferroelectric memory array of the present invention includes a plurality of repeating conductive plugs, which are multiple grooves etched on the surface of the ferroelectric memory material, and the grooves are filled with conductive medium as electrodes, and each conductive plug is connected to a corresponding conductive post.

[0015] In this invention, all conductive plugs are filled with a conductive medium, and the contact layer between the conductive medium and the ferroelectric material has a low resistance.

[0016] In this invention, the shape of the conductive plug is generally, but not limited to, a cube, and the conductive post can be a cuboid or a cylinder.

[0017] In this invention, there is a certain angle between the row and column where the conductive plug is located and the initial polarization of the ferroelectric storage material in the in-plane projection direction. The angle range is greater than 0 degrees and less than 90 degrees, preferably 45°.

[0018] In this invention, the gap size between the conductive plugs or the storage cell size is greater than or equal to 1 nm and less than or equal to 500 nm, and preferably the side length of the conductive plug is greater than the gap size.

[0019] In this invention, the first, second, third, and fourth memory devices are made of the same material, are located in the same layer, and can achieve a maximum of 2F. 2 The material is densely packed and makes good contact with adjacent conductive plugs, resulting in low contact resistance.

[0020] In this invention, the ferroelectric storage medium material of the storage device is selected from lithium niobate, lithium tantalate, bismuth ferrite, barium titanate, lead zirconate titanate, hafnium oxide thin film material, single crystal material, or a combination thereof. By applying a write voltage greater than the coercive voltage of domain reversal between the selected word lines or bit lines, local reversal of ferroelectric domains located between adjacent electrodes is achieved, forming a parallel or antiparallel domain structure with the non-reversed reference domains at the bottom or periphery. This allows for the non-volatile storage of logic "0" or "1" information. The domain walls have a lower resistance than the ferroelectric storage medium material, and erasure and writing are possible as the parallel or antiparallel domain structure is formed. When a read voltage less than the coercive voltage of domain reversal is applied, a large switching current is generated, which can identify the written parallel or antiparallel domain information.

[0021] In this invention, the memory array further includes an insulating layer comprising silicon oxide, silicon nitride, and aluminum oxide, wherein the insulating layer is disposed in the remaining space between the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array.

[0022] In this invention, all or part of the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array are distributed above or below the ferroelectric storage medium plane.

[0023] This invention provides a method for fabricating the in-plane read / write ferroelectric memory array, comprising the following steps:

[0024] When the first word line layer is positioned above the first conductive pillar array, the first bit line layer is positioned above the second conductive pillar array, the second word line layer is positioned above the third conductive pillar array, and the second bit line layer is positioned above the fourth conductive pillar array, the specific steps are as follows:

[0025] Repeated conductive plug grooves are formed on a ferroelectric single-crystal substrate by mask etching. Multiple exposures and other methods can be used to make the groove size larger than the groove spacing, and the grooves are filled with electrode material.

[0026] The filling of electrode material in the groove can be achieved using thin film growth, electroplating and chemical mechanical polishing techniques, and then an insulating thin film layer is deposited on the surface of the above ferroelectric dielectric.

[0027] A first conductive plug contact hole is formed, and a first layer of word line electrodes is configured;

[0028] A flat insulating layer is formed covering the surface of the first letter line layer using thin film growth and chemical mechanical polishing techniques;

[0029] A second conductive plug contact hole is formed, and a first layer bit line electrode is configured;

[0030] A flat insulating layer covering the surface of the first line layer is formed using thin film growth and chemical mechanical polishing techniques.

[0031] A third conductive plug contact hole is formed, and a second layer of word line electrodes is configured;

[0032] A flat insulating layer covering the surface of the second letter line layer is formed using thin film growth and chemical mechanical polishing techniques.

[0033] A fourth conductive plug contact hole is formed, and a second layer bit line electrode is configured.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] Unlike the existing 4F 2 The present invention relates to a close-packed ferroelectric memory array. The in-plane close-packed read / write ferroelectric memory array and electrodes are arranged periodically, with all electrodes led out through three-dimensional interconnected conductive pillars. Furthermore, the row and column packing directions of the in-plane electrodes are not parallel to the in-plane projection direction of the spontaneous polarization of the ferroelectric memory material substrate; that is, the angle between the in-plane projection direction of the substrate ferroelectric polarization and the direction of each row and column of the conductive plug is greater than 0 degrees and less than 90 degrees, preferably 45°. This angle allows the electric field between any two adjacent electrodes to generate a component in the polarization direction, enabling the reading and writing of domains between any two adjacent electrodes, and increasing the storage density to 2F. 2 . Attached Figure Description

[0036] The above and other objects and advantages of the present invention will become more fully clear from the following detailed description taken in conjunction with the accompanying drawings, wherein the same or similar elements are indicated by the same reference numerals.

[0037] Figure 1 It is a 4F that is currently available. 2 A schematic diagram of the structure of a close-packed ferroelectric memory array.

[0038] Figure 2 This is a three-dimensional interconnected stereoscopic diagram of an in-plane ultra-high density ferroelectric memory array according to the first embodiment of the present invention.

[0039] Figure 3 This is a top view schematic diagram of an in-plane ultra-high density ferroelectric memory array according to the first embodiment of the present invention, wherein (a) is an in-plane memory cell, and (b), (c), (d), and (e) are the first word line layer, the first bit line layer, the second word line layer, and the second bit line layer, respectively.

[0040] Figure 4 This is the first embodiment of the present invention. Figure 3(e) Schematic cross-section of an in-plane ultra-high density ferroelectric memory array along line S1-S1'.

[0041] Figure 5 This is the first embodiment of the present invention. Figure 4 A top view (a) and a left view (b) of an in-plane read / write storage cell within the dashed box N.

[0042] Figure 6 This is the first embodiment of the present invention. Figure 5 The diagram shows the working principle of the in-plane storage cell, where (a) is the top view and (b) is the side view. Figure 6 (a) is a sectional view of line S2-S2'.

[0043] Figure 7 a- Figure 7 g is Figure 2 A schematic diagram of the fabrication process of an in-plane ultra-high density ferroelectric memory array.

[0044] Figure 8 The image shown is an in-plane scanning electron microscope (SEM) image of a four-bit memory device structure with four electrodes.

[0045] Figure 9 This is an in-plane piezoelectric microscopy (PFM) domain imaging image of the four domain walls of a four-bit memory device with four terminal electrodes during writing (a) and erasing (b).

[0046] Figure 10 for Figure 9 The diagram shows the current-voltage (IV) test results for a four-bit memory device. Detailed Implementation

[0047] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments depicted herein are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the method proposed in this invention without inventive effort are within the scope of protection of this invention.

[0048] In the accompanying drawings, the thickness or spacing of layers and regions has been exaggerated for clarity, and the dimensional proportions between the parts shown in the drawings do not reflect the actual dimensional proportions.

[0049] In the following embodiments, for clarity of description, the domain direction or polarization direction is given by way of example; however, it should be understood that the domain direction or polarization direction of the ferroelectric memory is not limited to the direction shown in the embodiments illustrated.

[0050] Figure 2The diagram shown is a three-dimensional schematic representation of an in-plane ultra-high density ferroelectric memory array and its interconnection according to a first embodiment of the present invention. Figure 3 The diagram shown is a top view of a high-density memory array for in-plane read / write according to a first embodiment of the present invention. Figure 4 As shown Figure 3 (e) A cross-sectional view of the in-plane read / write memory array along line S1-S1'. (See reference) Figure 2 , Figure 3 and Figure 4 As can be seen, the memory array structure of this embodiment mainly includes a ferroelectric material substrate 00, two word line layers WL1 and WL2, two bit line layers BL1 and BL2, four sets of conductive pillars 11, 22, 33, and 44, four sets of conductive plugs 10, 20, 30, and 40, four sets of memory cell arrays 12, 23, 34, and 41, and an insulating layer 000. For clarity, Figure 3 , Figure 4 Not all word lines, bit lines, and conductive pillars are drawn in the text.

[0051] In this invention, the ferroelectric storage medium material of the storage device is selected from lithium niobate, lithium tantalate, bismuth ferrite, barium titanate, lead zirconate titanate, hafnium oxide thin film material, single crystal material, or a combination thereof.

[0052] There are two word line layers, namely the first word line layer WL1 and the second word line layer WL2, and two bit line layers, namely the first bit line layer BL1 and the second bit line layer BL2. The word line layers and bit line layers are arranged alternately outside the substrate surface, and from the first layer to the fourth layer, they are WL1, BL1, WL2 and BL2 respectively.

[0053] The first word line layer WL1 is located in the first layer and is connected to some of the conductive posts 11. It has multiple word lines WL11, WL12, WL13... arranged sequentially along the first direction. Each first conductive plug 10 has a first conductive post 11 connected to it and is equipped with word lines connected to the conductive post. The conductive plugs adjacent to the first conductive plug 10 are 40 and 20, and a storage unit is provided in the gap area between the adjacent conductive plugs. The gap area between the first conductive plug 10 and the fourth conductive plug 40 is the storage unit 41, and the gap area between the first conductive plug 10 and the second conductive plug 20 is the storage unit 12.

[0054] The first bit line layer BL1 is located in the second layer, connected to some of the conductive posts 22, and has multiple bit lines BL11, BL12, BL13... arranged sequentially along a second direction, which is perpendicular to the first direction. Each second conductive plug 20 has a second conductive post 22 connected to it, and bit lines are configured to connect to the conductive post. The conductive plugs adjacent to the second conductive plug 20 are 10 and 30, and a storage cell is provided in the gap area between adjacent conductive plugs. The gap area between the second conductive plug 20 and the first conductive plug 10 is the storage cell 12, and the gap area between the second conductive plug 20 and the third conductive plug 30 is the storage cell 23.

[0055] The second word line layer WL2 is located in the third layer and is connected to some of the conductive posts 33. It has multiple word lines WL21, WL22, WL23... arranged sequentially along the first direction. Each third conductive plug 30 has a third conductive post 33 connected to it, and word lines are configured to connect to the conductive post. The conductive plugs adjacent to the third conductive plug 30 are 20 and 40, and a storage unit is provided in the gap area between the adjacent conductive plugs. The gap area between the third conductive plug 30 and the second conductive plug 20 is the storage unit 23, and the gap area between the third conductive plug 30 and the fourth conductive plug 40 is the storage unit 34.

[0056] The second bit line layer BL2 is located in the fourth layer and is connected to some of the conductive posts 44. It has multiple bit lines BL21, BL22, BL23... arranged sequentially along the second direction. Each fourth conductive plug 40 has a fourth conductive post 44 connected to it, and bit lines are configured to connect to the conductive post. The conductive plugs adjacent to the fourth conductive plug 40 are 30 and 10, and a storage cell is provided in the gap area between the adjacent conductive plugs. The gap area between the fourth conductive plug 40 and the third conductive plug 30 is the storage cell 34, and the gap area between the fourth conductive plug 40 and the first conductive plug 10 is the storage cell 41.

[0057] The word lines, bit lines, conductive plugs, and conductive posts are made of conductive materials, including but not limited to copper, gold, silver, titanium, chromium, and cobalt. The conductive plugs have good contact with the ferroelectric memory cells.

[0058] The insulating layer 000 is disposed in the remaining space between word line layers WL1 and WL2, bit line layers BL1 and BL2, and conductive pillar arrays 11, 22, 33, and 44, and includes silicon oxide, silicon nitride, and aluminum oxide.

[0059] In this embodiment, Figure 4 The dashed box N represents the storage cell between the conductive plugs connected to the word line WL14 and the bit line BL18. Figure 5 The diagram shows a top view (a) and a cross-sectional view (b) of the storage unit. The working principle of the storage unit is as follows: Figure 6As shown. When a write voltage V greater than the coercivity voltage Vc of the device is applied to word line WL14, some domains inside the device will be reversed. A conductive domain wall 102 is formed between the reversed domain 202 and the unreversed domain 101. At this time, a low-resistance state "1" can be obtained by applying a read voltage (greater than 0V and less than Vc) to WL11. When a write voltage -V less than the coercivity voltage -Vc of the device is applied to bit line BL18 in the opposite direction, the reversed domain returns to its initial state and the conductive domain wall disappears. At this time, a high-resistance state "0" can be obtained by applying a read voltage to WL14.

[0060] In this embodiment, the electrode material selected for the electrode layer and the connecting wire electrode material for filling the contact hole is high temperature resistant and low resistivity, and can be, but is not limited to, one or more of the following materials: TiN, Pt, PtSi, NiSi, TiW, Ta, TaN, Ti, W, Mo, Al, Cu, Cr, Ir, IrO2, SrRuO3, RuO2;

[0061] The fabrication method of the memory array according to the first embodiment will be described below. Figure 7 a- Figure 7 g is a top view schematic diagram of the manufacturing method of a three-dimensional memory array according to the first embodiment of the present invention. For clarity and convenience of explanation, some components are omitted in some of the drawings.

[0062] First, prepare a smooth, flat, and uncontaminated original substrate ferroelectric single crystal wafer or thin film. Spin-coat photoresist onto the surface. Transfer the designed memory cell bump pattern onto the original substrate using pattern transfer techniques such as optical exposure, electron beam exposure, ion beam exposure, or nanoimprint lithography. Grow a hard mask material. Leave the hard mask pattern on the original substrate using a liftoff technique. Etch the ferroelectric single crystal thin film using dry etching or wet etching techniques, leaving the ferroelectric bumps and removing the hard mask material to form the plug groove; see also Figure 7 a and Figure 7 b. Among them Figure 7 In the semiconductor manufacturing process, the side length of the in-plane electrode is equal to the gap size, which is the characteristic process dimension F. To ensure that adjacent electrodes overlap in the polarization direction, it is preferable that the side length of the conductive plug is greater than the gap size. Figure 7 As shown in b. From Figure 7 a to Figure 7 b can be obtained using methods such as multiple exposures. Furthermore, there is a certain angle between the initial polarization of the ferroelectric storage material and the in-plane projection direction of each row and column containing the conductive plug, with the angle ranging from greater than 0 degrees to less than 90 degrees, preferably 45°.

[0063] Then, an electrode thin film is prepared, and a conductive layer is left for the plug portion using a similar method;

[0064] Using thin film growth techniques, such as PECVD (plasma-enhanced chemical vapor deposition), a SiO2 film with a thickness of 50 to 3000 nanometers is grown on the original substrate. CMP (chemical vapor deposition) technology is then used to polish the SiO2 film to the target thickness and ensure a smooth and flat surface. See also... Figure 7 c);

[0065] Optionally, a protective film, such as Si3N4 or photoresist (HSQ), can be grown before growing SiO2.

[0066] Secondly, contact holes are etched at the first conductive plug 10 using a mask, and then the mask is prepared again and filled with electrode material to obtain the first layer of word line electrodes; see [link to documentation]. Figure 7 d;

[0067] repeat Figure 7 The process shown in d can produce the first layer bit line electrode, the second layer word line electrode, and the third layer bit line electrode; see also Figure 7 e, 7f, 7g.

[0068] In this embodiment of the invention, the specific shape of the domain wall formed is not limited to the shape shown in the illustrations of this embodiment.

[0069] In this invention, all or part of the first word line layer WL1, the first bit line layer BL1, the second word line layer WL2, the second bit line layer BL2, the first conductive pillar array 11, the second conductive pillar array 22, the third conductive pillar array 33, and the fourth conductive pillar array 44 may also be distributed below the ferroelectric storage medium plane.

[0070] To verify the feasibility of the close-packed structure proposed in this invention, a memory device with four terminals was designed, the structure of which is as follows: Figure 8 As shown, (a) is a structural diagram and (b) is a SEM image of the actual device. This device consists of four electrodes, A, B, C, and D, embedded in a ferroelectric substrate 00. Applying an appropriate voltage across adjacent electrodes can form flipped domains with a polarization direction opposite to that of the substrate, thus creating domain walls. Applying a reverse voltage can erase these domains. Figure 9 PFM images of writing (a) and erasing (b) the four domain walls for this four-bit device are shown. The IV test curves between each electrode are as follows. Figure 10 As shown, (a), (b), (c), and (d) correspond to the test conditions of electrodes AB, AD, CD, and BC, respectively. This enables four-bit storage. Based on its four-bit storage characteristics, the four-terminal device is densely arranged on a plane to obtain the in-plane ultra-high density ferroelectric memory array proposed in this invention.

[0071] Those skilled in the art should understand that the present invention does not limit the number, spatial position, or order of word line layers, word lines, bit lines, conductive pillars, and conductive plugs.

[0072] In the above description, the use of directional terms and similar terms to describe components of various embodiments indicates directions shown in the drawings or directions that can be understood by those skilled in the art. These directional terms are used for relative description and clarification, and are not intended to limit the orientation of any embodiment to a specific direction or orientation.

[0073] The above examples primarily illustrate the in-plane ultra-high density ferroelectric memory array and its three-dimensional interconnection fabrication method of the present invention. Although only some embodiments of the present invention have been described, those skilled in the art should understand that the present invention can be implemented in many other forms without departing from its spirit and scope. Therefore, the examples and embodiments shown are to be considered illustrative rather than restrictive, and the present invention may cover various modifications and substitutions without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An in-plane ultra-high density ferroelectric memory array, characterized in that, It includes a ferroelectric material substrate, two word line layers, two bit line layers, four sets of conductive pillar arrays, four sets of conductive plugs, and four sets of ferroelectric memory cells; The two word line layers are the first word line layer and the second word line layer; the two bit line layers are the first bit line layer and the second bit line layer; the four sets of conductive pillar arrays are the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array; the four sets of conductive plugs are the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug; and the four sets of ferroelectric memory cells are the first memory device, the second memory device, the third memory device, and the fourth memory device. The in-plane storage cell is composed of ferroelectric storage cells with closely packed conductive plugs in each row and column and the gap regions between them. The direction of the close packing of the conductive plugs in each row and column is not parallel to the direction of the spontaneous polarization of the ferroelectric storage material substrate projected in the plane. That is, the angle between the direction of the ferroelectric polarization of the substrate projected in the plane and the direction of each row and column of the conductive plug is greater than 0 degrees and less than 90 degrees. The conductive plugs are arranged in a periodic manner in the plane according to the order of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, and every four consecutive conductive plugs constitute an arrangement cycle. A first word line layer is disposed above a first conductive pillar array, the word line layer having a plurality of word lines arranged along a first direction; The first conductive post is connected to the first conductive plug in the plane; The first bit layer is disposed above or below the second conductive pillar array and has a plurality of bit lines arranged along a second direction perpendicular to the first direction. The second conductive pillar is connected to a second conductive plug in the plane, and a first storage device is disposed in the gap region between the second conductive plug and the adjacent first conductive plug. The second word line layer is disposed above or below the third conductive pillar array and has multiple word lines arranged along the first direction. The third conductive pillar is connected to the third conductive plug in the plane, and a second storage device is disposed in the gap area between the third conductive plug and the adjacent second conductive plug. The second bit line layer is disposed above or below the fourth conductive pillar array and has multiple bit lines arranged along the second direction. The fourth conductive pillar is connected to the fourth conductive plug in the plane. A third storage device is disposed in the gap region between the fourth conductive plug and the adjacent third conductive plug. A fourth storage device is disposed in the gap region between the fourth conductive plug and the adjacent first conductive plug. The read / write signal is biased in the memory cell region between a selected word line and bit line intersection point in the first word line layer, the second word line layer, the first bit line layer, and the second bit line layer.

2. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, The conductive plug is formed by etching multiple grooves on the surface of a ferroelectric material substrate. The grooves are filled with a conductive medium as an electrode, and the contact resistance between the conductive medium and the ferroelectric material is small.

3. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, The conductive plug is cube-shaped, and the conductive post is cuboid or cylindrical.

4. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, There is a certain angle between the row and column where the conductive plug is located and the initial polarization of the ferroelectric material in the in-plane projection direction, and the angle is 45°.

5. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, The gap size between conductive plugs or the size of the storage cell is greater than or equal to 1 nm and less than or equal to 500 nm, and the side length of the conductive plug is greater than the gap size.

6. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, The first, second, third, and fourth memory devices use the same ferroelectric storage medium material, are located in the same layer, and can achieve a maximum 2F. 2 Dense heap.

7. The in-plane ultra-high density ferroelectric memory array as described in claim 6, characterized in that, The ferroelectric storage medium material of the storage device is selected from lithium niobate, lithium tantalate, bismuth ferrite, barium titanate, lead zirconate titanate, hafnium oxide thin film material, single crystal material, or a combination thereof. By applying a write voltage greater than the coercive voltage of domain reversal between the selected word lines or bit lines, local reversal of ferroelectric domains within the storage cell located between adjacent electrodes is achieved, forming a parallel or antiparallel domain structure with the non-reversed reference domains at the bottom or periphery. This allows for the non-volatile storage of logic "0" or "1" information. The domain walls have a lower resistance than the ferroelectric storage medium material, and non-volatile erasure and writing are possible as the parallel or antiparallel domain structure is formed. When a read voltage less than the coercive voltage of domain reversal is applied, a large switching current is generated, which can identify the written parallel or antiparallel domain logic information.

8. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, It also includes an insulating layer made of one or a combination of silicon oxide, silicon nitride, or aluminum oxide; the insulating layer is disposed in the remaining space between the first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array.

9. The in-plane ultra-high density ferroelectric memory array as described in claim 1, characterized in that, The first word line layer, the first bit line layer, the second word line layer, the second bit line layer, the first conductive pillar array, the second conductive pillar array, the third conductive pillar array, and the fourth conductive pillar array are all or partially distributed above or below the ferroelectric storage medium plane.

10. A method for fabricating an in-plane read / write ferroelectric memory array as described in any one of claims 1-9, characterized in that: When the first word line layer is positioned above the first conductive pillar array, the first bit line layer is positioned above the second conductive pillar array, the second word line layer is positioned above the third conductive pillar array, and the second bit line layer is positioned above the fourth conductive pillar array, the specific steps are as follows: Repeated conductive plug grooves are formed on a ferroelectric material substrate by mask etching, making the groove size larger than the groove spacing; electrode material is filled in the grooves using thin film growth, electroplating and chemical mechanical polishing techniques. Then, an insulating thin film layer is deposited on the ferroelectric dielectric surface; A first conductive plug contact hole is formed, and a first layer of word line electrodes is configured; A flat insulating layer is formed covering the surface of the first letter line layer using thin film growth and chemical mechanical polishing techniques; A second conductive plug contact hole is formed, and a first layer bit line electrode is configured; A flat insulating layer covering the surface of the first line layer is formed using thin film growth and chemical mechanical polishing techniques. A third conductive plug contact hole is formed, and a second layer of word line electrodes is configured; A flat insulating layer is formed covering the surface of the second letter line layer using thin film growth and chemical mechanical polishing techniques; A fourth conductive plug contact hole is formed, and a second layer bit line electrode is configured.

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