A multi-time-scale neural synapse device and a preparation method thereof

Abstract

The application relates to a multi-time-scale neural synapse device and a preparation method thereof, wherein the device structure comprises a substrate, an insulating layer, a back gate, a back dielectric layer, a channel, a source electrode, a drain electrode, a top dielectric layer and a top gate; based on the materials of the back dielectric layer and the top dielectric layer, the back gate and the top gate are selected as LTP modulation gates or STP modulation gates; a reading voltage is applied to the drain electrode, and the resistance value between the source electrode and the drain electrode can be used as the weight value of the synapse. Through the stimulation of a single gate, the device can realize multi-state long-term resistance transition and short-term resistance transition with different relaxation times, and then through the stimulation process of simultaneously encoding the top gate and the back gate, the synapse weight value can be short-term transitioned in different initial states. Compared with the prior art, the application realizes multi-time-scale functions, the long-term resistance can be used as the network weight value, the short-term resistance is used for processing network timing information, accelerating calculation, and is helpful for promoting the development of high-order intelligent chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multi-timescale neural synapse device and its fabrication method. Background Technology

[0002] Inspired by the biological brain, neuromorphic computing offers a low-power, high-efficiency solution to the current computing architecture's "memory wall" and "power wall." Neural synapses, the mediums for signal transmission and processing in the biological brain, possess multi-timescale plasticity. Long-term plasticity (LTP) is fundamental to learning and memory, while short-term plasticity (STP) provides computational capabilities. Achieving tunable, multi-timescale artificial neural synapses using a single device could enable large-scale neuromorphic chips.

[0003] However, current research focuses on single-timescale neural synaptic devices, i.e., only achieving LTP or STP for neural network acceleration or brain-like algorithms. For example, See-On Park et al. disclosed an experimental demonstration of a highly reliable dynamic memristor for artificial neurons and neuromorphic computing (See-On Park et al., Nature Communications, 2022.10.1038 / s41467-022-30539-6.), and Syed Ghazi Sarwat et al. disclosed a phase-change mode transfer synapse for hybrid plasticity neural computing (Syed Ghazi Sarwat et al., Nature Nanotechnology, 2022.DOI:10.1038 / s41565-022-01095-3.). Current artificial neural synaptic devices cannot achieve tunable multi-timescale plasticity through device dynamics; they can only map part of the functions of biological synapses, making it difficult to store weights and process data simultaneously. Synaptic devices with a single timescale are insufficient to correspond to the diverse functions of biological synapses, which is not conducive to the integration and optimization of neuromorphic chips. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art by providing a multi-timescale neural synaptic device and its fabrication method.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A multi-timescale neural synapse device includes a substrate, an insulating layer, a back gate, a back dielectric layer, a channel, a source, a drain, a top dielectric layer, and a top gate;

[0007] The substrate, insulating layer, back gate, back dielectric layer, channel, top dielectric layer and top gate are arranged sequentially from bottom to top, and the source and drain are located on both sides of the channel;

[0008] Based on the materials of the back dielectric layer and the top dielectric layer, the back gate and the top gate are selected as LTP modulation gates or STP modulation gates, respectively.

[0009] The top and back grids are symmetrical structures.

[0010] A read voltage is applied to the drain, and the resistance between the source and drain is used as the weight of the synaptic device;

[0011] By encoding a single gate stimulus, the synaptic device achieves polymorphic long-term resistance transitions and short-term resistance transitions with different relaxation times. By simultaneously encoding the stimulation processes of the top gate and the back gate, the weights of the synaptic device undergo short-term transitions under different initial states.

[0012] Furthermore, if the top dielectric layer is made of a volatile material and the back dielectric layer is made of a non-volatile material, then the top gate is used as the STP modulation gate and the back gate is used as the LTP modulation gate.

[0013] If the back dielectric layer is made of a volatile material and the top dielectric layer is made of a non-volatile material, then the back gate is used as the STP modulation gate and the top gate is used as the LTP modulation gate.

[0014] Furthermore, the gate stimulation includes stimulation voltage, stimulation duration, and number of stimulation pulses.

[0015] Furthermore, the device utilizes a short-time algorithm to calculate the timing data during the storage of weights.

[0016] A method for fabricating a multi-timescale neural synaptic device, used to fabricate the multi-timescale neural synaptic device as described above, includes the following steps:

[0017] An insulating SiO2 layer is formed on a silicon substrate by oxidation.

[0018] A back gate is deposited on the SiO2 insulating layer;

[0019] A back dielectric layer is deposited on the back gate;

[0020] Deposit channels on the back dielectric layer;

[0021] Source and drain electrodes are deposited on both sides of the channel, respectively;

[0022] A top dielectric layer is deposited on the source and drain electrodes;

[0023] A top gate is deposited on the top dielectric layer.

[0024] Furthermore, the thickness of the back gate is 10nm to 200nm, and the bottom gate is a back gate made of one or more conductive materials such as TiN, Pd, Pt, W, Cu, Ag or Au.

[0025] Furthermore, the thickness of the back dielectric layer is 3nm to 200nm, and the thickness of the top dielectric layer is 3nm to 200nm;

[0026] The back dielectric layer and the top dielectric layer are dielectric layers made of materials with electrically tunable non-volatile built-in electric field characteristics or materials with electrically tunable volatile capacitance characteristics.

[0027] Furthermore, the channel thickness is 2nm to 50nm, and the channel is made of a material with semiconductor properties.

[0028] Furthermore, the thickness of the source and drain electrodes is 2nm to 50nm, and the source and drain electrodes are made of one or more conductive materials such as TiN, Pd, Pt, W, Cu, Ag or Au.

[0029] Furthermore, the thickness of the top gate is 10nm to 100nm, and the top gate is made of one or more conductive materials such as TiN, Pd, Pt, W, Cu, Ag or Au.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The multi-timescale neural synaptic device proposed in this invention is a dual-gate transistor structure. It utilizes the top and back gates to control the channel state and uses source-drain resistance to characterize synaptic efficiency, generating short-term resistance variations based on different long-term resistance states. One gate enables long-term channel conductance control and exhibits non-volatility; the other gate enables short-term channel conductance control and exhibits volatile characteristics. The long-term resistance of the device can be used as network weights, while the short-term resistance is used to process network timing information, accelerating computation and contributing to the development of high-order intelligent chips. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of the neural synapse device of the present invention;

[0033] Figure 2 This is a schematic diagram of the electrical response of the neural synaptic device of the present invention under stimulation by the LTP gate control voltage VG1;

[0034] Figure 3 This is a schematic diagram of the electrical response of the neural synaptic device of the present invention under STP gate-controlled voltage VG2 stimulation;

[0035] Figure 4This is a schematic diagram of the electrical response of the neural synaptic device of the present invention under dual-gate control;

[0036] Figure 5 This is a flowchart illustrating the fabrication process of the neural synapse device of the present invention;

[0037] Figure 6 This is a diagram showing the response characteristics of the LTP gate terminal of the neural synapse device of the present invention;

[0038] Figure 7 This is a diagram showing the response characteristics of the STP gate of the neural synapse device of the present invention;

[0039] Figure 8 This diagram shows the response characteristics of the neural synapse device of the present invention under STP gate and STP gate hybrid programming. Detailed Implementation

[0040] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0041] To address the shortcomings of existing technologies, this invention discloses a multi-timescale neural synaptic device. This device employs a dual-gate transistor structure, utilizing the top and back gates to control the channel state and the source-drain resistance to characterize synaptic efficiency, generating short-term resistance variations based on different long-term resistance states. One gate enables long-term channel conductance control and exhibits non-volatility; the other gate enables short-term channel conductance control and exhibits volatile characteristics. The long-term resistance can be used as network weights, while the short-term resistance is used to process network timing information, accelerating computation and potentially driving the development of high-order intelligent chips.

[0042] like Figure 1 The diagram shown is a schematic of the structure of the multi-timescale neural synapse device proposed in this invention. The neural synapse device is a novel material device. Its basic structure, from bottom to top, includes a substrate, an insulating layer, a bottom gate (BG), a bottom dielectric layer (BD), a channel, a source, a drain, a top dielectric layer (TD), and a top gate (TG).

[0043] Among them, BG (back gate) and TG (top gate) can be selected as LTP modulation gate (long-term plasticity, LTP) or STP modulation gate (short-term plasticity, STP) respectively, depending on the material of BD (back dielectric layer) and TD (top dielectric layer);

[0044] The top gate (TG) and back gate (BG) are symmetrical in structure. If the top dielectric layer is made of a volatile material and the back dielectric layer is made of a non-volatile material, the top gate is used as the STP modulation gate and the back gate is used as the LTP modulation gate.

[0045] Taking the back gate as the LTP modulation gate as an example: the back dielectric layer can be a ferroelectric material, such as HZO, PZT, BTO, or a Flash structure. After stimulation is applied to the back gate, a residual built-in electric field is generated, producing a long-term stimulation of the channel, thus forming the LTP effect. Taking the top gate as the STP modulation gate: the top dielectric layer can be an antiferroelectric material, such as HZO, PZO, HfO, or AlO. After stimulation is applied to the top gate, a short-term channel resistance change is generated based on polarization reversal or the influence of defect sites within the channel, forming the STP effect. When continuous pulse stimulation is applied to the top gate, the balance between spontaneous decay and the stimulation effect results in a long-term pulse enhancement (PPF) or pulse suppression (PPD) effect. The channel material can be IGZO, p-type doped Si, InO, ZnO, MoS, etc.

[0046] Similar to the above scheme, when the back gate is used as the STP modulation gate, and the top gate is used as the LTP modulation gate, the back dielectric layer is made of a volatile material and the top dielectric layer is made of a non-volatile material.

[0047] By applying a read voltage to the drain, the resistance between the source and drain can be used as the weights of the synapse. By encoding a single gate stimulus, including the stimulus voltage, stimulus duration, and number of stimulus pulses, the device can achieve polymorphic long-term resistance transitions and different relaxation times. Furthermore, by simultaneously encoding the stimulation processes of the top and back gates, the synaptic weights can undergo short-term transitions under different initial states. The device can utilize short-time algorithms to calculate timing data during the weight storage process.

[0048] like Figure 2 As shown, this invention presents a multi-timescale neural synapse device operating at an LTP gate control voltage V. G1 A schematic diagram of the electrical response under stimulation is shown. Taking ferroelectric material as the gate dielectric as an example, when a pulse stimulus is applied to the LTP modulation gate, the ferroelectric material undergoes partial polarization reversal, inducing the generation of charge carriers in the channel, thereby changing the channel resistance and increasing the source-drain current. When an opposite polarity stimulus is applied, the polarization of the ferroelectric material is restored, the source-drain current decreases, and a long-term multi-resistivity modulation effect is achieved.

[0049] like Figure 3The diagram shows the electrical response of the multi-timescale neural synaptic device proposed in this invention under STP gate voltage VG2 stimulation. Taking an antiferroelectric material as the gate dielectric as an example, when a pulse stimulation is applied to the STP modulation gate, the antiferroelectric material undergoes a polarity reversal under stimulation. When the stimulation disappears, the polarization reversal spontaneously recovers, resulting in an initial increase followed by a decrease in the source-drain current. By adjusting the stimulation time, stimulation intensity, and stimulation interval, short-term modulation effects with different relaxation times and growth ratios can be achieved. Changing the stimulation polarity can achieve inhibitory modulation of the current.

[0050] like Figure 4 The diagram shows the electrical response of the device under dual-gate control. By simultaneously controlling both gates (VG1 as long-term gate control and VG2 as short-term control), short-term resistance state control can be achieved based on different long-term resistance states, which is reflected in the channel current change when the drain is connected to a fixed read bias and the source is grounded.

[0051] like Figure 5 As shown, in a preferred embodiment, the fabrication of the multi-timescale neural synapse device proposed in this invention includes the following steps:

[0052] Step 1: Oxidize and form a SiO2 insulating layer on the substrate silicon wafer. The thickness of the SiO2 layer is 100nm to 300nm. The thickness of the oxide layer can be reduced or increased according to the actual process conditions.

[0053] Step 2: Deposit a back gate (BG) on the SiO2 layer. The thickness of the back gate is 10 nm to 200 nm. The back gate material can be a conductive material such as TiN, Pd, Pt, W, Cu, Ag, or Au.

[0054] Step 3: Deposit a back dielectric layer (BD) on the back gate, with a thickness of 3 nm to 200 nm. The dielectric material can be Hf. x Zr y O z Ba x Ti y O z Bi x Fe y O z The values ​​of x, y, and z vary depending on the stoichiometric ratio, and non-volatility is required. Dielectric layer materials include, but are not limited to, the materials mentioned above; materials with electrically tunable non-volatile built-in electric field characteristics or electrically tunable volatile capacitance characteristics can be used.

[0055] Step 4: Deposit channel material on the back dielectric layer, with a channel thickness of 2nm to 50nm. Channel materials can be IGZO, p-type doped Si, InO, ZnO, MoS, etc. Channel materials include, but are not limited to, the above-mentioned materials; any material with semiconductor properties can be used.

[0056] Step 5: Deposit source and drain electrodes (S, D) on both sides of the channel, with a thickness of 2nm to 50nm. The source and drain electrode materials can be conductive materials such as TiN, Pd, Pt, W, Cu, Ag, or Au.

[0057] Step 6: Deposit a top dielectric layer (TD) on the source and drain electrodes, with a thickness of 3 nm to 200 nm. The dielectric material can be Hf. x Zr y O z Materials such as HfO and AlO, where the values ​​of x, y, and z vary depending on the stoichiometry, and volatility is a given. Dielectric layer materials include, but are not limited to, the above materials; materials with electrically tunable non-volatile built-in electric field characteristics or electrically tunable volatile capacitance characteristics can also be used.

[0058] Step 7: Deposit the top gate (TG) on the top dielectric layer. The thickness of the top gate is 10 nm to 100 nm. The top gate electrode material can be a conductive material such as TiN, Pd, Pt, W, Cu, Ag, or Au. After device fabrication, anneal as needed.

[0059] like Figure 6-8 The figure shows the response characteristics of multi-timescale synaptic devices; as shown... Figure 6 Taking the LTP gate pulse amplitude as an example, the device produces different degrees of long-term impedance transitions under pulse stimulation of different amplitudes. Furthermore, the long-term impedance can be programmed by adjusting the pulse duration and number.

[0060] like Figure 7 Taking the STP gate pulse amplitude as an example, under pulse stimulation of different amplitudes, the device generates short-term resistive state transitions with different relaxation times. Furthermore, the short-term resistive state relaxation time can be programmed by adjusting the pulse duration and quantity.

[0061] like Figure 8 The device's response under mixed programming of LTP gate (VG1) and STP gate (VG2). Under positive programming of VG1, the device resistance decreases; when a continuous positive pulse is applied to VG2, the device exhibits a PPF (paired-pulse facilitation) response, and the resistance decreases briefly; when a small negative voltage is applied to VG1, the device resistance partially returns to a high-resistance state.

[0062] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A multi-timescale neural synaptic device, characterized in that, It includes a substrate, an insulating layer, a back gate, a back dielectric layer, a channel, a source, a drain, a top dielectric layer, and a top gate; The substrate, insulating layer, back gate, back dielectric layer, channel, top dielectric layer and top gate are arranged sequentially from bottom to top, and the source and drain are located on both sides of the channel; Materials based on a back dielectric layer and a top dielectric layer; The top and back grids are symmetrical structures, and are symmetrical with respect to the channel material; A read voltage is applied to the drain, and the resistance between the source and drain is used as the weight of the synaptic device; By encoding a single gate stimulus, the synaptic device achieves polymorphic long-term resistance transitions and short-term resistance transitions with different relaxation times. By simultaneously encoding the stimulation processes of the top gate and the back gate, the synaptic device weights undergo short-term transitions under different initial states. If the top dielectric layer is made of a volatile material and the back dielectric layer is made of a non-volatile material, then the top gate is used as the STP modulation gate and the back gate is used as the LTP modulation gate. If the back dielectric layer is made of a volatile material and the top dielectric layer is made of a non-volatile material, then the back gate is used as the STP modulation gate and the top gate is used as the LTP modulation gate.

2. The multi-timescale neural synaptic device according to claim 1, characterized in that, The gate stimulation includes stimulation voltage, stimulation duration, and number of stimulation pulses.

3. The multi-timescale neural synaptic device according to claim 1, characterized in that, The device uses a short-time algorithm to calculate the time-series data during the storage of weights.

4. A method for fabricating a multi-timescale neural synaptic device, characterized in that, The method for fabricating a multi-timescale neural synaptic device as described in any one of claims 1-3 includes the following steps: An insulating SiO2 layer is formed on a silicon substrate by oxidation. A back gate is deposited on the SiO2 insulating layer; A back dielectric layer is deposited on the back gate; Deposit channels on the back dielectric layer; Source and drain electrodes are deposited on both sides of the channel, respectively; A top dielectric layer is deposited on the source and drain electrodes; A top gate is deposited on the top dielectric layer.

5. The method for fabricating a multi-timescale neural synaptic device according to claim 4, characterized in that, The thickness of the back gate is 10nm~200nm, and the back gate is made of one or more conductive materials selected from TiN, Pd, Pt, W, Cu, Ag or Au.

6. The method for fabricating a multi-timescale neural synaptic device according to claim 4, characterized in that, The thickness of the back dielectric layer is 3nm~200nm, and the thickness of the top dielectric layer is 3nm~200nm; The back dielectric layer and the top dielectric layer are dielectric layers made of materials with electrically tunable non-volatile built-in electric field characteristics or materials with electrically tunable volatile capacitance characteristics.

7. The method for fabricating a multi-timescale neural synaptic device according to claim 4, characterized in that, The channel thickness is 2nm~50nm, and the channel is made of a material with semiconductor properties.

8. The method for fabricating a multi-timescale neural synaptic device according to claim 4, characterized in that, The thickness of the source and drain electrodes is 2nm~50nm, and the source and drain electrodes are made of one or more conductive materials selected from TiN, Pd, Pt, W, Cu, Ag or Au.

9. The method for fabricating a multi-timescale neural synaptic device according to claim 4, characterized in that, The thickness of the top gate is 10nm~100nm, and the top gate is made of one or more conductive materials selected from TiN, Pd, Pt, W, Cu, Ag or Au.

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