Method and system using uart and single wire protocol

Abstract

Methods and systems (100) for data communication using single-wire communication protocols and universal asynchronous receiver-transmitter (UART) communication protocols are disclosed. The method includes receiving, by a first device (116), a reset pulse. The method includes operating the first device in a standard speed single-wire protocol if a width of the reset pulse is between 480 microseconds and 640 microseconds. The method includes operating the first device in an ultra speed single-wire protocol if the width of the reset pulse is between 48 microseconds and 80 microseconds. The method includes operating the first device in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between 240 microseconds and 480 microseconds. The method includes transmitting, by the first device, a response in response to the reset pulse (116). The method includes synchronizing the first device (116) with a host device in response to the reset pulse.

Description

Background Technology

[0001] This specification generally relates to data communication, and more specifically to methods and systems using UART and single-wire communication protocols.

[0002] Single-wire is a serial communication protocol that uses a single wire to transmit digital information (bits). This protocol allows a host device and one or more slave devices (e.g., peripheral devices) to transmit digital information in only one direction at a time (half-duplex). The host device and slave devices can be transmitters and receivers. The host device initiates and controls single-wire operation. The single-wire protocol uses CMOS / TTL logic and operates over a wide power supply voltage range.

[0003] Transmitting digital information serially over a single wire is less expensive than transmitting it in parallel over multiple wires because serial transmission requires only one pin, while parallel transmission requires a higher pin count. However, some single-wire protocols require input / output (I / O) bit-triggered software, which must be configured to read and write inputs and handle timing. Furthermore, the data transfer rate of some single-wire protocols is typically limited to a maximum rate of 120 kbps, depending on the cable / trace length.

[0004] To improve data rates, the Universal Asynchronous Receiver-Transmitter (UART) single-wire communication protocol is used in half-duplex mode in various hardware devices. In the UART protocol, the data format and transmission speed are configurable. UART devices cannot directly generate or receive external signals between different devices. Separate interface circuitry (e.g., driver circuitry) is used to convert the logic level signals of the UART to or from external devices. The UART master device receives multiple bytes of data and transmits the individual bits sequentially using the driver circuitry. At the destination, the slave UART device receives these bits using the driver circuitry and reassembles them into complete bytes. Unlike conventional or traditional single-wire protocols that only allow the transmission of a single bit per time slot (e.g., 120 microseconds), the UART protocol allows the transmission of 8 bits per time slot. Due to the faster speed of UART, various hardware devices (such as microcontrollers) are configured to communicate using the UART protocol. However, because many traditional slave devices are configured to operate only with conventional single-wire protocols, many systems simultaneously have both conventional single-wire compatible devices and UART-compatible devices coupled to the UART master device. Summary of the Invention

[0005] Various aspects of this specification relate to methods and systems for data communication using a single-wire communication protocol and a Universal Asynchronous Receiver-Transmitter (UART) communication protocol. In one aspect, a method includes receiving a reset pulse by a first device. The method further includes operating the first device with a standard-speed single-wire protocol if the width of the reset pulse is between 480 microseconds and 640 microseconds. The method also includes operating the first device with an overspeed single-wire protocol if the width of the reset pulse is between 48 microseconds and 80 microseconds. The method further includes operating the first device with a Universal Asynchronous Receiver-Transmitter (UART) protocol if the width of the reset pulse is between 240 microseconds and 480 microseconds. The method also includes transmitting an acknowledgment by the first device in response to the reset pulse. The method also includes transmitting data by a second device in response to an acknowledgment from the first device. The method also includes synchronizing the first device with the second device in response to the reset pulse.

[0006] In another aspect of this specification, a method for communication between a host device and one or more slave devices includes the host device transmitting a reset pulse and the slave devices receiving the reset pulse. The method further includes determining the width of the reset pulse. The method also includes: if the width of the reset pulse is between 480 microseconds and 640 microseconds, operating the slave device using a standard speed single-wire protocol. The method further includes: if the width of the reset pulse is between 48 microseconds and 80 microseconds, operating the slave device using an overspeed single-wire protocol. The method further includes: if the width of the reset pulse is between 240 microseconds and 480 microseconds, operating the slave device using a Universal Asynchronous Receiver-Transmitter (UART) protocol. The method also includes the slave device transmitting an acknowledgment in response to the reset pulse.

[0007] In another aspect of this specification, a data communication system includes a host device configured to provide a reset pulse via a transmit terminal and receive an acknowledgment at a receive terminal. The system further includes a slave device configured to receive a reset pulse at an input / output (I / O) terminal and provide an acknowledgment via the I / O terminal. The slave device includes a second terminal coupled to ground. The system also includes an NMOS transistor having a drain terminal coupled to both the I / O terminal and the transmit terminal, and a source terminal coupled to ground. The NMOS transistor includes a gate terminal. The system further includes a pull-up resistor coupled between the drain terminal and a voltage source terminal; and the system includes an inverter having an input terminal coupled to the transmit terminal and an output terminal coupled to the gate terminal. The slave device is configured to operate with a standard speed single-wire protocol if the width of the reset pulse is between 480 microseconds and 640 microseconds, and is configured to operate with an overspeed single-wire protocol if the width of the reset pulse is between 48 microseconds and 80 microseconds, and is configured to operate with a Universal Asynchronous Receiver-Transmitter (UART) protocol if the width of the reset pulse is between 240 microseconds and 480 microseconds.

[0008] In another aspect of the specification, the NMOS transistor is configured to turn on and drive its drain terminal to ground in response to a low reset pulse, and the NMOS transistor is configured to turn off and drive its drain terminal to a high level in response to a high reset pulse.

[0009] In another aspect of this specification, a data communication system includes a host device configured to provide a reset pulse via a transmit terminal and receive an acknowledgment at a receive terminal. The system further includes a slave device configured to receive a reset pulse at an input / output (I / O) terminal and provide an acknowledgment via the I / O terminal. The slave device includes a second terminal coupled to ground. The system also includes a PMOS transistor having a source terminal coupled to the I / O terminal and the transmit terminal and a drain terminal coupled to ground. The PMOS transistor includes a gate terminal. The system further includes a pull-up resistor coupled between the source terminal and a voltage source terminal; and the system includes an inverter having an input terminal coupled to the transmit terminal and an output terminal coupled to the gate terminal. The slave device is configured to operate in standard speed single-wire protocol if the width of the reset pulse is between 480 microseconds and 640 microseconds, and is configured to operate in ultra-high speed single-wire protocol if the width of the reset pulse is between 48 microseconds and 80 microseconds, and is configured to operate in Universal Asynchronous Receiver-Transmitter (UART) mode if the width of the reset pulse is between 240 microseconds and 480 microseconds.

[0010] In another aspect of the specification, the PMOS transistor is configured to turn off and drive its drain terminal to a high potential in response to a low potential reset pulse, and the PMOS transistor is configured to turn on and drive its drain terminal to ground in response to a high potential reset pulse. Attached Figure Description

[0011] Figure 1 Data communication systems in some embodiments are shown.

[0012] Figures 2 to 6 The timing diagram of the waveform is shown.

[0013] Figure 7 These are flowcharts of methods in some embodiments. Detailed Implementation

[0014] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, which show some, but not all, of the embodiments. In fact, these concepts can be embodied in many different forms, and there is no limitation. Rather, these descriptions are provided to make this specification suitable for any applicable needs.

[0015] Various aspects of this specification relate to methods and systems for data communication using a single-wire communication protocol and a Universal Asynchronous Receiver-Transmitter (UART) communication protocol. In one aspect, the methods and systems enable a host device and one or more slave devices to communicate using both a conventional or traditional single-wire communication protocol and a UART communication protocol. The slave device selects between the UART protocol and a conventional or traditional single-wire protocol, depending on the communication protocol used by the host device to transmit digital information (bits).

[0016] Figure 1 An example data communication system 100 according to this specification is shown. System 100 includes a host device 104 (also referred to as host 104) having a transmit terminal 108 and a receive terminal 112. The receive terminal 112 is coupled to a single-wire bus 110. For example, host device 104 may be a microcontroller. System 100 also includes a slave device 116 (also referred to as peripheral device 116) having input / output (I / O) terminals 120 coupled to the single-wire bus 110. Slave device or peripheral device 116 includes a second terminal 124 coupled to ground.

[0017] Continue to refer to Figure 1System 100 includes a transistor 130 having a first terminal 134 coupled to bus 110 and a second terminal 138 coupled to ground. Transistor 130 also includes a gate terminal 142 coupled to the output terminal 154 of inverter 146. Inverter 146 includes an input terminal 150 coupled to the emitter terminal 108 of host 104. System 100 also includes a pull-up resistor R coupled between bus 110 and voltage source terminal 160. PUP The voltage source terminal 160 can be coupled to a voltage power supply V. DD .

[0018] In one example, transistor 130 is an NMOS transistor having a drain terminal (terminal 134) coupled to bus 110 and a source terminal (terminal 138) coupled to ground. In another example, transistor 130 is a PMOS transistor having a source terminal (terminal 134) coupled to bus 110 and a drain terminal (terminal 138) coupled to ground.

[0019] Continue to refer to Figure 1 Data transmission between the host device 104 and the slave device 116 is a bit-oriented operation with data read and data write. The host device 104 initiates and controls four basic operations: (1) reset; (2) write bit 0 – send bit 0 to the slave device; (3) write bit 1 – send bit 1 to the slave device; and (4) read bit – read a bit from the slave device. Most single-wire devices support two data rates: a standard speed of approximately 15 kbps and an overspeed of approximately 70 kbps or higher. The communication sequence begins when the host device 104 drives a defined reset pulse. The slave device 116 responds to the reset pulse with an acknowledge pulse and synchronizes with the host device 116.

[0020] Reset pulse: In order to send a reset pulse to slave device 116, bus 110 is driven to a low level and delayed for 480 microseconds. Then bus 110 is released and delayed for 70 microseconds.

[0021] Write bit 0: In order to send bit 0 to slave device 116, bus 110 is driven low and delayed for 60 microseconds. Then bus 110 is released and delayed for up to 120 microseconds.

[0022] Write bit 1: In order to send bit 1 to slave device 116, bus 110 is driven low and delayed for 6 microseconds. Then bus 110 is released and delayed for up to 120 microseconds.

[0023] Reading a bit: In order to read a bit from slave device 116, bus 110 is driven low and delayed for 6 microseconds. Bus 110 is then released and delayed for up to 120 microseconds. Figure 2The timing diagrams for reset pulse 204, write bit 9 (208), write bit 1 (212), and read bit (216) are shown.

[0024] Figure 3 An exemplary time slot 304 and a timing diagram of the bits transmitted in time slot 304 are shown. Time slot 304 is divided into eight sampling windows D0-D7, which can be used by the host device and slave devices to sample bits. Under conventional or traditional single-wire protocols, a single bit is transmitted in time slot 304, but under the UART protocol, eight bits are transmitted in time slot 304. In pulse 308, the host device transmits bit 1 (host write -1) sampled by the slave device in sampling window D3 in sampling windows D0-D7, and in pulse 312, the host device transmits bit 0 (host write -0) sampled by the slave device in sampling window D3 in sampling windows D0-D7. In pulse 316, the host device receives bit 1 sampled in sampling window D3 (host read -1), and in pulse 320, the host device receives bit 0 sampled in sampling window D3 (host read -0). Although in Figure 3 In the example, the host and slave devices sample the bits in sample window D3, but any of sample windows D0-D7 can be used to sample the bits. The receiving device encodes the transmitted signal as logic 0 (bit 0) or logic 1 (bit 1) based on the percentage of time the signal is at a low level. For example, in a given time slot, if the transmitted signal is at a low level for at least 90% of the duration, the signal is encoded as logic 0 (bit 0), and if the transmitted signal is at a low level for 10% or less of the duration, the signal is encoded as logic 1 (bit 1).

[0025] Figure 4 A timing diagram showing the pulse sequences in the write and read operations is shown. The write operation begins when the master device 104 sends a reset pulse 404A via the single-wire bus, followed by an acknowledgment 404B from the slave device 116. The master device 104 then sends bit 1 404C, sampled by the slave device 116 in sample window 404D. The master device 104 then sends bit 0 404E, sampled by the slave device 116 in sample window 404F, via the bus. The read operation begins with a reset pulse 408A and a subsequent acknowledgment 408B from the slave device 116. The slave device 116 sends bit 1 408C, sampled by the master device 104 in sample window 408D. The slave device 116 then sends bit 0 408E, sampled by the master device 104 in sample window 408F.

[0026] As described above, conventional single-wire protocols allow only one bit to be transmitted in each time slot, but the UART protocol allows eight bits to be transmitted in one time slot. Embodiments of this specification enable systems such as System 100 to switch between conventional single-wire or UART protocols that rely on the same hardware interface. Therefore, host device 104 can transmit bits via bus 112 using either a conventional single-wire protocol or the UART protocol. Slave device 116 identifies the communication protocol and switches between the conventional single-wire protocol and the UART protocol.

[0027] According to the examples in this specification, the width of the reset pulse is used to determine whether operation is performed using the standard single-wire protocol or the UART protocol. Furthermore, the width of the reset pulse is used to set the speed of the single-wire protocol (standard speed or overspeed).

[0028] In one example, a reset pulse detector 118 in slave device 116 measures the width of the reset pulse. If the reset pulse width is between 480 microseconds and 640 microseconds, the slave device operates according to the standard speed single-wire protocol. If the reset pulse width is between 48 microseconds and 80 microseconds, the slave device operates according to the overspeed single-wire protocol.

[0029] Figure 5 The timing diagram shows the waveforms from a standard speed and overspeed single-wire protocol, as shown in an example. For the standard speed single-wire protocol, the host device sends a reset pulse 504A with a width between 480 and 640 microseconds, followed by an acknowledgment 504B from the slave device. The slave device switches to the standard speed single-wire protocol. The host device performs two write operations: sending bit 1 (504C) and then bit 0 (504D). The host device then performs two write operations: receiving bit 1 (504E) and then receiving bit 0 (504F).

[0030] For the SuperSpeed ​​Single-Wire protocol, the master device sends a reset pulse 508A with a width between 48 and 80 microseconds, followed by an acknowledgment 508B from the slave device. The slave device switches to the SuperSpeed ​​Single-Wire protocol. The master device performs two write operations: sending bit 1 (508C) and then bit 0 (508D). Then, the master device performs two write operations: receiving bit 1 (508E) and then receiving bit 0 (508F).

[0031] Figure 6The timing diagram of the waveforms in the UART protocol is shown. For the UART protocol, the master device sends a reset pulse 604A with a width between 240 microseconds and 480 microseconds and receives an optional alarm or response 604B. The master device then sends a Baud Rate Training Pattern 604C to enable the slave device to align its internal clock (i.e., synchronize) to decode the UART frame. The master device then sends a master command or data 604D. The master device then receives data 604E from the slave device.

[0032] Figure 7 The flowchart 700 illustrates an example method. In block 704, the host device 104 sends a reset pulse via bus 112. The slave device 116 receives the reset pulse and, in block 708, determines whether the width of the reset pulse is less than 80 microseconds. If the width of the reset pulse is less than 80 microseconds, in block 712, the slave device 116 switches to the overspeed single-wire protocol, and in block 716, the slave device 116 receives commands and data sent by the host device.

[0033] If slave device 116 determines in box 708 that the width of the reset pulse is not less than 80 microseconds, the process moves to box 720, where slave device 116 determines whether the width of the reset pulse is greater than 480 microseconds. If the width of the reset pulse is greater than 480 microseconds, slave device 116 switches to the standard speed single-wire protocol in box 724. If the width of the reset pulse is not greater than 480 microseconds, slave device 116 switches to UART protocol mode in box 728. The process moves to box 716, where slave device 116 receives commands and data.

[0034] Therefore, slave device 116 only operates in UART mode when the width of the reset pulse is between 240 microseconds and 480 microseconds. Since the width of the reset pulse for the standard speed single-wire protocol is between 480 microseconds and 640 microseconds and the width of the reset pulse for the overspeed single-wire protocol is between 48 microseconds and 80 microseconds, the pulse width in the 240-480 microsecond range is reserved for UART mode, thus allowing slave device 116 to recognize that master device 104 intends to communicate using the UART protocol.

[0035] refer to Figure 1The operation of system 100 will now be described. For example, consider the case where transistor 130 is an NMOS transistor. To perform a write 0 operation, host device 104 drives emitter terminal 108 to a low potential, which causes output 154 of inverter 146 to be driven to a high potential. Gate terminal 142 coupled to output 154 is also driven to a high potential, causing the NMOS transistor to turn on and provide a conductive path. As a result, drain terminal 134 is driven to a low potential, causing bus 112 to also be driven to a low potential. Therefore, bit 0 appears at I / O terminal 120.

[0036] To perform a write-1 operation, the host device 104 drives the emitter terminal 108 to a high potential, which causes the output 154 of the inverter 146 to be driven low. Consequently, the gate terminal 142 coupled to the output 154 is also driven low, causing the NMOS transistor to turn off. As a result, the drain terminal 134 is driven high, causing the bus 112 to also be driven high. Therefore, bit 1 appears at the I / O terminal 120 of the slave device 116.

[0037] To perform a read 0 operation, slave device 116 drives I / O terminal 116 low, causing bus 112 to be driven low. Therefore, bit 0 appears at receive terminal 112. When I / O terminal 120 is driven low, a voltage supply V is formed. DD The low-resistance path to the I / O terminals causes current to flow from the voltage supply V. DD The current flows to I / O terminal 120. However, the pull-up resistor R... PUP Limit current from voltage source V DD The current flows to I / O terminal 120.

[0038] To perform a read 1 operation, slave device 116 drives I / O terminal 116 to a high level, causing bus 112 to be driven to a high level. Therefore, bit 1 appears at receive terminal 112.

[0039] For example, consider the case where transistor 130 is a PMOS transistor. To perform a write 0 operation, host device 104 drives emitter terminal 108 to a high potential, which causes the output 154 of inverter 146 to be driven low. Gate terminal 142, coupled to the output of inverter 146, is also driven low, causing the PMOS transistor to turn on and source terminal 134 to be driven low. As a result, bus 112 is driven low. Therefore, bit 0 appears at I / O terminal 120.

[0040] To perform a write 1 operation, the master device 104 drives the transmit terminal 108 to a low potential, which causes the output 154 of the inverter 146 to be driven to a high potential. Consequently, the gate terminal 142 coupled to the output 154 is also driven to a high potential, causing the PMOS transistor to turn off. As a result, the source terminal 134 is driven to a high potential, causing the bus 112 to be driven to a high potential. Therefore, bit 1 appears at I / O terminal 120. To read bit 0, the slave device 116 drives the I / O terminal 120 to a low potential, causing the bus 112 to be driven to a low potential. Therefore, bit 0 appears at the receive terminal 112. To read bit 1, the slave device 116 drives the I / O terminal 120 to a high potential, causing the bus 112 to be driven to a high potential. Therefore, bit 1 appears at the receive terminal 112.

[0041] The various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functions. Whether these functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. For each specific application, the described functions may be implemented in different ways, and such implementation decisions do not deviate from the scope of this specification.

[0042] For the sake of simplicity and clarity, the complete structure and operation of all systems applicable to this specification are not depicted or described herein. Instead, only systems unique to this specification or necessary for understanding this specification are depicted and described.

Claims

1. A method of communication, comprising: The reset pulse is received by the first device; If the width of the reset pulse is greater than 480 microseconds and less than 640 microseconds, the first device operates at standard speed single-wire protocol; If the width of the reset pulse is between 48 microseconds and 80 microseconds, the first device is operated using the overspeed single-wire protocol. as well as If the width of the reset pulse is greater than 240 microseconds and not greater than 480 microseconds, the first device is operated using the Universal Asynchronous Receiver-Transmitter Protocol (UART).

2. The method of claim 1, wherein the reset pulse is emitted by the second device.

3. The method according to claim 2, wherein the second device is a host device.

4. The method according to claim 2, wherein the first device is a subordinate device.

5. The method of claim 1, further comprising transmitting a response from the first device in response to the reset pulse.

6. The method of claim 5, further comprising transmitting data by the second device in response to the response from the first device.

7. The method of claim 1, further comprising synchronizing the first device with the host device in response to the reset pulse.

8. A method for communicating between a host device and one or more slave devices, the method comprising: The host device transmits a reset pulse; The reset pulse is received by the slave device; Determine the width of the reset pulse; If the width of the reset pulse is greater than 480 microseconds and less than 640 microseconds, the slave device operates with a standard speed single-wire protocol. If the width of the reset pulse is between 48 microseconds and 80 microseconds, the slave device operates with an overspeed single-wire protocol. If the width of the reset pulse is greater than 240 microseconds and not greater than 480 microseconds, the slave device is operated using the Universal Asynchronous Receiver-Transmitter Protocol, i.e., the UART protocol. as well as In response to the reset pulse, the slave device sends a response.

9. The method of claim 8, further comprising synchronizing the slave device with the master device in response to the reset pulse.

10. The method of claim 8, further comprising transmitting data by the host device in response to the response from the slave device.

11. A data communication system, comprising: The host device is configured to provide a reset pulse via a transmit terminal and receive an acknowledgment at a receive terminal; A slave device is configured to receive the reset pulse at an input / output terminal, i.e., an I / O terminal, and to provide the response through the I / O terminal, the slave device having a second terminal coupled to ground; An NMOS transistor having a drain terminal coupled to the I / O terminal and the emitter terminal and a source terminal coupled to ground, the NMOS transistor having a gate terminal; A pull-up resistor is coupled between the drain terminal and the voltage source terminal; An inverter having an input terminal coupled to the emitter terminal and an output terminal coupled to the gate terminal. The slave device is configured to operate with a standard speed single-wire protocol if the width of the reset pulse is greater than 480 microseconds and less than 640 microseconds, and the slave device is configured to operate with an ultra-high speed single-wire protocol if the width of the reset pulse is between 48 microseconds and 80 microseconds, and the slave device is configured to operate with a Universal Asynchronous Receiver-Transmitter Protocol (UART) if the width of the reset pulse is greater than 240 microseconds and not greater than 480 microseconds.

12. The data communication system of claim 11, wherein the NMOS transistor is configured to turn on and drive the drain terminal to ground in response to the reset pulse being low.

13. The data communication system of claim 11, wherein the NMOS transistor is configured to turn off and drive the drain terminal to a high potential in response to the reset pulse being high.

14. The data communication system according to claim 11, wherein the host device is a microcontroller.

15. The data communication system of claim 11, wherein the slave device is configured to synchronize with the host device in response to the reset pulse.

16. The data communication system of claim 11, wherein the host device is configured to transmit data in response to the response from the slave device.

17. The data communication system of claim 11, wherein the receiving terminal is coupled to the I / O terminal.

18. The data communication system according to claim 11, wherein the slave device is a peripheral device.

19. A data communication system, comprising: The host device is configured to provide a reset pulse via a transmit terminal and receive an acknowledgment at a receive terminal; A slave device is configured to receive the reset pulse at an input / output terminal, i.e., an I / O terminal, and to provide the response through the I / O terminal, the slave device having a second terminal coupled to ground; A PMOS transistor having a source terminal coupled to the I / O terminal and the emitter terminal and a drain terminal coupled to ground, the PMOS transistor having a gate terminal; A pull-up resistor is coupled between the source terminal and the voltage source terminal; An inverter having an input terminal coupled to the emitter terminal and an output terminal coupled to the gate terminal. The slave device is configured to operate with a standard speed single-wire protocol if the width of the reset pulse is greater than 480 microseconds and less than 640 microseconds, and the slave device is configured to operate with an ultra-high speed single-wire protocol if the width of the reset pulse is between 48 microseconds and 80 microseconds, and the slave device is configured to operate with a Universal Asynchronous Receiver-Transmitter Protocol (UART) if the width of the reset pulse is greater than 240 microseconds and not greater than 480 microseconds.

20. The data communication system of claim 19, wherein the PMOS transistor is configured to turn off and drive the drain terminal to a high potential in response to the reset pulse being low.

21. The data communication system of claim 19, wherein the PMOS transistor is configured to turn on and drive the drain terminal to ground in response to the reset pulse being high.

22. The data communication system according to claim 19, wherein the host device is a microcontroller.

23. The data communication system of claim 19, wherein the slave device is configured to synchronize with the master device in response to the reset pulse.

24. The data communication system of claim 19, wherein the host device is configured to transmit data in response to the response from the slave device.

25. The data communication system according to claim 19, wherein the slave device is a peripheral device.

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