High-density spin-orbit-torque magnetic random access memory

Abstract

The present disclosure relates to a spin-orbit torque memory device having a vertical transistor structure. The spin-orbit torque memory device includes a magnetic memory element, such as a magnetic tunnel junction formed on a spin-orbit torque layer. The vertical transistor structure selectively provides current to the spin-orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high current required to provide spin-orbit torque switching while also consuming a small amount of wafer area. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

Description

Technical Field

[0001] The present invention relates to a spin orbital moment (SOT) magnetic random access memory (MRAM), and more particularly, to an SOT MRAM structure that employs vertical transistors to provide drive current to the spin orbital moment layer. Background Technology

[0002] Random Access Memory (RAM) is a ubiquitous component in modern digital circuit architectures. RAM can be a standalone device or integrated into devices that use RAM, such as microprocessors, microcontrollers, application-specific integrated circuits (ASICs), system-on-a-chip (SoCs), and other similar devices. RAM can be volatile or non-volatile. Volatile RAM loses its stored information whenever power is lost. Non-volatile RAM retains its memory contents even when power is off.

[0003] Magnetoresistive random access memory (MRAM) is a non-volatile memory technology with response (read and write) times comparable to volatile memory. Data stored in MRAM does not degrade over time, and MRAM uses very little power compared to other RAM technologies. Unlike conventional RAM technologies that store data while charge or current flows, MRAM uses magnetic memory elements. Therefore, MRAM possesses several desirable characteristics that make it a candidate for general-purpose memory, such as high speed, high density (i.e., small cell size), low power consumption, and very little logic state degradation over time.

[0004] Despite these characteristics, conventional MRAM devices are not perfect. Conventional memory elements (such as magnetic tunnel junctions (MTJs)) in spin-torque MRAMs (e.g., STT-MRAMs) are two-terminal devices with shared read and write paths. This shared read and write path introduces problems for read speed and write reliability. For writing, the barrier layer in the MTJ must be thin enough (and have relatively low resistance) to allow the current required for switching. However, thin barrier layers are more susceptible to dielectric breakdown due to repeated write operations. Furthermore, the state of the MTJ can be unintentionally flipped by the read current. This is known as "read interference." As MTJ technology shrinks in physical size, the switching current tends to decrease. However, high-speed read operations typically require larger read currents. Therefore, high-speed MRAMs, especially deeply scaled MTJ devices, suffer from read interference. Thus, meeting the reliability requirements for both write endurance (due to strain on the tunnel barrier in the MTJ) and read reliability is challenging.

[0005] Spin-orbit moment-based MRAM devices exhibit switching speeds as low as approximately 200 ps, ​​making them suitable for L1 / L2 caching applications. Another key aspect of these devices is their lack of durability issues because the read and write current paths are separate. In two-terminal MRAM devices, the read current is typically an order of magnitude lower than the write current. By eliminating the large write switching current, SOT memories remove significant stress from the MgO barrier layer, thereby improving reliability and durability.

[0006] However, such devices suffer from data density limitations. First, they are three-terminal devices and therefore require three transistors. Second, the write current density through spin-orbit moment materials in these structures can reach as high as 1 to 2 × 10⁻⁶. 8 A / cm 2 This requires switching currents in the hundreds of microamps (e.g., about 100 to 400 microamps) for typical spin-orbit moment layers. This significantly increases transistor size, making it very expensive. Reducing the cross-section of the spin-orbit moment layer and the size of the transistor is crucial for finding suitable applications. Summary of the Invention

[0007] This invention provides a spin orbital moment data recording device comprising a magnetic memory element having a magnetic free layer. A conductive spin orbital moment layer is adjacent to the magnetic free layer of the magnetic memory element. A vertical transistor structure is electrically connected to the spin orbital moment layer and configured to selectively supply current to the spin orbital moment layer.

[0008] The vertical transistor structure may further include semiconductor pillars and a gate dielectric layer surrounding the semiconductor pillars. A conductive gate layer may be formed adjacent to the gate dielectric, such that the gate dielectric layer separates the conductive gate layer from the semiconductor pillars. The semiconductor pillars may be formed having first and second doped ends, both of which may be n+ doped regions. The semiconductor pillar structure may be an epitaxially grown semiconductor material, which may be a substantially single-crystal semiconductor material.

[0009] The vertical transistor structure may be a write selector transistor, and the data recording device may further include a read selector transistor that can be electrically connected to the magnetic data recording element at an end opposite to the spin orbital layer.

[0010] The magnetic memory element may be a magnetic tunnel junction element. The spin-orbit spacer may be formed of one or more of β-phase tungsten (W) and / or β-phase tantalum (Ta).

[0011] Spin-orbit moment memory (SEM) offers improved durability compared to other types of magnetic memories because switching can be performed without repeatedly driving high currents through the memory element. These high currents would stress the barrier layer, potentially causing it to break down and reducing lifespan and reliability. However, the high currents required to drive the spin-orbit moment device for switching also necessitate sufficiently large and robust write selector transistors to handle these high write currents.

[0012] The vertical transistor structure advantageously allows the high current required for the spin-orbit memory to be supplied to the spin-orbit layer. The vertical transistor also advantageously provides this high current while occupying a small wafer area.

[0013] These and other features and advantages of the invention will become apparent after reading the following detailed description of the embodiments in conjunction with the accompanying drawings, in which like reference numerals indicate all like elements. Attached Figure Description

[0014] To gain a more complete understanding of the nature and advantages of the invention and its preferred modes of use, the following detailed description should be read in conjunction with the accompanying drawings, which are not drawn to scale.

[0015] Figure 1 This is the electrical schematic diagram of the circuit system of a spin-orbit moment magnetic random access memory unit.

[0016] Figure 2 This is a perspective view of the memory element of a spin-orbit moment magnetic random access memory system according to an embodiment.

[0017] Figure 3 This is a cross-sectional view of the vertical transistor structure according to an embodiment;

[0018] Figure 4 From Figure 3 A cross-sectional view of the vertical transistor structure seen in line 4-4;

[0019] Figure 5 This is a perspective view of a spin-orbit magnetic random access memory (SRAM) structure that employs a vertical transistor structure electrically connected to a spin-orbit magnetic random access memory (SRAM) element.

[0020] Figures 6 to 15 A portion of a spin-orbit moment memory structure is shown in various intermediate manufacturing stages to illustrate possible methods for manufacturing spin-orbit moment structures employing vertical transistors. Detailed Implementation

[0021] The following description represents the currently considered best embodiments for carrying out the invention. This description is intended to illustrate the general principles of the invention and is not intended to limit the inventive concepts claimed herein.

[0022] Figure 1 This is a schematic diagram of a spin-orbit-moment (SOM) memory structure 100 according to one possible embodiment. The memory structure 100 includes a SOM memory element 102, which includes a magnetic memory element 104, which may be a magnetic tunnel junction (MTJ), and a SOM layer 106. At its most basic level, the MTJ may include a magnetic reference layer 108, a magnetic free layer 110, and a thin non-magnetic barrier layer 112, as will be described in more detail below. The SOM layer 106 may be made of a conductive metal, such as β-phase tungsten (W) and / or β-phase tantalum (Ta). The memory element 102 is a three-terminal device that can be electrically connected to the source line SL and selectively connected to the bit line BL. As will be seen, a pair of transistors 114, 116 can be used to select between a read mode and a write mode, respectively. Transistor 114 is a write transistor that can be turned on to allow write current to flow through the SOM layer 106 between the source line SL and the bit line BL. The switching mechanism of the memory element 102 will be described in more detail below. The transistor switching device 116 is a read transistor that allows read current to flow through the magnetic memory element 104 between the bit line and the source line.

[0023] Figure 2 This diagram illustrates an enlarged perspective view of the structure and operation of a spin-orbit moment memory element 102 according to an embodiment. The memory element structure 102 includes the aforementioned magnetic memory element 104, which may be a magnetic tunnel junction element. For example, the MTJ element 104 may include a magnetic reference layer 108, which may be made of a magnetic material such as (but not limited to) NiFe, CoFe, etc., and has magnetization 202 fixed in a predetermined orientation, which may be parallel to the plane of the layer, such as... Figure 2 As shown in the diagram. Pinning of the magnetization 202 of the reference layer 108 can be facilitated by a synthetic antiferromagnetic structure 204, which may comprise a pair of magnetic layers 206, 208 exchange-coupled via, for example, a nonmagnetic coupling layer 210 of Ru. The magnetic layers 206, 208 can be antiparallel exchange-coupled such that the magnetization of layers 206, 208 is pinned in opposite directions, as shown. The exchange coupling between the synthetic antiferromagnetic structure 204 and the reference layer 108 results in the magnetization 202 of the reference layer 108 being firmly pinned in the desired direction.

[0024] The MTJ may also include a magnetic free layer 110 having a magnetization 204 that is movable between magnetic orientations, the magnetic orientations also being parallel to the plane of the magnetic free layer 110. The MTJ may be constructed to have in-plane magnetic anisotropy to allow the magnetization 212 to switch between two orientations and then remain stable in said orientation. The magnetization 212 of the magnetic free layer 110 may be tilted in a stationary state to facilitate switching between the two states.

[0025] The magnetization 212 can be switched between two stable magnetic states by coupling with the spin orbitals of the spin orbital layer 106. When a current flows through layer 106, the spin orbitals of electrons passing through the spin orbital layer 106 become aligned, as illustrated by line 208, where electrons at the top of layer 106 are aligned in a first direction and electrons at the bottom of layer 106 are aligned in the opposite direction. The spin-oriented electrons at the top surface of layer 106 provide a force on the magnetization 212 of the free layer 110 that causes the magnetization 212 to switch to the desired orientation. Switching the magnetization 212 to the opposite direction can be achieved by generating a current flowing through the spin orbital layer 106 in the opposite direction.

[0026] Using a spin-orbit moment layer 106 to switch the magnetization 212 of the magnetic free layer 110 improves the switching speed and durability of the memory system. Switching without a spin-orbit moment layer requires applying a high switching current directly through the memory element 104 in a direction perpendicular to the layer plane. This applies high thermal stress to the barrier layer 112, which can lead to barrier layer breakdown, thereby shortening the lifespan of the memory element. In addition, spin-orbit moment switching provides a higher switching speed than other switching mechanisms. For example, spin-orbit moment-based MRAM devices can exhibit switching speeds as low as about 200 picoseconds (ps), making them suitable for L1 / L2 cache applications.

[0027] One challenge posed by spin-orbit moment MRAM systems is the need for a large current to pass through the spin-orbit moment layer 106 to achieve the desired switching of the magnetization 212 of the free layer 110. This large current requires a corresponding large selector transistor. Using current, conventional transistors would require a large wafer area to handle the high current load and thus reduce the density of memory systems using this technology.

[0028] According to an embodiment, this challenge can be overcome by using a vertically epitaxial selector transistor. (Reference) Figure 1 A schematic diagram, Figure 1 The selector transistor 114, schematically shown, can be configured as a vertical transistor structure, which can handle high current loads while occupying less area than conventional transistor structures. Another selector transistor 116 can also be configured as a vertical transistor structure. However, since this transistor 116 does not need to handle the high current load of transistor 114, it does not need to be configured as a vertical transistor structure.

[0029] Figure 3 and 4 A cross-sectional view of the transistor structure 114 according to an embodiment is shown. Figure 3 It is a cross-sectional view along a plane parallel to the word line structure (written WL), and Figure 4 From Figure 3The cross-sectional view is shown in line 4-4. The selector transistor structure 114 is formed on a semiconductor substrate 302, which is preferably a silicon substrate, but may also be some other semiconductor material. The semiconductor substrate 302 includes an upper portion that can be doped to form a source line layer 304. The source line layer 304 may be divided into individual source line structures by a dielectric trench isolation structure 306, which may be made of oxide (e.g., silicon oxide) or nitride.

[0030] Semiconductor pillars 308 are formed above source line layers 304 on substrate 302. The semiconductor pillars are preferably epitaxially grown semiconductors, such as Si or SiGe. Epitaxially grown semiconductor materials have been found to possess excellent crystallographic properties, exhibiting properties highly suitable for conducting current. The method for constructing these epitaxial semiconductor pillars 308 will be described in more detail below. Doped regions 310 and 312 may be formed at the bottom and top of the semiconductor pillars 308. The doped regions 310 and 312 may be n+ doped by implantation, annealing, etc., and provide the source and drain of the vertical semiconductor structure 114.

[0031] The semiconductor pillar 308 is surrounded by a gate dielectric layer 314 and a gate structure 316, such that the gate dielectric layer 314 surrounds the pillar 308 and separates the semiconductor pillar 314 from the gate structure 316. The gate structure may include upper and lower dielectric layers 318 and a conductive gate line layer 320 located between the upper and lower dielectric layers 318. The upper and lower dielectric layers 318 may be made of oxide or nitride, and the conductive gate layer 320 may be made of, for example, a highly doped semiconductor material (e.g., highly doped silicon). Conductive leads 322 may be formed above the top (opposite to the source line layer 304) to provide electrical connection between the semiconductor pillar 308 and the bit line (BL).

[0032] The semiconductor pillar 308 can be cylindrical, but it can also have other shapes. For example, the semiconductor pillar can have an elongated elliptical or oval shape (when viewed from above) or can be formed as a rectangular prism (when viewed from above). Figure 3 and 4 (When viewed from above). Figure 3 and 4 As shown, the bottom of the semiconductor pillar 308 may have a sloping bottom. This can be advantageous during the formation of the pillar 308, as will be explained further below. The semiconductor pillar 308, together with the gate dielectric layer 314 and the gate structure 316, forms a vertical CMOS selector transistor structure, wherein the bottom 310 and the top 312 are the source and drain regions, respectively. When a gate voltage is applied across the gate dielectric layer from the conductive gate layer 320, the pillar 308 becomes conductive to allow current to flow between the source line layer 304 and the bit line layer BL. Conversely, when the gate voltage is removed, the semiconductor pillar 308 becomes electrically insulating to prevent current from flowing between the source line layer 304 and the bit line BL.

[0033] Figure 5 This is a perspective view of a spin-orbit moment MRAM structure employing, for example, the vertical transistor structure 114 described above. Figure 5 As seen, bit line BL is connected to read selector transistor 116, which connects bit line BL to magnetic memory element 104, which may be a magnetic tunnel junction (MTJ) element. Bit line BL is also connected to vertical selector transistor 114. Vertical selector transistor 114 is a write word line selector that selectively connects bit line BL to source line layer 304.

[0034] During read mode, read transistor 116 is off and transistor 114 is on. Read transistor 116 is controlled by a signal from read word line WL, which provides a gate voltage to read transistor 116. The memory state of memory element 104 can be read by applying a voltage to the memory element between the bit span line BL and the source line SL.

[0035] During write mode, write selector transistor 114 is turned off, thereby connecting bit line BL to source line SL via source line layer 304 formed in the substrate. The write selector transistor is controlled by a gate voltage applied to the write word line (write WL). This causes current to flow through spin orbital layer 106. As previously described, when current flows through spin orbital layer 106, electrons become spin-polarized in opposite directions at the top and bottom of layer 106. This electron spin polarization causes the free layer of memory element 104 to be magnetized in a desired direction, which depends on the direction of current flow through spin orbital layer 106.

[0036] The vertical semiconductor structure 114 can advantageously handle higher current loads than conventional transistor structures, and can do so while occupying a small area on the substrate 302. These advantages are further enhanced when the semiconductor pillars are formed by epitaxial growth on the substrate. Figures 6 to 15 This is a view of a portion of a spin-orbit-moment (SOM) MRAM system during various intermediate manufacturing stages, illustrating a method for fabricating a SOM structure with a vertical transistor configuration. Special reference. Figure 6A semiconductor substrate 602 is provided. The substrate 602 may be a silicon wafer or another type of semiconductor material, such as SiGe. The upper portion 604 of the substrate 602 may be doped (e.g., n+ doping) to form a highly doped source layer. Doping can be performed by ion implantation or in-situ deposition of the doped semiconductor material. Optionally, a dielectric trench isolation structure 606 may be formed to separate the doped upper portion 604 into individual source layers. The trench isolation structure 606 may be formed by etching trenches and depositing a dielectric material such as silicon oxide or silicon nitride. A chemical mechanical polishing process may be performed to planarize the wafer-doped source region 604 and the upper surface of the trench isolation structure 606.

[0037] For reference Figure 7 A series of layers are deposited to form a gate structure 702. The gate structure 702 includes a conductive gate layer 708 located between the first and second dielectric gate dielectric layers 704 and 706. The conductive gate layer 708 may be a highly doped semiconductor (e.g., highly doped silicon) or some other type of conductive material. The first and second dielectric layers 704 and 706 may be oxides or nitrides, such as silicon oxide or silicon nitride.

[0038] For reference Figure 8 An opening 802 is formed in layers 704, 708, and 706, stopping at the doped source layer 604 of the substrate 602. The opening can be configured to have a shape that defines the silicon pillar structure, and can be circular, elliptical, rectangular, etc., as needed. The opening 802 is formed by a masking and etching process. Next, a gate dielectric layer 804 is deposited, followed by a protective layer 806. The gate dielectric layer can be a material such as silicon oxide or silicon nitride and is deposited to have a thickness on the side of the opening 802, which will provide the desired spacing between the semiconductor pillar (not yet formed) and the conductive gate layer 708. The protective layer can be a material selected to have etch selectivity for the gate dielectric layer 804, such that the protective layer 806 can be removed by etching chemicals to leave the gate dielectric layer 804 substantially intact. The gate dielectric layer 804 and the protective layer 806 can be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0039] For reference Figure 9 An anisotropic material removal process, such as ion milling, is performed to preferentially remove the horizontally positioned portions of layers 804 and 806 to open the bottom of opening 802 and expose the underlying source line layer 604. This material removal process leaves the gate dielectric layer 804 and the protective layer 806 on the inside of opening 802. The protective layer 806 protects the gate dielectric layer 804 during this material removal process (e.g., ion milling).

[0040] For reference Figure 10Selective etching is performed to remove the protective layer 806, leaving the gate dielectric layer 804 on the inside of the opening 802. This selective etching can be reactive ion etching and can be performed using chemicals selected to remove the protective layer 806 without significantly removing the gate dielectric layer 804.

[0041] refer to Figure 11 Further etching can be performed to remove a portion of the doped source line layer 604. This etching can be performed by forming a bevel 1102 on the exposed source layer 604, as shown in the example. Figure 11 As shown in the figure. This has been found to promote good crystal growth during subsequent epitaxial semiconductor deposition.

[0042] For reference Figure 12 Semiconductor material 1202 is grown in opening 802. Semiconductor 1202 can be Si, SiGe, etc., and is preferably grown using selective epitaxial growth. Epitaxial growth of semiconductor material 1202 provides good crystal properties within it. As mentioned above, the beveled shape of the source line layer 604 at the bottom of opening 802 further promotes the excellent crystal properties of the epitaxially grown semiconductor material 1202. Therefore, semiconductor material 1202 can have a single-crystal or near-single-crystal structure, resulting in low resistance in the transistor structure to allow the transistor to withstand the high current load required to drive the switching current in a spin-orbit moment MRAM system. Figure 12 As can be seen, the deposition or growth of semiconductor material can cause a portion of the semiconductor material to extend out of the opening 802. Alternatively, semiconductor growth can be terminated before the semiconductor material 1202 reaches the top of the opening, after which doped semiconductor material can be deposited, as will be seen.

[0043] For reference Figure 13 A chemical mechanical polishing process can be performed to planarize the semiconductor material 1202 by removing any semiconductor material extending out of the opening 802 to leave the semiconductor pillar 1202, such as... Figure 13 As shown in the diagram. Additionally, the upper and lower portions of the semiconductor pillar 1202 can be doped to form upper and lower doped semiconductor regions 1302 and 1304. The lower doped portion 1304 can be doped by annealing to cause dopant atoms to diffuse from the source line layer 604 into the lower portion 1304 of the semiconductor material. The upper portion 1302 of the semiconductor pillar 1202 can be doped by ion implantation. Alternatively, the upper portion 1302 of the semiconductor pillar 1202 can be doped by terminating the epitaxial growth of the semiconductor material 1202 before reaching the top of the opening 802 and then performing in-situ deposition of the doped semiconductor material. The doped regions 1302 and 1304 can be n+ doped. The doped regions 1302 and 1304 form the source and drain of the semiconductor channel. After forming the semiconductor pillar 1202 and the doped source and drain regions 1302 and 1304, the upper end of the semiconductor pillar 1202 can be connected to the bit line circuit system BL.

[0044] Figure 14 Showing from Figure 13 An enlarged cross-sectional view as seen in line 14-14. (See also...) Figure 14 As shown, a dielectric layer 1402 may be formed on a substrate 602 extending from end 1404 of the source line layer 604. A spin orbital layer 1406 may be formed above the dielectric layer 1402 and overlap a portion of the source line layer 604. The spin orbital layer 1406 may be formed of a conductive metal, such as β-phase tungsten (W) or β-phase tantalum (Ta). A magnetic memory element 1408 is formed above the spin orbital layer 1406. The magnetic memory element 1408 may be the aforementioned MTJ memory element and may include a magnetic free layer 1410, a non-magnetic barrier layer 1412, and a magnetic reference layer 1414, wherein the magnetic free layer is adjacent to the spin orbital layer 1406.

[0045] The aforementioned semiconductor pillar structure 1202, gate dielectric 804, and gate structure 702 form a write selector transistor 114, as previously mentioned above. Figure 1 As described. Gate structure 702 can be connected to the write word line (write WL) circuitry. As shown, write selector transistor 114 is electrically connected to the bit line circuitry BL and via source line layer 604 to spin-orbit moment layer 1406. Read transistor 116 is also terminally connected to the bit line circuitry BL and magnetic memory element 1408, similar to the previously referenced... Figure 1 A diagram illustrating the discussion.

[0046] During a write operation, the voltage applied by the write WL circuitry disconnects the write transistor 114 to allow current to flow through the spin orbital moment layer 1406 between the bit line BL and the source line circuitry SL, as indicated by the dashed line 1416. In the write state, the read selector transistor switches to the off state. As previously discussed, the flow of current causes electrons to spin polarize on the upper and lower surfaces of the spin orbital moment layer 1406. This spin polarization can be used to apply a spin orbital moment to the free layer 1410 of the memory element 1408 to selectively magnetize the magnetic free layer 1410 in a desired orientation. Depending on the direction of current flow through the spin orbital moment layer 1406, the magnetization orientation of the magnetic free layer 1410 can be switched in one of two directions. As previously discussed, magnetizing the free layer 1410 in one direction sets the magnetic memory element 1408 in a high-resistance state, and magnetizing the free layer 1410 in the opposite direction sets the magnetic memory element 1410 in a low-resistance state. In this way, memory elements rely on their resistance state to safely record data bits.

[0047] In read mode, write selector transistor 114 switches to the off state and read selector transistor 116 switches to the on state to allow electrical connection between bit line BL and memory element 1408. Read selector transistor 116 is controlled by read word line circuitry (read WL), which selectively applies a gate voltage to read selector transistor 116. When read selector transistor 116 is on, a voltage can be applied across the magnetic memory element 1408 between bit line BL and source line SL, which can be used to determine the resistance state of the magnetic memory element.

[0048] Figure 15 The spin orbital moment MRAM according to the alternative embodiment is explained. Figure 15 The embodiment is similar to the one described above, except that the spin-orbit matrix layer 1406 is adjacent to the source layer 604 instead of overlapping it with the source line layer 604. This is achieved by etching into the source line layer 604 and depositing a conductive spin-orbit matrix layer, followed by a chemical mechanical polishing process to planarize the structure before forming the selector transistor 114 and the magnetic memory element 1408. In this embodiment, during a write operation, current flows from the source line layer 604 to the spin-orbit matrix layer and then to the source line circuitry SL, as indicated by arrow 1502.

[0049] Although various embodiments have been described above, it should be understood that they are illustrative only and not limiting. Those skilled in the art will also appreciate other embodiments falling within the scope of this invention. Therefore, the breadth and scope of this invention should not be limited to any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A data recording device, comprising: Magnetic memory element having a magnetic free layer; A conductive spin orbital layer is formed on a substrate and isolated from the substrate by a dielectric layer, the magnetic memory element is formed on the spin orbital layer, and the magnetic free layer is formed directly adjacent to the spin orbital layer. A conductive source electrode layer is formed on or in the substrate and adjacent to the dielectric layer, wherein the spin orbital layer overlaps a portion of the source electrode layer, and the source electrode layer is electrically connected to the spin orbital layer through the overlapping portion of the spin orbital layer. and A vertical transistor structure formed on and electrically connected to the source line layer, the vertical transistor structure being configured to selectively supply current to the spin-orbit moment layer.

2. The data recording device according to claim 1, wherein the vertical transistor structure further comprises: Semiconductor pillars formed on the substrate; A gate dielectric layer that surrounds the semiconductor pillar; and A conductive gate layer is adjacent to the gate dielectric layer, such that the gate dielectric layer separates the conductive gate layer from the semiconductor pillar.

3. The data recording apparatus according to claim 2, wherein the semiconductor pillar has a first and a second doped end.

4. The data recording apparatus according to claim 2, wherein the semiconductor pillar has a first and a second n+ doped portion.

5. The data recording device according to claim 2, wherein the semiconductor pillar comprises an epitaxially grown semiconductor material.

6. The data recording device according to claim 2, wherein the semiconductor pillar comprises a single-crystal semiconductor material.

7. The data recording apparatus of claim 1, wherein the vertical transistor structure is a write selector transistor, and the data recording apparatus further includes a read selector transistor electrically connected to the magnetic memory element.

8. The data recording apparatus of claim 7, wherein the read selector transistor is connected to the magnetic memory element at the end opposite to the spin orbital layer.

9. The data recording device according to claim 1, wherein the magnetic memory element is a magnetic tunnel junction element.

10. The data recording apparatus of claim 7, further comprising conductive bit lines electrically connected to the read selector transistor and the write selector transistor, wherein the spin orbital layer is electrically connected to the magnetic memory element.

11. The data recording apparatus of claim 2, further comprising a write word line circuit system electrically connected to the conductive gate layer.

12. The data recording apparatus according to claim 1, wherein the spin orbital moment layer comprises one or more of β phase W or β phase Ta.

13. A data recording device, comprising: Semiconductor substrate; A source line layer is formed on the semiconductor substrate; A vertical transistor structure is formed on the source line layer and is directly electrically connected to the source line layer formed in the semiconductor substrate; A spin orbital moment layer, formed in the semiconductor substrate and adjacent to the source line layer, to establish a direct electrical connection with the source line layer within the semiconductor substrate; and Magnetic memory element formed on the spin orbital matrix.

14. The data recording device according to claim 13, wherein the magnetic memory element is a magnetic tunnel junction element.

15. The data recording apparatus of claim 13, wherein the magnetic memory element is a magnetic tunnel junction element comprising a magnetic free layer, and wherein the magnetic free layer is adjacent to the spin-orbit moment layer.

16. The data recording apparatus of claim 13, wherein the spin orbital moment layer comprises one or more of β phase W or β phase Ta.

17. The data recording apparatus of claim 13, wherein the vertical transistor structure further comprises: A semiconductor pillar having upper and lower doped regions; A gate dielectric layer is formed on the side of the semiconductor pillar; and A gate structure is formed such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

18. The data recording apparatus of claim 17, wherein the gate dielectric layer surrounds the semiconductor pillar and the gate structure further includes a conductive layer located between the first and second dielectric layers.

19. The data recording apparatus of claim 18, further comprising a write word line circuit system electrically connected to the conductive layer of the gate structure.

20. The data recording apparatus of claim 19, further comprising a read transistor and a conductive bit line electrically connected to the vertical transistor structure and the read transistor.

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