A server backplane and a server

Abstract

The application provides a server backboard and a server. The server backboard comprises a main control chip and a plurality of NVME hard disks. The main control chip is used for performing service management on each NVME hard disk through an I2C bus connected between each NVME hard disk. The main control chip performs data communication with a mainboard BMC through the I2C bus. The server backboard provided by the above scheme introduces the main control chip, realizes decoupling design of uplink and the mainboard BMC, overall management of the downlink on the backboard, and when the mainboard BMC is matched with the server backboard, only communication connection needs to be established with the main control chip, so that the development cost of the mainboard BMC is reduced.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a server backplane and a server. Background Technology

[0002] Backplanes are an indispensable component in server architecture design. When assembling servers, different types of backplanes are required depending on the customer's needs, such as 2-port backplanes, 4-port backplanes, or 8-port backplanes.

[0003] In related technologies, when using different types of backplanes, in order to manage the backplane, the motherboard BMC needs to first determine the backplane type and then adapt the communication between the two for the specific backplane type. The motherboard BMC communicates with the backplane via the I2C bus.

[0004] However, different backplane designs have different devices connected under the I2C and different numbers of NVMe drives. This design difference means that the motherboard BMC needs to adapt the I2C link according to the backplane type when adapting to different backplanes, which increases the development cost of the motherboard BMC. Therefore, there is an urgent need for a server backplane with strong compatibility, which is of great significance to reducing the development cost of the motherboard BMC. Summary of the Invention

[0005] This application provides a server backplane and a server to address the shortcomings of related technologies, such as increased development costs of the motherboard BMC.

[0006] The first aspect of this application provides a server backplane, including: a main control chip and a plurality of NVMe hard drives;

[0007] The main control chip is used to perform business management on each of the NVMe hard drives through the I2C bus connected to each of the NVMe hard drives;

[0008] The main control chip communicates with the motherboard BMC via the I2C bus.

[0009] In some alternative embodiments, the main control chip is an MCU that supports ADC functionality and has built-in flash memory.

[0010] In some optional embodiments, the main control chip is specifically used for:

[0011] Data read and write operations can be performed directly on each of the NVME hard drives via the I2C bus connected to each of the NVME hard drives.

[0012] In some optional embodiments, the main control chip is used for:

[0013] Monitor the voltage of each NVMe hard drive and generate a voltage monitoring log for each NVMe hard drive.

[0014] In some optional embodiments, the main control chip is used for:

[0015] Monitor the current of each NVMe hard drive and generate a current monitoring log for each NVMe hard drive.

[0016] In some optional embodiments, the main control chip is used for:

[0017] Record the server backplane's operation logs.

[0018] In some optional embodiments, the server backplane further includes: a transistor;

[0019] The main control chip is used to monitor the voltage of the transistor and determine the temperature of the server backplane based on the voltage monitoring results of the transistor.

[0020] In some optional embodiments, the main control chip is used for:

[0021] Partition storage server backplane attribute information, NVMe hard drive attribute information, and backplane log data.

[0022] In some optional embodiments, the I2C register interaction specification of the main control chip is determined based on the maximum number of NVMe hard drives on the server backplane.

[0023] A second aspect of this application provides a server, including: a server motherboard and a server backplane as described in the first aspect and various possible designs of the first aspect;

[0024] The server motherboard includes a motherboard BMC, and an I2C bus is provided between the motherboard BMC and the main control chip on the server backplane so that the motherboard BMC and the main control chip can communicate data through the I2C bus.

[0025] The technical solution of this application has the following advantages:

[0026] This application provides a server backplane and a server. The server backplane includes a main control chip and a plurality of NVMe hard drives. The main control chip is used to perform service management on each NVMe hard drive via an I2C bus connected to each of the NVMe hard drives. The main control chip communicates with the motherboard BMC via the I2C bus. The server backplane provided by the above solution achieves decoupling of the uplink from the motherboard BMC by introducing a main control chip, and provides overall downlink management of the backplane. When the motherboard BMC is paired with this server backplane, it only needs to establish a communication connection with the main control chip, reducing the development cost of the motherboard BMC. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0028] Figure 1 This is a schematic diagram of the structure of a traditional server backplane;

[0029] Figure 2 This is a schematic diagram of the structure of a server backplane provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of another server backplane structure provided in an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of another server backplane provided in an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the server structure provided in an embodiment of this application.

[0033] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the following descriptions of embodiments, "a plurality of" means two or more, unless otherwise explicitly defined.

[0036] like Figure 1The diagram shows the structure of a traditional server backplane, where the motherboard BMC communicates with the backplane via the I2C bus. Different backplane designs have different devices connected to the I2C bus, varying numbers of NVMe hard drives, and different I2C topologies. These design differences require the BMC to adapt the I2C link according to the backplane type, increasing the complexity of the motherboard BMC software design. Furthermore, even backplanes of the same type may have differences in hardware I2C addresses, further increasing design difficulty and development costs for the motherboard BMC.

[0037] To address the aforementioned issues, this application provides a server backplane and server, comprising: a main control chip and several NVMe hard drives; the main control chip is used to perform service management on each NVMe hard drive via an I2C bus connected to each of the NVMe hard drives; the main control chip communicates with the motherboard BMC via the I2C bus. The server backplane provided by the above solution, by introducing a main control chip, achieves a decoupling design between the uplink and the motherboard BMC, and provides overall downlink management of the backplane. When the motherboard BMC is paired with this server backplane, it only needs to establish a communication connection with the main control chip, reducing the development cost of the motherboard BMC.

[0038] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0039] This application provides a server backplane to reduce the development cost of the motherboard BMC, such as... Figure 2 The diagram shown is a structural schematic of a server backplane provided in an embodiment of this application. The server backplane includes a main control chip and several NVMe hard drives.

[0040] The main control chip is used to perform business management on each NVME hard drive through the I2C bus connected to each NVME hard drive; the main control chip communicates with the motherboard BMC through the I2C bus.

[0041] Specifically, a main control chip can be introduced into the server backplane. This main control chip is connected to each NVMe hard drive on the server backplane via an I2C bus. By configuring the communication link between the main control chip and each NVMe hard drive, the main control chip can perform service management on each NVMe hard drive through the I2C bus. Service management includes at least data read and write operations on the NVMe hard drives. An I2C bus is also provided between the main control chip and the motherboard BMC, enabling data communication between them, thereby allowing the motherboard BMC to control and manage the server backplane.

[0042] Specifically, in one embodiment, the main control chip is a microcontroller unit (MCU) that supports ADC function and has built-in flash memory. The ADC function refers to the function of converting continuously changing analog signals into discrete digital signals. Specifically, the main control chip can directly perform data read and write operations on each of the NVME hard drives through the I2C bus connected to each of the NVME hard drives.

[0043] Specifically, because the MCU is programmable, the embodiments of this application can be omitted in the server backplane hardware design. Figure 1 The I2C SWITCH chip in the traditional server backplane shown uses the GPIO of the MCU to simulate the I2C master function, so as to directly perform data read and write operations on each of the NVME hard drives.

[0044] Based on the above embodiments, in traditional server backplane designs, voltage fluctuations can lead to problems such as disk failures. When this problem occurs in a server room, the inability to quickly locate the problem can severely disrupt server operations.

[0045] To address the aforementioned technical problems, the embodiments of this application, while reducing the development cost of the motherboard BMC, fully utilize the flexibility and functional diversity of MCU design. On the one hand, this increases the functionality of the server backplane; on the other hand, it reduces the design cost of the server backplane. Figure 3 This is a schematic diagram of another server backplane structure provided in an embodiment of this application. As an implementable approach, in one embodiment, the main control chip can monitor the voltage of each NVMe hard drive and generate voltage monitoring logs for each NVMe hard drive.

[0046] Specifically, such as Figure 3 As shown, the main control chip (MCU) includes an ADC module, which specifically refers to an analog-to-digital converter used for sensor data acquisition. The ADC module can be connected to the backplane power supply (12V) to monitor its voltage. Since the backplane power supply powers each NVMe hard drive, the voltage monitoring results can be used as the voltage monitoring results for each NVMe hard drive, and the timestamps of the voltage monitoring are recorded to generate voltage monitoring logs for each NVMe hard drive. When voltage fluctuations occur during system operation, the generated voltage monitoring logs can be used to trace abnormal issues such as disk failures.

[0047] Specifically, in one embodiment, the main control chip can monitor the current of each of the NVMe hard drives and generate a current monitoring log for each of the NVMe hard drives.

[0048] Specifically, the main control chip (MCU) can use an ADC module connected to the backplane power supply (12V) to monitor the current of the backplane power supply, obtain the current monitoring results of each NVMe hard drive, and then generate corresponding current monitoring logs. Furthermore, based on the obtained voltage and current monitoring results, the overall power consumption of the server backplane can be determined and recorded.

[0049] Specifically, in one embodiment, the main control chip internally sets a power monitoring threshold. When the voltage or current monitoring result of the power supply exceeds the corresponding threshold, the main control chip records the abnormal voltage or current value and prints a timestamp to achieve real-time monitoring of the power supply and recording of abnormal data. When the server experiences abnormal problems such as disk failure, the voltage anomaly can be quickly located based on the log analysis. The server backplane provided in this application fully utilizes the ADC function of the MCU to monitor the voltage and current of the NVMe hard drive on the server backplane and record logs, achieving real-time monitoring and logging of voltage fluctuations and other issues, thus improving the traceability of server backplane faults. This application introduces an MCU as the main control chip in the server backplane hardware design, which can successfully replace IC devices such as CPLD, EEPROM, and I2C SWITCH. At the same time, it adds functions such as voltage and current monitoring of the server backplane. From both material cost and functional perspectives, this is a significant improvement over traditional server backplanes.

[0050] Specifically, in one embodiment, the CPIO port of the main control chip is connected to the indicator light on the server backplane, which is used to provide an abnormal fault alarm through the indicator light when an abnormal fault occurs on the server backplane.

[0051] Specifically, in one embodiment, the main control chip can record the operation logs of the server backplane.

[0052] It should be noted that when the main control chip has built-in flash memory, the flash memory can replace... Figure 1 The EEPROM shown in the traditional server backplane is used to record the server backplane's operation logs.

[0053] The server backplane's operation log includes at least records of the insertion and removal of the NVMe hard drives on the server backplane. The operation log can be used to trace abnormal failures of the server backplane.

[0054] Specifically, in one embodiment, such as Figure 3 As shown, the server backplane also includes a transistor-based main control chip, used to monitor the voltage of the transistor and determine the temperature of the server backplane based on the voltage monitoring results of the transistor.

[0055] It should be noted that the voltage of a transistor changes with temperature.

[0056] Specifically, the main control chip includes an ADC module, which can be connected to a transistor to monitor the transistor's voltage. Then, based on the voltage-temperature correspondence represented by the transistor's attribute information, the temperature of the server backplane is determined according to the transistor's voltage monitoring results.

[0057] To ensure the accuracy of the final server backplane temperature, data calibration can be performed based on the main control chip, such as by taking the average value, to determine the server backplane temperature.

[0058] Specifically, in one embodiment, the main control chip can partition and store server backplane attribute information, NVME hard disk attribute information, and backplane log data.

[0059] Specifically, the flash memory of the main control chip replaces the EEPROM in the traditional server backplane and is used to store server backplane attribute information, NVME hard disk attribute information, and backplane log data.

[0060] The server backplane attribute information includes at least the manufacturer part number and board specifications of the server backplane, the NVMe hard drive attribute information includes at least the manufacturer, model and capacity of each NVMe hard drive, and the backplane log data includes at least the server backplane operation log, voltage monitoring log and current monitoring log, that is, storing the voltage value, current value, power consumption and NVMe hard drive insertion and removal records of the server backplane power supply, and may also include the server backplane temperature monitoring data.

[0061] Specifically, in order to improve the data management efficiency of the backplane server, the server backplane attribute information, NVMe hard disk attribute information and backplane log data can be partitioned and stored to facilitate subsequent data management.

[0062] It should be noted that the server backplane design scheme provided in this application embodiment can also be applied to other server boards. The specific design can be adapted according to the actual application. This application embodiment does not limit the design.

[0063] Based on the above embodiments, in order to reduce the development cost of the server backplane, such as Figure 4 This is a schematic diagram of another server backplane structure provided in an embodiment of the present application. As an implementable approach, in one embodiment, the I2C register interaction specification of the main control chip is determined according to the upper limit number of NVME hard drives on the server backplane.

[0064] like Figure 4As shown, the main control chip (MCU) includes a register, a data control module, flash memory, an I2C master, and an ADC module. Specifically, the I2C master design can be implemented based on the MCU code. This is used to read information from the NVMe hard drive, manage NVMe drive operations, and selectively store relevant information in flash memory or directly transmit it to the motherboard BMC via the register, depending on the importance of the NVMe hard drive information. MCU chips generally have built-in ADC functionality; for example, using an MCU that supports an 8-channel ADC can monitor the voltage and current of the NVMe hard drive's power supply (12V).

[0065] Specifically, the motherboard BMC communicates with the main control chip on the server backplane via the I2C bus. This means the BMC only communicates with the backplane MCU and does not connect any other I2C devices. The main control chip provides unified management of the server backplane and caches relevant data in its internal SRAM or flash memory. A complete I2C interaction document is defined between the main control chip and the motherboard BMC, covering all types of backplane interaction data. The BMC only needs to implement one set of code to achieve functional adaptation for all types of backplanes.

[0066] For example, taking the commonly used 2-port, 4-port, and 8-port backplanes in server architecture as examples, the maximum number of hard drives supported by a server backplane is 8, meaning the maximum number of NVMe hard drives on a server backplane is 8. Therefore, the data for an 8-port backplane can be fully defined in the I2C register interaction specification between the motherboard BMC and the main control chip, thus ensuring backward compatibility with 2-port and 4-port backplanes. The table below shows an example register interaction specification. This address can be expanded according to actual needs; this table only illustrates the maximum 8-port backplane as an example.

[0067]

[0068]

[0069] This application provides a server backplane, which includes a main control chip and several NVMe hard drives. The main control chip manages the NVMe hard drives via an I2C bus connected to each NVMe hard drive. The main control chip also communicates with the motherboard BMC via the I2C bus. The server backplane provided by this solution achieves decoupling between the uplink and the motherboard BMC by introducing a main control chip, while providing overall downlink management of the backplane. When the motherboard BMC is paired with this server backplane, it only needs to establish a communication connection with the main control chip, reducing the development cost of the motherboard BMC. Furthermore, by introducing an MCU as the main control chip into the server backplane hardware design, it allows for the replacement of IC devices such as CPLD, EEPROM, temperature sensor, and I2C switch, while also adding power supply voltage and power consumption monitoring. This not only saves material costs but also improves the performance of the server backplane. Meanwhile, by unifying the register interaction specifications between the motherboard BMC and the MCU, the decoupled design of the motherboard BMC and the backplane can be achieved. After changing the server backplane type, the motherboard BMC does not need to be adapted, further reducing the development cost of the motherboard BMC.

[0070] This application provides a server, such as Figure 5 The diagram shown is a structural schematic of a server provided in an embodiment of this application. The server includes: a server motherboard and a server backplane provided in the above embodiment.

[0071] The server motherboard includes a motherboard BMC, and an I2C bus is provided between the motherboard BMC and the main control chip on the server backplane so that the motherboard BMC and the main control chip can communicate data through the I2C bus.

[0072] The specific implementation of the server in this embodiment has been described in detail in the embodiments concerning the server backplane, and will not be elaborated here.

[0073] The server provided in this application embodiment includes a server motherboard and a server backplane. The server motherboard includes a motherboard BMC, and an I2C bus is provided between the motherboard BMC and the main control chip of the server backplane to enable data communication between the motherboard BMC and the main control chip through the I2C bus. The server backplane includes the main control chip and several NVMe hard drives. The main control chip is used to perform business management on each NVMe hard drive through the I2C bus connected to each NVMe hard drive. The server provided by the above solution achieves decoupling design between the uplink and the motherboard BMC by introducing a main control chip into the server backplane, and overall management of the backplane for downlink. When the motherboard BMC is paired with this server backplane, it only needs to establish a communication connection with the main control chip, reducing the development cost of the motherboard BMC. Furthermore, by introducing an MCU as the main control chip into the server backplane hardware design, IC devices such as CPLD, EEPROM, temperature sensor, and I2C SWITCH are replaced, while power supply voltage and power consumption monitoring are added. This not only saves material costs but also improves the performance of the server backplane. Meanwhile, by unifying the register interaction specifications between the motherboard BMC and the MCU, the decoupled design of the motherboard BMC and the backplane can be achieved. After changing the server backplane type, the motherboard BMC does not need to be adapted, further reducing the development cost of the motherboard BMC.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A server backplane, characterized in that, include: The main control chip and several NVMe hard drives; The main control chip is used to perform business management on each of the NVMe hard drives through the I2C bus connected to each of the NVMe hard drives; The main control chip communicates with the motherboard BMC via the I2C bus; The main control chip is an MCU that supports ADC function and has built-in flash memory; The I2C register interaction specification of the main control chip is determined according to the maximum number of NVMe hard drives on the server backplane. The main control chip includes registers, a data center, flash memory, an I2C initiator, and an ADC module. The main control chip implements an I2C master design based on MCU code to read information from the NVMe hard drive and realize the business management of the NVMe hard drive.

2. The server backplane according to claim 1, characterized in that, The main control chip is specifically used for: Data read and write operations can be performed directly on each of the NVME hard drives via the I2C bus connected to each of the NVME hard drives.

3. The server backplane according to claim 1, characterized in that, The main control chip is used for: Monitor the voltage of each NVMe hard drive and generate a voltage monitoring log for each NVMe hard drive.

4. The server backplane according to claim 1, characterized in that, The main control chip is used for: Monitor the current of each NVMe hard drive and generate a current monitoring log for each NVMe hard drive.

5. The server backplane according to claim 1, characterized in that, The main control chip is used for: Record the server backplane's operation logs.

6. The server backplane according to claim 1, characterized in that, The server backplane also includes: a transistor; The main control chip is used to monitor the voltage of the transistor and determine the temperature of the server backplane based on the voltage monitoring results of the transistor.

7. The server backplane according to claim 1, characterized in that, The main control chip is used for: Partition storage server backplane attribute information, NVMe hard drive attribute information, and backplane log data.

8. A server, characterized in that, include: Server motherboard and server backplane as described in any one of claims 1 to 7; The server motherboard includes a motherboard BMC, and an I2C bus is provided between the motherboard BMC and the main control chip on the server backplane so that the motherboard BMC and the main control chip can communicate data through the I2C bus.

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