Circuitry

Abstract

A circuit system includes a multi-mode switch multiplexer, a control circuit and a receiver. The multi-mode switch multiplexer is configured to receive a plurality of mode settings from firmware and select one of the plurality of mode settings as an output mode setting. The control circuit is configured to generate a mode switch signal to control the multi-mode switch multiplexer. The receiver is configured to set its internal elements according to the output mode setting.

Description

Technical Field

[0001] This invention relates to a circuit system capable of rapidly switching modes. Background Technology

[0002] The DisplayPort (DP) specification introduces Advanced Link Power Management (ALPM), which requires display devices to quickly exit sleep mode and enter subsequent modes. Since these modes involve the control of hardware components, and different modes require different settings for component control, generally, after deciding to switch to a different mode, firmware transmits control signals corresponding to that mode to the receiver to control the components. However, this firmware-based processing is quite time-consuming, thus affecting the speed of mode switching. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a circuit system capable of rapid mode switching to solve the problems described in the prior art.

[0004] In one embodiment of the present invention, a circuit system is disclosed, comprising a multi-mode switching multiplexer, a control circuit, and a receiver. The multi-mode switching multiplexer is configured to receive multiple mode settings from firmware and select one of the multiple mode settings as the output mode setting; the control circuit is configured to generate a mode switching signal to control the multi-mode switching multiplexer, and the receiver is configured to configure its internal components according to the output mode setting. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a circuit system according to an embodiment of the present invention.

[0006] Figure 2 This is a multi-mode switching multiplexer and its corresponding timing diagram according to an embodiment of the present invention.

[0007] Figure 3 This is a schematic diagram showing the operation of components within the receiver when the circuit system is in sleep mode.

[0008] Figure 4 This is a schematic diagram of the operation of components within the receiver when the circuit system is in wake-up mode.

[0009] Figure 5 This is a schematic diagram showing the operation of components within the receiver when the circuit system is in receive mode. Detailed Implementation

[0010] Figure 1This is a schematic diagram of a circuit system 100 according to an embodiment of the present invention. Figure 1 As shown, the circuit system 100 includes a receiver 110, a detection circuit 120, a control circuit 130, a multi-mode switching multiplexer 140, a microprocessor 150, and a storage element 160, wherein the storage element 160 includes program code 162. In this embodiment, the circuit system 100 is located at the receiving end of the display, and the circuit system 100 supports the DisplayPort (DP) standard, and the circuit system 100 can be used to receive DP signals and perform subsequent processing.

[0011] The circuit system 100 can operate in multiple different modes, and the receiver 110 will have different settings in different modes. In this embodiment, the circuit system 100 can operate in three different modes. When the circuit system 100 operates in the first mode, the receiver 110 uses mode setting S1 to set the internal components. When the circuit system 100 operates in the second mode, the receiver 110 uses mode setting S2 to set the internal components. When the circuit system 100 operates in the third mode, the receiver 110 uses mode setting S3 to set the internal components. Each of mode settings S1, S2, and S3 includes multiple different control bits / signals. In order to enable the receiver 110 to quickly obtain the required mode settings S1 / S2 / S3 for internal component settings during mode switching, the microprocessor 150 in this embodiment generates three mode settings S1, S2, and S3 to the multi-mode switching multiplexer 140 after executing program code 162 (i.e., firmware, or software). The three mode settings S1, S2, and S3 are written to the input terminal of the multi-mode switching multiplexer 140. When the circuit system 100 needs to perform mode switching, the control circuit 130 generates mode switching signals Vc1 and Vc2 to the multi-mode switching multiplexer 140, so that the multi-mode switching multiplexer 140 can directly use one of the mode settings S1, S2, and S3 as the output mode setting SC for use by the receiver 110.

[0012] In this embodiment, since the firmware directly writes the three mode settings S1, S2, and S3 to the input of the multi-mode switching multiplexer 140, and these three mode settings S1, S2, and S3 remain continuously present at the input of the multi-mode switching multiplexer 140 during the operation of the circuit system 100, when the circuit system 100 needs to switch to different modes (e.g., from the first mode to the second mode), the control circuit 130 can generate mode switching signals Vc1 and Vc2 to directly control the multi-mode switching multiplexer 140 to output different mode settings, without requiring the microprocessor 150 to output different mode settings separately based on the mode switch. As described above, since the operation of outputting different mode settings S1 / S2 / S3 during mode switching in this embodiment can be completed solely through hardware circuitry without firmware intervention, the purpose of rapid mode switching can be achieved.

[0013] In this embodiment, the circuit system 100 is located on the display. When the display is powered on and the circuit system 100 is powered on, the microprocessor 150 writes the mode settings S1, S2, and S3 to the input of the multi-mode switching multiplexer 140, even if the circuit system 100 does not need to operate in the first, second, and third modes mentioned above. This ensures that in subsequent operations of the circuit system 100, the microprocessor 150 does not need to spend time writing the mode settings S1, S2, and S3 to the multi-mode switching multiplexer 140.

[0014] Figure 2 This is a multi-mode switching multiplexer 140 and its corresponding timing diagram according to an embodiment of the present invention. Figure 2 As shown, the multi-mode switching multiplexer 140 includes multiplexers 210 and 220. Multiplexer 210 receives mode settings S1 and S2, and selects one of mode settings S1 and S2 for output according to mode switching signal Vc1. Multiplexer 220 receives mode setting S3 and the output of multiplexer 210, and selects one of mode setting S3 and the output of multiplexer 210 for output according to mode switching signal Vc2. For example, when both mode switching signals Vc1 and Vc2 are at low voltage levels, the multi-mode switching multiplexer 140 selects mode setting S1 as the output mode setting SC; when mode switching signals Vc1 and Vc2 are at high and low voltage levels respectively, the multi-mode switching multiplexer 140 selects mode setting S2 as the output mode setting SC; and when mode switching signal Vc2 is at a high voltage level, the multi-mode switching multiplexer 140 selects mode setting S3 as the output mode setting SC. It should be noted that the mode switching signals Vc1 and Vc2 and their corresponding mode settings are merely illustrative examples and not limitations of the invention.

[0015] In the embodiment, the first mode, the second mode, and the third mode of the circuit system 100 are respectively sleep mode, wake-up mode, and receive mode, and Figure 1 , Figure 2 The mode settings S1, S2, and S3 shown correspond to sleep mode, wake-up mode, and receive mode, respectively. Specifically, when the circuit system 100 enters sleep mode, the transmitting end located outside the system circuit 100 transmits data containing sleep information to the receiver 110. The receiver 110 then transmits the received data to the control circuit 130 for interpretation. If the control circuit 130 determines that the received data indicates that it should enter sleep mode, the control circuit 130 will output mode switching signals Vc1 and Vc2 to the multi-mode switching multiplexer 140 to select mode setting S1 as the output mode setting SC for setting the receiver 110.

[0016] Figure 3 This is a schematic diagram illustrating the operation of components within the receiver 110 when the circuit system 100 is in sleep mode. Figure 3 As shown, receiver 110 includes switch SW1, equalizer 310, analog-to-digital converter 320, processing circuit 330, clock generation circuit 340, and bias generation circuit 350. Under the control of mode setting S1, equalizer 310, analog-to-digital converter 320, processing circuit 330, and clock generation circuit 340 stop operating. However, since bias generation circuit 350 requires a relatively long time to generate a stable bias voltage after power-on or wake-up, bias generation circuit 350 will still generate bias voltage to equalizer 310, analog-to-digital converter 320, and clock generation circuit 340 in sleep mode.

[0017] Furthermore, when the circuit system 100 is operating in sleep mode, Figure 1 The detection circuit 120, control circuit 130, and multi-mode switching multiplexer 140 will still operate normally to ensure that subsequent wake-up signals can be received and mode switching can be performed.

[0018] Next, when the circuit system 100 needs to be woken up, the transmission terminal located outside the system circuit 100 will transmit a wake-up signal, such as a low frequency periodic signal (LFPS). The detection circuit 120 will detect this wake-up signal and generate a detection result to the control circuit 130 for judgment. When the control circuit 130 determines the wake-up signal, the control circuit 130 will output the mode switching signals Vc1 and Vc2 to the multi-mode switching multiplexer 140 to select mode setting S2 as the output mode setting SC for setting the receiver 110.

[0019] Figure 4 This is a schematic diagram illustrating the operation of components within the receiver 110 when the circuit system 100 is in wake-up mode. For example... Figure 4 As shown, under the control of mode setting S2, the equalizer 310 and analog-to-digital converter 320 start operating to establish bias voltage and operating point. The clock generation circuit 340 switches to phase-locked loop (PLL) mode to oscillate the clock signal to near the required frequency for supply to the analog-to-digital converter 320. In wake-up mode, the receiver 110 still has not received any audio or video data from the outside.

[0020] Then, after a period of time after the circuit system 100 enters the wake-up mode, the circuit system 100 prepares to enter the receiving mode. At this time, the control circuit 130 will output the mode switching signals Vc1 and Vc2 to the multi-mode switching multiplexer 140 to select the mode setting S3 as the output mode setting SC for setting the receiver 110. Figure 5 This is a schematic diagram illustrating the operation of components within receiver 110 when circuit system 100 is operating in receive mode. For example... Figure 5 As shown, under the control of mode setting S3, the clock generation circuit 340 operates in Clock and Data Recovery Circuit (CDR) mode, and at this time, the receiver 110 begins to operate normally to receive audio and video data from the outside. Specifically, the equalizer 310 receives the input signal (audio and video signal) from the outside to generate an equalized signal. The analog-to-digital converter 320 performs analog-to-digital conversion on the equalized signal to generate a digital signal to the processing circuit 330. The processing circuit 330 can process the received digital signal and transmit it to the control circuit 130 or other audio and video processing circuits for further processing. The processing circuit 330 also transmits the received digital signal to the clock generation circuit 340 to generate a clock signal.

[0021] As described above, the circuit system 100 of this embodiment is designed to allow the circuit system 100 to switch quickly when it needs to switch to sleep mode, wake-up mode and receive mode, thereby solving the problem of delay caused by firmware intervention in the prior art.

[0022] In this embodiment, the control circuit 130 can be a digital circuit, and the multi-mode switching multiplexer 140 can be an analog circuit. However, in other embodiments, both the control circuit 130 and the multi-mode switching multiplexer 140 can be implemented using digital circuits.

[0023] In summary, the circuit system of this invention uses a multi-mode switching multiplexer to receive multiple mode settings from the firmware upon power-up. During subsequent mode switching, the appropriate mode settings can be generated for component configuration via hardware processing alone, without the need for firmware control. This achieves the goal of rapid mode switching.

[0024] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] 100: Circuit System

[0027] 110: Receiver

[0028] 120: Detection circuit

[0029] 130: Control circuit

[0030] 140: Multi-mode switching multiplexer

[0031] 150: Microprocessor

[0032] 160: Storage element

[0033] 162: Program Code

[0034] Vc1, Vc2: Mode switching signals

[0035] S1, S2, S3: Mode Settings

[0036] SC: Output Mode Settings

[0037] 210, 220: Multiplexers

[0038] 310: Equalizer

[0039] 320: Analog-to-Digital Converter

[0040] 330: Processing Circuit

[0041] 340: Clock Generator Circuit

[0042] 350: Bias voltage generation circuit

[0043] SW1: Switch

Claims

1. A circuit system, comprising: A multi-mode switching multiplexer is used to receive multiple mode settings from the firmware and select one of them as the output mode setting. Control circuitry is used to generate mode switching signals to control the multi-mode switching multiplexer; as well as A receiver is used to receive input signals and transmit the received signals to the control circuit, and also to turn at least one of its internal components on or off according to the output mode setting. These multiple mode settings are written to the receiver of the multi-mode switching multiplexer.

2. The circuit system of claim 1, wherein the multi-mode switching multiplexer receives the multiple mode settings from the firmware when the circuit system is powered on.

3. The circuit system as described in claim 1, wherein after the multiple mode settings are written to the receiving end of the multi-mode switching multiplexer, when the circuit system needs to perform mode switching, the multi-mode switching multiplexer will not receive the multiple mode settings again from the firmware.

4. The circuit system as claimed in claim 1, wherein the control circuit is a digital circuit, the multi-mode switching multiplexer is a digital circuit or an analog circuit, and the control circuit generates the mode switching signal to control the multi-mode switching multiplexer to generate the output mode setting without involving the control of the firmware.

5. The circuit system of claim 1, wherein the plurality of mode settings include a first mode setting, a second mode setting, and a third mode setting, and the control circuit generates a first mode switching signal and a second mode switching signal to control the multi-mode switching multiplexer; Furthermore, this multi-mode switching multiplexer includes: A first multiplexer is configured to receive the first mode setting and the second mode setting, and select one of the first mode setting and the second mode setting as the output of the first multiplexer according to the first mode switching signal; as well as The second multiplexer is used to receive the third mode setting and the output of the first multiplexer, and select one of the third mode setting and the output of the first multiplexer as the output mode setting according to the second mode switching signal.

6. The circuit system of claim 1, wherein the circuit system is operable in a sleep mode, a wake-up mode, and a receive mode, the plurality of mode settings including a first mode setting corresponding to the sleep mode, a second mode setting corresponding to the wake-up mode, and a third mode setting corresponding to the receive mode.

7. The circuit system of claim 6, further comprising: Detection circuit; When the receiver receives the input signal and the control circuit determines that the input signal indicates the sleep mode, the circuit system operates in the sleep mode, and the control circuit generates the mode switching signal to control the multi-mode switching multiplexer to select the first mode setting as the output mode setting to configure the receiver; when the circuit system operates in the sleep mode and the detection circuit receives the wake-up signal, the circuit system switches to the wake-up mode, and the control circuit generates the mode switching signal to control the multi-mode switching multiplexer to select the second mode setting as the output mode setting to configure the receiver. And after the circuit system operates in the wake-up mode for a period of time, the circuit system switches to the receive mode, and the control circuit generates the mode switching signal to control the multi-mode switching multiplexer to select the third mode setting as the output mode setting to set the receiver.

8. The circuit system of claim 7, wherein the receiver includes an equalizer, an analog-to-digital converter, and a clock generation circuit; when the circuit system operates in the sleep mode, the receiver disables the equalizer, the analog-to-digital converter, and the clock generation circuit according to the first mode setting; when the circuit system operates in the wake-up mode, the receiver enables the equalizer, the analog-to-digital converter, and the clock generation circuit according to the second mode setting, and the clock generation circuit operates in a phase-locked loop mode; and when the circuit system operates in the receive mode, the clock generation circuit operates in a frequency and data recovery mode.

9. The circuit system of claim 1, wherein the circuit system supports the display interface standard.

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