Multi-channel memory device

Abstract

The present application provides a multi-channel memory device including N first memory blocks, a first spare memory block, and N first interface circuits. Each first interface circuit is coupled to two of the first memory blocks and the first spare memory block. The first interface circuits are configured to select N first selected memory blocks from among the first memory blocks and the first spare memory block to be coupled to a plurality of first input / output interfaces according to a plurality of first selection signals, where N is a positive integer greater than 1.

Description

Technical Field

[0001] This invention relates to a multi-channel memory device, and more particularly to a multi-channel memory device with repair capabilities. Background Technology

[0002] In electronic devices, system-on-a-chip (SoC) demands for memory (such as dynamic random access memory) are constantly evolving towards higher speeds and higher bandwidths. High-bandwidth DRAM chips require a large number of input / output (I / O) interfaces. Therefore, to meet these demands, multi-channel memory devices have been developed, meaning a single chip contains multiple independent memory blocks. Each channel's memory block has a small capacity, but can output large amounts of data simultaneously. However, if one memory block malfunctions, or if the shared power supply experiences an anomaly, the entire chip will malfunction.

[0003] The most direct way to solve the above problems is to add an extra set of spare memory blocks with additional channels and corresponding interface circuitry, but this would cause problems for the memory controller. If the extra interface circuitry is not needed, a data path remapping design must be added, but this would complicate the internal wiring. Summary of the Invention

[0004] This invention relates to a multi-channel memory device that can quickly switch to a backup memory block to replace a damaged memory block.

[0005] According to an embodiment of the present invention, a multi-channel memory device includes N first memory blocks, a first spare memory block, and N first interface circuits. Each first interface circuit is coupled to two of the first memory blocks and the first spare memory blocks. The first interface circuit selects N first selected memory blocks and the first spare memory blocks from the first memory blocks according to a plurality of first selection signals to be coupled to a plurality of first input / output interfaces, where N is a positive integer greater than 1.

[0006] According to the above, the multi-channel memory device of the present invention is provided with a plurality of first interface circuits, and each first interface circuit is coupled to two of the first memory blocks and the first spare memory blocks. When one of the plurality of first memory blocks is damaged, the first interface circuit can adjust the coupling state of the first memory block, the first spare memory block and the plurality of first input / output interfaces, so that the first spare memory block can replace the damaged first memory block. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 , Figure 2 and Figure 5 These are schematic diagrams of multi-channel memory devices according to different embodiments of the present invention;

[0009] Figure 3 This is a schematic diagram of the repair operation of a multi-channel memory device according to an embodiment of the present invention;

[0010] Figure 4A as well as Figure 4B This is a schematic diagram illustrating an embodiment of multiple interface circuits of the present invention.

[0011] Explanation of icon numbers

[0012] 100, 200, 500: Multi-channel memory devices;

[0013] 110~117, 210~217, 521-1, 521-2: Memory blocks;

[0014] 121, 221, 521-1, 521-2: Spare memory blocks;

[0015] 130~137, 230~237, 430~437, 530-1~537-2: Interface circuits;

[0016] 240: Memory;

[0017] 250: Decoder;

[0018] ADDI: Address Information;

[0019] bSW0~bSW7: Reverse signals;

[0020] C <0> ~C <8> : Memory channel;

[0021] DM1, DM2, DM3: Redundant interface circuits;

[0022] ERI: Error message;

[0023] P0~P8: Power supply;

[0024] PD0~PD7: solder pads;

[0025] PWR0~PWR8: Power control signals;

[0026] S11~S82: Switches;

[0027] SW0~SW7: Selection signals. Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0029] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a multi-channel memory device according to an embodiment of the present invention. The multi-channel memory device 100 includes multiple memory blocks 110-117, a spare memory block 121, and multiple interface circuits 130-137. In this embodiment, the number of memory blocks 110-117 can be N, where N is a positive integer greater than 1. In this embodiment, N can be equal to 8. Furthermore, the number of interface circuits 130-137 can be the same as the number of the first memory blocks 110-117.

[0030] In this embodiment, interface circuits 130-137 can be arranged in a row, while memory blocks 110-117 are divided into two groups and respectively located on the two sides of interface circuits 130-137. Specifically, memory blocks 110, 112, 114, and 116 are located on the first side of interface circuits 130-137, while memory blocks 111, 113, 115, and 117 are located on the second side of interface circuits 130-137. In this embodiment, memory blocks 110-117 can each provide eight memory channels.

[0031] Each of interface circuits 130-137 is coupled to two of memory blocks 110-117 and spare memory block 121. Specifically, the i-th interface circuit 130-136 is coupled to the i-th memory blocks 110-116 and the (i+1)-th memory blocks 111-117, where i is a positive integer greater than 0 and less than N. The N-th interface circuit 137 is coupled to the N-th memory block 117 and spare memory block 121. Interface circuits 130-137 are also coupled to corresponding input / output interfaces; in this embodiment, the input / output interfaces can be solder pads.

[0032] In detail, interface circuit 130 is coupled to memory blocks 110 and 111; interface circuit 131 is coupled to memory blocks 111 and 112; interface circuit 132 is coupled to memory blocks 112 and 113; interface circuit 133 is coupled to memory blocks 113 and 114; interface circuit 134 is coupled to memory blocks 114 and 115; interface circuit 135 is coupled to memory blocks 115 and 116; interface circuit 136 is coupled to memory blocks 116 and 117; and interface circuit 137 is coupled to memory block 117 and spare memory block 121.

[0033] Interface circuits 130-137 receive multiple selection signals SW0-SW7 respectively. Interface circuits 130-137 select one of the two corresponding coupled memory blocks (or memory block 117 and spare storage area 121) as the selected memory block according to the selection signals SW0-SW7, and couple the selected memory block to the corresponding input / output interface.

[0034] Selection signals SW0-SW7 are generated based on the damage status of memory blocks 110-117. When memory blocks 110-117 are not damaged, interface circuits 130-137 can select memory blocks 110-117 to be coupled to the corresponding 8 pads respectively, based on selection signals SW0-SW7. When one of memory blocks 110-117 is damaged, interface circuits 130-137 can select signals SW0-SW7 to prevent the damaged memory block from being coupled to any pad, to allow the undamaged memory blocks to be coupled to the 1st to 7th pads in sequence, and to couple the spare memory block 121 to the 8th pad.

[0035] Of course, the eight memory blocks 110-117 in this embodiment are merely illustrative examples. In this embodiment of the invention, the number of memory blocks in the multi-channel memory device 100 is not limited to eight. In other embodiments of the invention, the number of memory blocks can be eight or more, or eight or less, without fixed limitations.

[0036] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of a multi-channel memory device according to another embodiment of the present invention. The multi-channel memory device 200 includes multiple memory blocks 210-217, a spare memory block 221, multiple interface circuits 230-237, redundant interface circuits DM1 and DM2, a memory 240, and a decoder 250. In this embodiment, the memory 240 is used to store error information ERI of the error state of each memory block 210-217. Specifically, when one of the memory blocks 210-217 is found to be in a damaged state, the address information ADDI of the damaged memory block can be written into the memory 240, and the memory 240 can then provide the error information ERI based on the address information ADDI.

[0037] Decoder 250 is coupled to memory 240 to receive error information ERI and decode it to generate selection signals SW0-SW7. Further, decoder 250 can generate inverted signals bSW0-bSW7 and power control signals PWR0-PWR8 based on the selection signals SW0-SW7. The power control signals PWR0-PWR7 can be the same as the selection signals SW0-SW7. When all memory blocks 210-217 are intact, the power control signal PWR8 can be a non-active logic level; conversely, when one of memory blocks 210-217 is damaged, the power control signal PWR8 can be an active logic level.

[0038] In this embodiment, the coupling method of memory blocks 210-217, spare memory block 221, and interface circuits 230-237 is similar to... Figure 1 The embodiments are the same and will not be described in detail here. It is worth mentioning that the multi-channel memory device 200 of this embodiment further provides redundant interface circuits DM1 and DM2 on both sides of the column formed by interface circuits 230-237. The circuit architecture of each of the redundant interface circuits DM1 and DM2 is the same as that of each of the interface circuits 230-237. Through the redundant interface circuits DM1 and DM2, the load coupled to all memory blocks 210-217 and the backup memory block 221 can be consistent.

[0039] Furthermore, in this embodiment, memory blocks 210-217 and spare memory block 221 each have a power channel to receive power supplies P0-P8. On the other hand, memory blocks 210-217 and spare memory block 221 can determine whether to receive power supplies P0-P8 respectively based on power control signals PWR0-PWR8.

[0040] When all memory blocks 210-217 are tested and found to be in a normal state, decoder 250 decodes the error message ERI to generate selection signals SW0-SW7, their inverted signals bSW0-bSW7, and power control signals PWR0-PWR8. Selection signals SW0-SW7 and their inverted signals bSW0-bSW7 are transmitted to interface circuits 230-237, respectively, while power control signals PWR0-PWR8 are transmitted to memory blocks 210-217 and spare memory block 221, respectively. At this time, interface circuit 230 couples memory block 210 to the corresponding pad; interface circuit 231 couples memory block 211 to the corresponding pad; interface circuit 232 couples memory block 212 to the corresponding pad; interface circuit 233 couples memory block 213 to the corresponding pad; interface circuit 234 couples memory block 214 to the corresponding pad; interface circuit 235 couples memory block 215 to the corresponding pad; interface circuit 236 couples memory block 216 to the corresponding pad; and interface circuit 237 couples memory block 217 to the corresponding pad. Furthermore, memory blocks 210 to 217 receive power from P0 to P7 according to power control signals PWR0 to PWR7, respectively, while the spare memory block 221 cuts off the power P8 receiving channel according to power control signal PWR8.

[0041] On the other hand, when one of memory blocks 210-217 is found to be corrupted, please refer to [link to relevant documentation]. Figure 3 This is a schematic diagram illustrating the repair operation of a multi-channel memory device according to an embodiment of the present invention. Figure 3 In this example, memory block 212 is considered a damaged memory block. Based on selection signals SW0-SW7 and their inverse signals bSW0-bSW7, interface circuit 230 can select memory block 210 to couple to the first pad; interface circuit 231 can select memory block 211 to couple to the second pad; interface circuit 232 can select memory block 213 to couple to the third pad; interface circuit 233 can select memory block 214 to couple to the fourth pad; interface circuit 234 can select memory block 215 to couple to the fifth pad; interface circuit 235 can select memory block 216 to couple to the sixth pad; interface circuit 236 can select memory block 217 to couple to the seventh pad; and interface circuit 237 can select spare memory block 221 to couple to the eighth pad.

[0042] On the other hand, according to the power control signals PWR0 to PWR8, the power channel of memory block 212 receiving power P2 can be cut off. The power channels of memory blocks 210 to 211 and 213 to 217 receiving power P0 to P1 and P3 to P7 respectively, and the power channel of backup memory block 221 receiving power P8 can be turned on.

[0043] As explained above, when one of the memory blocks 210-217 is damaged, interface circuits 230-237 can sequentially select the normal memory block and the spare memory block 221 to couple to the corresponding pads, and skip the damaged memory block. In this way, a normal memory block can be provided to perform access operations, completing the repair operation simply and quickly. On the other hand, the power supply to the memory block determined to be damaged can be cut off, effectively preventing unnecessary power consumption.

[0044] Please refer to Figure 4A as well as Figure 4B , Figure 4A as well as Figure 4B This is a schematic diagram illustrating an embodiment of multiple interface circuits according to an embodiment of the present invention. Figure 4A In this configuration, interface circuits 430 to 437 are connected in series. Each of interface circuits 430 to 437 includes two switches connected in series between two memory channels. Specifically, interface circuit 430 includes switches S11 and S12; interface circuit 431 includes switches S21 and S22; interface circuit 432 includes switches S31 and S32; interface circuit 433 includes switches S41 and S42; interface circuit 434 includes switches S51 and S52; interface circuit 435 includes switches S61 and S62; interface circuit 436 includes switches S71 and S72; and interface circuit 437 includes switches S81 and S82. Interface circuits 430 to 437 are respectively coupled to memory channel C. <0> C <1> Interval, memory channel C <1> C <2> Interval, memory channel C <2> C <3> Interval, memory channel C <3> C <4> Interval, memory channel C <4> C <5> Interval, memory channel C <5> C <6> Interval, memory channel C <6> C <7> Interval, memory channel C <7> C <8> Interval. Memory channel C <0> ~C <7> Each is used to couple to multiple memory blocks, memory channel C <8> It is then used to couple to the backup memory block.

[0045] On the other side, interface circuits 430 to 437 are coupled to pads PD0 to PD7 respectively. Switches S11, S22, S31, S42, S51, S62, S71, and S82 are controlled by inverting selection signals bSW0 to bSW7 respectively, while switches S12, S21, S32, S41, S52, S61, S72, and S81 are controlled by selection signals SW0 to SW7 respectively.

[0046] exist Figure 4AIn the process, when all memory blocks are in a normal state, switches S11, S22, S31, S42, S51, S62, S71, and S82 are turned on, while switches S12, S21, S32, S41, S52, S61, S72, and S81 are turned off. Interface circuits 430 to 437 respectively enable memory channel C <0> Coupled to pad PD0; enables memory channel C <1> Coupled to pad PD1; enabling memory channel C <2> Coupled to pad PD2; enabling memory channel C <3> Coupled to pad PD3; enabling memory channel C <4> Coupled to pad PD4; enabling memory channel C <5> Coupled to pad PD5; enabling memory channel C <6> Coupled to pad PD6; enabling memory channel C <7> Coupled to pad PD7. This allows for the provision of memory channel C. <0> ~C <7> Multiple memory blocks are coupled separately to perform data access operations.

[0047] In addition, Figure 4B In the middle, with memory channel C <2> The connected memory block is a damaged memory block as an example. At this time, switches S11, S22, S32, S41, S52, S61, S72, and S81 are turned on, while switches S12, S21, S31, S42, S51, S62, S71, and S82 are turned off. Interface circuits 430 to 437 respectively enable memory channel C <0> Coupled to pad PD0; enables memory channel C <1> Coupled to pad PD1; enabling memory channel C <3> Coupled to pad PD2; enabling memory channel C <4> Coupled to pad PD3; enabling memory channel C <5> Coupled to pad PD4; enabling memory channel C <6> Coupled to pad PD5; enabling memory channel C <7> Coupled to pad PD6; enabling memory channel C <8> Coupled to pad PD7. In other words, interface circuits 430 to 437 can isolate the damaged memory block from pads PD1 and PD2, and couple the undamaged memory block and the backup memory block to pads PD0 to PD7 in sequence to complete the repair operation.

[0048] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a multi-channel memory device according to another embodiment of the present invention. Unlike the previous embodiment, in this embodiment, the multi-channel memory 500 includes multiple backup memory blocks 521-1 and 521-2. Backup memory block 521-1, together with memory blocks 510-1 to 517-1 and interface circuits 530-1 to 537-1, forms a first set of circuits for operation. Backup memory block 521-2, together with memory blocks 510-2 to 517-2 and interface circuits 530-2 to 537-2, forms a second set of circuits for operation.

[0049] In this embodiment, the first set of circuits and the second set of circuits can independently perform the memory block repair operation. The operation mode of the repair operation of the first set of circuits and the second set of circuits is the same as that of the aforementioned embodiments and implementation methods, and will not be described in detail here.

[0050] Furthermore, in other embodiments of the present invention, the number of memory blocks in the first group of circuits can be N, and the number of memory blocks in the second group of circuits can be M. The values ​​of N and M can be the same or different.

[0051] In this embodiment, the multi-channel memory 500 further includes redundant interface circuits DM1, DM2, and DM3. Redundant interface circuit DM1 is arranged on one side of interface circuit 530-1 and coupled to memory block 510-1. Redundant interface circuit DM2 is arranged between interface circuits 537-1 and 537-2 and coupled to backup memory blocks 521-1 and 521-2. Redundant interface circuit DM3 is arranged on one side of interface circuit 530-2 and coupled to memory block 511-2. The circuit architectures of redundant interface circuits DM1, DM2, and DM3 are all identical. The circuit architecture of each of the redundant interface circuits DM1, DM2, and DM3 is also identical to the circuit architecture of each of memory blocks 510-1 to 517-2. Redundant interface circuits DM1, DM2 and DM3 are used to balance the load of memory blocks 510-1 to 517-2 and backup memory blocks 521-1 and 521-2, and improve the performance of multi-channel memory 500.

[0052] Of course, according to Figure 5 As can be seen from the embodiments, the multi-channel memory 500 of the present invention can be constructed using more sets of circuits and can provide more backup memory blocks to perform replacement operations on damaged memory blocks, thereby improving the repair capability of the multi-channel memory 500.

[0053] In summary, this invention, through multiple interconnected interface circuits, switches the coupling relationship between the memory block and backup memory block and the input / output interface when a memory block is damaged. This isolates the damaged memory block from access, enabling rapid repair of the multi-channel memory device.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel memory device, characterized in that, include: There are N first memory blocks, where N is a positive integer greater than 1; First spare memory block; as well as There are N first interface circuits, where the i-th first interface circuit is coupled to the i-th first memory block and the (i+1)-th first memory block, where i is a positive integer greater than 0 and less than N. The N-th first interface circuit is coupled to the N-th first memory block and the first spare memory block. The plurality of first interface circuits select N first selected memory blocks and the first spare memory block from the plurality of first memory blocks respectively according to a plurality of first selection signals to couple to a plurality of first input / output interfaces. The i-th first interface circuit includes: A first switch, coupled between the corresponding i-th first memory block and the corresponding i-th first input / output interface, is controlled by the inverted signal of the corresponding i-th first selection signal; and The second switch is coupled between the (i+1)th first memory block and the ith first input / output interface, and is controlled by the ith first selection signal. The first switch and the second switch have opposite on and off states. The Nth first interface circuit includes: A third switch, coupled between the corresponding Nth first memory block and the corresponding Nth first input / output interface, is controlled by the inverted signal of the corresponding Nth first selection signal; and The fourth switch is coupled between the corresponding first spare memory block and the Nth first input / output interface, and is controlled by the Nth first selection signal. The third switch has the opposite on and off states to the fourth switch. When the Kth first memory block among the N first memory blocks is damaged, the plurality of first selection signals control the N first interface circuits to decouple the Kth first memory block from any of the plurality of first input / output interfaces, to couple the 1st to K-1st first memory blocks to the 1st to K-1st first input / output interfaces respectively, to couple the K+1st to the Nth first memory blocks to the Kth to N-1st first input / output interfaces respectively, and to couple the first spare memory block to the Nth first input / output interface.

2. The multi-channel memory device according to claim 1, characterized in that, The i-th first interface circuit selects the i-th first memory block or the (i+1)-th first memory block according to the i-th first selection signal to couple to the i-th first input / output interface.

3. The multi-channel memory device according to claim 2, characterized in that, The Nth first interface circuit selects the Nth first memory block or the first spare memory block to be coupled to the Nth first input / output interface according to the Nth first selection signal.

4. The multi-channel memory device according to claim 1, characterized in that, Also includes: The memory stores error information about the error state of each of the first memory blocks; as well as A decoder, coupled to the memory, generates the plurality of first selection signals based on decoding the error information.

5. The multi-channel memory device according to claim 4, characterized in that, The decoder generates multiple power control signals based on the decoded error information, and each of the first interface circuits connects or disconnects the power supply to each of the first memory blocks and the first spare memory blocks based on each of the power control signals.

6. The multi-channel memory device according to claim 4, characterized in that, The memory is a fuse circuit.

7. The multi-channel memory device according to claim 1, characterized in that, Also includes: First redundant interface circuit and second redundant interface circuit The plurality of first interface circuits are arranged in a column, and the first redundant interface circuit and the second redundant interface circuit are respectively disposed on both sides of the column.

8. The multi-channel memory device according to claim 7, characterized in that, The circuit architecture of the first redundant interface circuit and the second redundant interface circuit is the same as that of each of the first interface circuits.

9. The multi-channel memory device according to claim 1, characterized in that, Also includes: M second memory blocks, where M is a positive integer greater than 1; Second backup memory block; as well as M second interface circuits, each second interface circuit being coupled to two of the plurality of second memory blocks and the second spare memory block, the plurality of second interface circuits selecting M second selected memory blocks and the second spare memory blocks from the plurality of second memory blocks respectively according to a plurality of second selection signals to be coupled to a plurality of second input / output interfaces.

10. The multi-channel memory device according to claim 9, characterized in that, N and M are either equal or different.

11. The multi-channel memory device according to claim 1, characterized in that, The plurality of first input / output interfaces are solder pads.

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