Prototype verification system and method

Abstract

The application discloses a prototype verification system and method, wherein the system comprises a mainboard and a prototype verification board. The mainboard comprises a mainboard power supply end and a mainboard clock circuit; the prototype verification board comprises a verification board power supply end, a verification board clock circuit and an analog circuit, and the analog circuit is used for simulating a substrate control manager for managing the mainboard. In the case that the mainboard and the prototype verification board are not connected, the verification board power supply end is used for supplying power for the analog circuit, and the verification board clock circuit is used for providing a clock signal for the analog circuit, so as to perform first verification on the substrate control manager simulated by the analog circuit. In the case that the mainboard and the prototype verification board are connected, the mainboard power supply end is used for supplying power for the analog circuit, and the mainboard clock circuit is used for providing a clock signal for the analog circuit, so as to perform second verification on the substrate control manager simulated by the analog circuit. The problems occurring in the verification can be accurately positioned.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a prototype verification system and method. Background Technology

[0002] The Baseboard Management Controller (BMC) is a fundamental controller for managing all servers, primarily monitoring and recording various key data across the entire server. BMC prototype verification refers to verifying the functionality of the BMC chip using other chips, such as FPGA (Field Programmable Gate Array) chips, before tape-out. Only after successful verification is the BMC chip tape-out performed, thus reducing the probability of the resulting BMC chip being unusable.

[0003] Currently, prototype verification of BMC is mainly conducted in conjunction with server motherboards. This verification method has the drawback of failing to accurately pinpoint problems that arise during the verification process. Summary of the Invention

[0004] In view of this, the present invention provides a prototype verification system and a prototype verification method that can accurately locate problems that occur during verification.

[0005] This invention provides a prototype verification system, the system comprising:

[0006] Motherboard, including the motherboard power supply and motherboard clock circuit;

[0007] The prototype verification board includes a power supply terminal, a clock circuit, and an analog circuit. The analog circuit is used to simulate a baseboard control manager that manages the motherboard, wherein:

[0008] When the motherboard and the prototype verification board are not connected, the power supply terminal of the verification board is used to supply power to the analog circuit, and the clock circuit of the verification board is used to provide a clock signal to the analog circuit to perform a first verification of the baseboard control manager simulated by the analog circuit.

[0009] When the motherboard is connected to the prototype verification board, the motherboard power supply terminal is used to supply power to the analog circuit, and the motherboard clock circuit is used to provide a clock signal to the analog circuit to perform a second verification of the baseboard control manager simulated by the analog circuit.

[0010] In some embodiments, the simulation circuit includes a plurality of interconnected verification chips, which are used to jointly simulate the substrate control manager.

[0011] In some embodiments, the interconnected verification chips communicate based on a first protocol;

[0012] The verification board clock circuit includes a first clock circuit, which is used to provide a clock signal of a first frequency for the first protocol when the verification chips communicate based on the first protocol.

[0013] In some embodiments, at least a portion of the plurality of verification chips include double-rate synchronous dynamic random access memory;

[0014] The verification board clock circuit includes a second clock circuit, which is used to provide a second frequency clock signal for the double-rate synchronous dynamic random access memory.

[0015] In some embodiments, the analog circuit simulates the substrate control manager, which has multiple different functions;

[0016] Among the multiple interconnected verification chips, at least some of the verification chips are used for different verification functions.

[0017] In some embodiments, the motherboard includes a motherboard port, the prototype verification board includes a verification board port, the motherboard and the prototype verification board are connected through the motherboard port and the verification board port, and when the motherboard and the prototype verification board are connected, the motherboard and the prototype verification board communicate based on a second protocol.

[0018] In some embodiments, when the motherboard is connected to the prototype verification board, the power supply terminal of the verification board is connected to the power supply terminal of the motherboard, the motherboard provides a first voltage to the prototype verification board through the motherboard power supply terminal and the verification board power supply terminal, and the motherboard provides a second voltage to the prototype verification board through the motherboard port and the verification board port.

[0019] In some embodiments, the verification chip is programmed with program code, which, when executed, is used to simulate the function of the baseboard control manager;

[0020] The first verification of the baseboard control manager simulated by the analog circuit includes verifying the correctness of the program code.

[0021] In some embodiments, if the program code passes verification, a second verification is performed on the baseboard control manager simulated by the analog circuit, including verifying whether the communication line between the prototype verification board and the motherboard is normal, and / or verifying whether the communication line of the motherboard is normal.

[0022] In another aspect, the present invention provides a prototype verification method applied to a prototype verification system, the prototype verification system including a motherboard and a prototype verification board, the prototype verification board including analog circuitry for simulating a baseboard control manager that manages the motherboard; the method includes:

[0023] When the motherboard and the prototype verification board are not connected, the analog circuit is powered by the verification board power supply terminal provided on the prototype verification board, and a clock signal is provided to the analog circuit by the verification board clock circuit provided on the prototype verification board, so as to perform a first verification of the baseboard control manager simulated by the analog circuit.

[0024] When the motherboard is connected to the prototype verification board, the analog circuit is powered by the motherboard power supply terminal provided on the motherboard, and a clock signal is provided to the analog circuit by the motherboard clock circuit provided on the motherboard, so as to perform a second verification of the baseboard control manager simulated by the analog circuit.

[0025] In some embodiments, the analog circuit includes a plurality of interconnected verification chips, each verification chip having program code programmed into it. When the program code is executed, it is used to simulate the function of the baseboard control manager.

[0026] The first verification of the substrate control manager simulated by the analog circuit includes:

[0027] The correctness of the program code is verified.

[0028] In some embodiments, if the program code passes verification, the second verification of the baseboard control manager simulated by the analog circuit includes:

[0029] Verify whether the communication line between the prototype verification board and the motherboard is normal, and / or

[0030] The communication lines of the motherboard are verified to be functioning properly.

[0031] In some embodiments of this application, by providing a power supply terminal and a clock circuit for the prototype verification board, independent first verification can be performed on the prototype verification board during the prototype verification process of the baseboard control manager, and second verification can be performed in conjunction with the motherboard. If a verification problem occurs during the first and second verification stages, it can be clearly determined whether the problem is caused by the prototype verification board or the motherboard, thus accurately locating the problem during verification. Attached Figure Description

[0032] The features and advantages of the invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the invention in any way. In the drawings:

[0033] Figure 1 This shows a schematic diagram of the motherboard structure in some technologies;

[0034] Figure 2 A schematic diagram of a prototype verification system for a substrate control manager in some technologies is shown;

[0035] Figure 3 A schematic diagram of the modules of a prototype verification system provided in one embodiment of this application is shown;

[0036] Figure 4 It shows Figure 3 A schematic diagram of the prototype verification system in the diagram;

[0037] Figure 5 It shows Figure 3 A schematic diagram of the prototype verification board in the diagram;

[0038] Figure 6 It shows Figure 5 The prototype verification board includes a schematic diagram of the verification board clock circuit.

[0039] Figure 7 A network topology diagram for RMII / NCSI function verification provided in one embodiment of this application is shown;

[0040] Figure 8 A network topology diagram for USB function verification provided in one embodiment of this application is shown;

[0041] Figure 9 A network topology diagram for I3C function verification provided in one embodiment of this application is shown;

[0042] Figure 10 A flowchart illustrating a prototype verification method provided in one embodiment of this application is shown. Specific implementation methods

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0044] Before explaining this application, the relevant concepts involved in this application shall be explained.

[0045] VR (Voltage Regulator) indicates a power manager; FAN (module) indicates a fan; PCH (Platform Controller Hub) indicates an integrated southbridge; CPLD (Complex Programmable Logic Device) indicates a complex programmable logic device; CPU (Central Processing Unit) indicates a central processing unit; DIMM (Dual-Inline-Memory Modules) indicates dual in-line memory modules; FLASH indicates flash memory; CLOCK BUFFER indicates a clock buffer; LEVEL SHIFT indicates a level shifter; USB PHY indicates a USB network interface card; ADC (Analog-to-Digital Converter) indicates an analog-to-digital converter; SERSOR indicates a sensor; UART HEADER (Universal Asynchronous Receiver / Transmitter) indicates an asynchronous receiver / transmitter; EMMC (Embedded MultiMedia Card) is embedded memory for products such as mobile phones or tablets; I210 is a type of network card; RTL8211 is an Ethernet transceiver; DRAM (Dynamic Random Access DRAM) Memory), Dynamic Random Access Memory; SD (Secure Digital Memory Card), a new generation of high-speed storage devices based on semiconductor flash memory; DCSCM (Datacenter-ready Secure Control Module), a data center-ready secure control module; LTPI, based on DCSCM2.The following are standard signal transmission links for the 0 protocol: SPI (Serial Peripheral Interface); QSPI (Quad SPI); DDR (Double Data Rate Synchronous Dynamic Random Access Memory); FPGA (Field Programmable Gate Array); GPIO (General-purpose input / output); I2C (Inter-Integrated Circuit), also known as IIC, is an integrated circuit bus; I3C (Improved Inter-Integrated Circuit) is an improved version of the I2C bus; UART (Universal Asynchronous Receiver-Transmitter) is a universal asynchronous receiver-transmitter; RGMII (Reduced Gigabit Media Independent Interface) is a simplified GMII interface; RMII (Reduced Media Independent Interface) is a simplified media independent interface; USB (Universal Serial Bus) is a universal serial bus.

[0046] Please see Figure 1 This is a schematic diagram of the structure of the motherboard 11 in some technologies. Figure 1 In the motherboard 11, dual CPUs are equipped with DIMMs, and together with PCH and CPLD, the CPU and system are used for system booting (also known as boot), while BMC monitors various tasks on the motherboard 11.

[0047] Please see Figure 2 This is a schematic diagram of a prototype verification system 100 for a substrate control manager in some technologies. Figure 2 In this prototype verification system 100, a motherboard 11 and a verification board 12 are included. The FPGA on the verification board 12 is used to simulate a BMC, and high-density connectors 2 and 3 are located on a clip. During BMC prototype verification, high-density connectors 0 and 1 on the motherboard 11 are connected to high-density connectors 2 and 3 on the verification board 12. This allows the FPGA signals to communicate with the CPU, PCH, CPLD, and other components via these high-density connectors. Simultaneously, the motherboard 11 supplies power to the components on the verification board 12 through the high-density connectors. This prototype verification system 100 has the following problems:

[0048] 1) During prototype verification, the routing on the motherboard 11 needs to be redesigned, and the signal lines that were originally connected to the BMC are changed to be connected to the high-density connector, which will damage the existing structure of the motherboard 11.

[0049] 2) Since the verification board 12 relies on the motherboard 11 for power, it needs to be used in conjunction with the motherboard 11 during the verification process, which makes it difficult to locate problems that occur during the verification process. For example, if a problem occurs during the system boot process of the motherboard 11, this problem may be introduced when redesigning the wiring of the motherboard 11, or it may be a hardware design problem with the card, or it may be a code problem with the prototype verification system of the card.

[0050] 3) Because high-density connectors have strict signal rate transmission requirements, and are expensive with dense wiring, making it difficult to fan out signals, finding suitable high-density connectors is challenging.

[0051] 4) The FPGA on the verification board 11 usually needs to be a high-specification, high-performance FPGA. The cost of such a large FPGA is too high, and there are few FPGAs that meet the specifications of the prototype verification system 100, which is not conducive to the prototype verification process.

[0052] 5) Open source, modularization, and process standardization are not easy to achieve. Current server environments are undergoing modularization and open source processes, and there are more and more open source resources, such as OCP and OPEN BMC. It is not easy to carry out open source design of the card design in OPEN BMC.

[0053] In view of this, please refer to Figure 3 This is a schematic diagram of a prototype verification system 300 provided in one embodiment of this application. Figure 3 In this prototype verification system 300, a motherboard 31 and a prototype verification board 32 are included. The motherboard 31 includes a motherboard power supply terminal 311 and a motherboard clock circuit 312. The prototype verification board 32 includes a verification board power supply terminal 321, a verification board clock circuit 322, and an analog circuit 323. The analog circuit 323 is used to simulate a baseboard control manager (BMC) that manages the motherboard 31.

[0054] When the main board 31 and the prototype verification board 32 are not connected, the power supply terminal 321 of the verification board is used to supply power to the analog circuit 323, and the clock circuit 322 of the verification board is used to provide a clock signal to the analog circuit 323 to perform the first verification of the baseboard control manager simulated by the analog circuit 323.

[0055] When the motherboard 31 is connected to the prototype verification board 32, the motherboard power supply terminal 311 is used to supply power to the analog circuit 323, and the motherboard clock circuit 322 is used to provide a clock signal to the analog circuit 323 to perform a second verification on the baseboard control manager simulated by the analog circuit 323.

[0056] Thus, the prototype verification process for the baseboard control manager can be divided into two steps. First, a first verification is performed without connecting the motherboard 31 and the prototype verification board 32. This first verification can be performed without requiring the motherboard 31. If a problem occurs during the first verification, since the motherboard 31 is not used for verification at this stage, the problem can be clearly identified as being caused by the prototype verification board 32. For example, it could be due to an error in the program code or a communication line malfunction on the prototype verification board 32. After the prototype verification board 32 has been verified, it is connected to the motherboard 31 for the second verification. This second verification can be performed based on the motherboard 31. If a problem occurs at this stage, since the prototype verification board 32 has already passed verification (i.e., there is no problem), the problem can be clearly identified as being caused by the motherboard 31. For example, it could be due to a communication error between the prototype verification board 32 and the motherboard 31, or a communication line malfunction on the motherboard 31. Specific examples of the first and second verifications can be found in subsequent descriptions and will not be repeated here.

[0057] In summary, in the technical solutions of some embodiments of this application, by providing a verification board power supply terminal 321 and a verification board clock circuit 322 for the prototype verification board 32, the prototype verification board 32 can be independently verified firstly, and then verified secondly in conjunction with the motherboard 31 during the prototype verification process of the baseboard control manager. If a verification problem occurs in either the first or second verification stage, it can be clearly determined whether the problem is caused by the prototype verification board 32 or the motherboard 31, thus accurately locating the problem during verification.

[0058] The following provides further details about the scheme proposed in this application.

[0059] Please see Figures 4 to 6 . Figure 4 for Figure 3 A schematic diagram of the prototype verification system 300 in the diagram. Figure 5 for Figure 3 A schematic diagram of the prototype verification board 32. Figure 6 for Figure 5 The prototype verification board 32 includes a schematic diagram of the verification board clock circuit 322.

[0060] based on Figure 4 and Figure 5The structure is shown. In some embodiments, the analog circuit 323 includes a plurality of interconnected verification chips. The interconnected verification chips can communicate with each other based on a first protocol. The interconnection between the verification chips can be a pairwise interconnection between all verification chips, or a pairwise interconnection between some verification chips. For example, assuming there are verification chips A, B, and C, verification chip A is connected to verification chips B and C, and verification chip B is connected to verification chip C; or verification chip A can be connected to verification chips B and C, but verification chips B and C are not connected.

[0061] The verification chip can be multiple smaller-scale FPGA chips. These FPGA chips can be connected via a bus and communicate based on a first protocol. In this way, multiple smaller-scale FPGA chips can be combined to obtain a high-specification, high-performance FPGA chip. The combined FPGA chips can mutually access logic resources and memory modules. The first protocol can be the AURORA protocol. Figure 4 In this example, two smaller-performance FPGA chips are spliced ​​together to create a higher-performance FPGA chip. Since smaller-performance FPGA chips are readily available and inexpensive, the difficulty and cost of prototype verification can be reduced.

[0062] These multiple interconnected verification chips work together to simulate the substrate control manager. Specifically, each verification chip can simulate a specific function of the substrate control manager, or different verification chips can share hardware resources to jointly simulate the substrate control manager. Figure 4 Taking the illustrated embodiment as an example, chip FPGA0 can be used to connect to GPIO, I2C bus, I3C bus, UART, RGMII, RMII, graphics card, etc., to receive or send low-speed signals, network signals, and signals related to the system boot (i.e., boot) of the motherboard 31. Simultaneously, the content project files related to the aforementioned functional modules of the baseboard control manager can be simulated in chip FPGA0. Thus, the aforementioned functional verification of the baseboard control manager can be completed based on chip FPGA0. Chip FPGA1 can be used to verify the functions of the baseboard control manager, such as the USB internal integrated controller, secure boot, encryption algorithm, and LTPI.

[0063] In some embodiments, at least a portion of the verification chip includes Double Data Rate (DDR) synchronous dynamic random access memory. DDR, also known as a DDR controller, can improve the performance of the verification chip.

[0064] Referring again to 6, in some embodiments, considering the different clock frequencies required by the first protocol and the Double Data Rate Synchronous Dynamic Random Access Memory (DRAM), the verification board clock circuit 322 may include a first clock circuit 3221 and a second clock circuit 3222. The first clock circuit 3221 provides a first frequency clock signal for the first protocol when the verification chips communicate based on the first protocol, and the second clock circuit 3222 provides a second frequency clock signal for the DRAM. This ensures the successful execution of the first verification. In this embodiment, the first clock circuit 3221 is... Figure 6 The RC21008 in the circuit is used to provide a 156.25MHz clock signal for the first protocol, and the second clock circuit 3222 is... Figure 6 The CK440 in the example is used to provide a 100MHz clock signal for the Double Data Rate Synchronous Dynamic Random Access Memory. The number of clock circuits and the frequency they provide can be set according to actual conditions, and this application does not impose any restrictions on this.

[0065] Continue reading Figure 4 In some embodiments, the motherboard 31 includes a motherboard port 313, and the prototype verification board 32 includes a verification board port 324. The motherboard 31 and the prototype verification board 32 are connected via motherboard port 313 and verification board port 324. When the motherboard 31 and the prototype verification board 32 are connected, they communicate based on a second protocol. Specifically, the second protocol can be the DCSCM protocol. The motherboard port 313 and the verification board port 324 can be DCSCM ports. Following standard hardware interface definitions and a fixed structure (the inherent characteristics of the DCSCM protocol and DCSCM ports) facilitates the verification of iterative updates to the baseboard control manager.

[0066] The following combination Figures 4 to 6 This section provides an example of the specific process for prototype verification. To more clearly illustrate the entire verification process, we will first... Figure 4 and Figure 5 The relevant module functions will be explained. Figure 4 neutralization Figure 5 In the prototype verification board 32, there are two verification board power supply terminals 321, namely verification board power supply terminal PSU CON and verification board power supply terminal PWR CON. The motherboard 31 includes two motherboard power supply terminals 311, namely motherboard power supply terminal PWR CON and motherboard power supply terminal RISER SLOT. Figure 5 The functions of each module are as follows:

[0067] ALLFLOW UART is used to transmit serial port information, specifically including the serial port information of the board control manager and the SYSTEM serial port information;

[0068] UART is used to transmit SOL port information and serial port information used for debugging.

[0069] LEVEL SHIFT is a chip used for level conversion. Because the voltage levels of the FPGA chip and the actual voltage levels of the BMC are inconsistent, the LEVEL SHIFT chip is needed to convert the voltage levels to be consistent.

[0070] FAN CON indicates the connector for the fan. It is mainly used to verify the PWM and TACH signals.

[0071] LED, SWITCH, and BTN are used to implement at least part of the logic control of the prototype verification board 32.

[0072] EMMC / SD can be used to store operating system.

[0073] DDR4, specifically SDRAM, refers to the medium in which information is stored in the substrate control manager.

[0074] QSPI FLASH is used to load the firmware information of the FPGA chip itself and the simulated ARM core.

[0075] MCIO is used to connect PCIe resources on the motherboard 31.

[0076] JTAG HEADER is a connector used for debugging FPGA chips.

[0077] PORT80 is used to display the system's working processes, primarily for displaying DEBUG information.

[0078] VR is the voltage controller of the DCSCM board system itself.

[0079] VGA is the connector for graphics card output.

[0080] RTL8211 and I210 are network card chips.

[0081] The USB PHY is used to verify USB 3.0 signals.

[0082] LTPI is a high-speed interface protocol used to verify the interface of the board control manager.

[0083] AURORA stands for the XLINX FPGA chip's own high-speed GTY interconnect protocol.

[0084] INTERCONNECT IO refers to the I / O signal that interconnects the FPGA0 chip and the FPGA1 chip.

[0085] CPLD is used to transmit I / O signals on the SGPIO bus between the CPLD and the motherboard 31.

[0086] CK440 / RC21008 indicates a clock generator used to provide the system with 100MHz and 156.25MHz clocks.

[0087] PSU CON is used to connect the PSU power supply to power the prototype verification board 32 when it is being verified alone.

[0088] PWR CON is used to power the prototype verification board 32 when it is used in conjunction with the motherboard 31 for verification.

[0089] Based on the above description, the first verification will be performed.

[0090] In this embodiment, the verification chip contains programmed code (such as communication protocol code). When the program code runs, it simulates the functions of the baseboard control manager. The baseboard control manager simulated by the analog circuit 323 undergoes a first verification, including verifying the correctness of the program code. (See also...) Figures 4 to 6 Before performing the first verification, the PSU CON power supply terminal of the verification board can be connected to the power supply to power the prototype verification board 32, and the FIRMWAR of the FPGA chip of the analog board control manager can be programmed into the QSPI FLASH. In this case, the prototype verification board 32 will undergo separate system boot. CK440 and RC21008 will provide clocks for the prototype verification board 32, respectively. CK440 provides a 100MHz clock to the double-rate synchronous dynamic random access memory built into the FPGA0 chip, and RC21008 provides a clock to the AURORA protocol interconnecting the FPGA0 and FPGA1 chips (100MHz and 156.25MHz clock topologies are as follows). Figure 6 (As shown). It should be noted that during the first verification process, since the prototype verification board 32 is not connected to the computing resources of the motherboard 31, it is not possible to fully verify all the specifications of the baseboard control manager, but most of the program code can be verified. The first verification includes, for example:

[0091] 1) Verify LTPI functionality. Specifically, this can be divided into I2C, UART, and GPIO function verification. The verification process is as follows:

[0092] See also Figure 5The CPLD can be connected to FPGA0, with the CPLD sending a test signal to FPGA0. Then, via MUX switching, the CPLD can be connected to FPGA1, with the CPLD sending a test signal to FPGA1, which in turn sends the test signal to FPGA0 via LTPI. If the test signal received by FPGA0 is the same before and after the MUX switch, it indicates that the LTPI code and physical link have been successfully verified. For easier understanding, consider this example: before the MUX switch, the CPLD sends the number 01 to FPGA0. After the MUX switch, the CPLD sends 01 to FPGA0 via FPGA1. If FPGA0 receives 01 before and after the MUX switch, it indicates that the LTPI protocol between FPGA0 and FPGA1 is correct, and the physical link is connected. If the information received by FPGA0 before and after the MUX switch is different, it indicates that the LTPI protocol between FPGA0 and FPGA1 is incorrect, and the relevant LTPI protocol code needs to be modified. For example, suppose that the CPLD sends the number 01 before and after the MUX switch, but before the MUX switch, FPGA0 receives the information 01, and after the MUX switch, FPGA0 receives the information 00. This indicates that the LTPI protocol between FPGA0 and FPGA1 is incorrect.

[0093] 2) Verify the AURORA protocol and Double Data Rate Synchronous Dynamic Random Access Memory (DDR). Specifically, under normal conditions of the AURORA protocol and DDR, FPGA0 and FPGA1 can be connected, allowing the logic resources and memory modules of multiple FPGAs to access each other. If these functions cannot be achieved, the AURORA protocol and DDR verification fails.

[0094] 3) Verify the RGMII function. Specifically, you can use an RJ45 connector to ping the network port and verify that the eMAC module code inside the FPGA is correct.

[0095] 4) Verify SD / EMMC functionality. Specifically, an OS system can be installed on the SD or EMMC to verify whether the read / write speed meets the requirements, and to verify the communication path between the board control manager and the SD or EMMC, as well as the AXI bus inside the built-in board control manager.

[0096] 5) Verify I2C and ADC functions. Specifically, since the baseboard control manager typically acts as the I2C host, the FPGA0 and FPGA1 chips also act as I2C hosts to access some I2C devices (such as FRU and THERMALSENSOR). Successful access indicates that the I2C function is working correctly. For ADC function verification, the voltage values ​​of each POWER RAIL on the prototype verification board 32 can be obtained and sent to the FPGA0 or FPGA1 chip via the I2C interface. Then, the data can be uploaded to the built-in ARM core for processing via other means to perform the verification.

[0097] 6) Verify PWM and TACH signals. Specifically, the FPGA0 chip can output PWM and TACH signals, which are then connected to a fan. The fan speed can be adjusted by changing the duty cycle of the PWM signal to verify the PWM and TACH functions.

[0098] In summary, the first verification is complete. The second verification will now proceed.

[0099] In this embodiment, after the program code verification passes, a second verification is performed on the baseboard control manager simulated by the analog circuit 323. This includes verifying whether the communication lines between the prototype verification board 32 and the main board 31 are functioning correctly, and / or verifying whether the communication lines of the main board 31 are functioning correctly. Before performing the second verification, the power supply between the main board 31 and the prototype verification board 32 needs to be adjusted. In this embodiment, since the communication between the motherboard port 313 and the verification board port 324 is based on the DCSCM2.0 standard protocol, according to this standard protocol, the motherboard 31 can only provide 4.4A of P12V to the prototype verification board 32 through the motherboard port 313 and the verification board port 324. This power supply cannot meet the power supply requirements of the prototype verification board 32. Therefore, the power supply connected to the verification board power supply terminal PSU CON can be removed, and the verification board power supply terminal PWR CON can be connected to the motherboard power supply terminal RISER SLOT. The motherboard 31 provides the first voltage to the prototype verification board 32 through the motherboard power supply terminal RISER SLOT and the verification board power supply terminal PWR CON, and the motherboard 31 provides the second voltage to the prototype verification board 32 through the motherboard port 313 and the verification board port 324. After completing the above operations, the second verification can be performed. Among them, the functions verified without the motherboard 31 can be verified with the motherboard 31. Since the clock needs to be switched, the clock switching circuit can be COLAY designed. Specifically, the second verification includes, for example:

[0100] 1) Since the first verification only verified the information transmission between the FPGA0 and FPGA1 chips for the LTPI function, when using the motherboard 31, the GPIO, I2C, and UART on the motherboard 31 can all be verified in the actual working system. Taking GPIO as an example, the GPIO on the motherboard 31 can be connected to the CPLD on the prototype verification board 32 via SGPIO, and then decoded on the prototype verification board 32 to transmit data from the FPGA0 chip to the FPGA1 chip via LTPI, thus verifying the LTPI transmission link in the actual system.

[0101] 2) Graphics Card Functionality Verification. The PCIe resources required by the graphics card can be obtained from the CPU (or PCH). These PCIe resources can be transmitted to the high-speed transceiver GTY of the FPGA0 chip. Inside the FPGA0 chip, the PCIe resources can be transmitted to the VGA module (including the 2D DRAWING ENGINE). The VGA module outputs R, G, and B (RED, GREEN, BLUE) digital signals, which are converted into analog signals by a digital-to-analog converter. After a series of physical link electrical characteristic matching, the signals can be connected to a monitor with a VGA interface. This allows the system to directly enter the BIOS interface upon successful boot.

[0102] 3) Network function RMII / NCSI verification. (See also...) Figure 7 This is a network topology diagram for RMII / NCSI function verification provided in one embodiment of this application. Specifically, since the network card chip I210 requires PCIe resources, the motherboard 31 needs to transfer the PCIe resources to the I210 before verification. Due to the physical pin limitations of the DCSCM interface connector, MCIO and cable connections can be used to send the motherboard 31's PCIe resources to the I210. After the PCIe resource transfer is completed, if the I210 can ping the network, the RMII function is verified. Furthermore, NCSI can be IP CONFIG bound from the FPGA chip via serial port in S5 state. If the FPGA can be pinged after rebooting, it indicates that the RMII and NCSI function verifications are successful.

[0103] 4) Verify USB functionality. (Refer to the relevant documentation.) Figure 8This is a network topology diagram for USB function verification provided in one embodiment of this application. Specifically, PCIe resources can be sent to FPGA1 via CABLE, so that the USBCONTRIOLLER inside FPGA1 can be verified. FPGA1 internally converts the PCIe resources into ULPI (USB 2.0 protocol interface) and PIPE (USB 3.0 protocol interface) signals, connects them to the USB PHY chip, outputs USB 3.0 and USB 2.0 signals, and connects them to the USB 3.0 connector. When the HOST can recognize the USB device being inserted, the USB function of the prototype verification system can be verified, and KVM can also be verified at the same time.

[0104] 5) Verify LPC and eSPI functionality. Specifically, these two protocols use different physical links due to their different signal levels, but the content they transmit is essentially the same (mainly transmitting some boot-related logic signals). Therefore, PORT 80 can be connected to display LPC and eSPI transmissions. It should be noted that since EGS and BHS do not support LPC, when verifying with an Intel EGS or BHS platform CPU, LPC needs to be connected separately to a header for verification with other systems.

[0105] 6) Verify the MCTP Over PCIe function. For ease of understanding, the MCTP Over PCIe function will be introduced first. Normally, one baseboard control manager manages one motherboard 31. However, if some motherboard 31 baseboard control managers malfunction, some functions of those motherboards 31 can be managed through the baseboard control managers of other motherboards 31. Here, the function of a baseboard control manager managing multiple motherboards 31 is the MCTP Over PCIe function. To verify this function, you can use the PCIe resources on the motherboard 31, connecting one motherboard 31 and two prototype verification boards 32 via cable. If access is possible under the same host OS, the MCTP Over PCIe function verification is successful.

[0106] 7) Verify I3C functionality. (Refer to the relevant documentation.) Figure 9 This is a network topology diagram for I3C function verification provided in one embodiment of this application. I3C functionality requires the motherboard 31 for verification. Taking the I3C DIMM strip as an example, if the I3C address on the motherboard can be scanned in the uboot interface, then I3C verification is successful.

[0107] 8) Verify PECI functionality. PECI is a bus defined by Intel standards used to enable the board control manager to acquire data such as temperature parameters from the CPU. When FPGA0 obtains this CPU temperature information and uploads it to the ARM Core for processing, the functionality of PECI is verified.

[0108] In summary, the second verification is complete.

[0109] Please see Figure 10 This is a schematic flowchart illustrating a prototype verification method provided in one embodiment of this application. The prototype verification method can be applied to a prototype verification system, which includes a motherboard and a prototype verification board. The prototype verification board includes analog circuitry for simulating a baseboard control manager that manages the motherboard. Figure 10 In this context, the prototype verification method includes the following steps:

[0110] Step S11: When the motherboard and the prototype verification board are not connected, power is supplied to the analog circuit through the verification board power supply terminal set on the prototype verification board, and a clock signal is provided to the analog circuit through the verification board clock circuit set on the prototype verification board, so as to perform the first verification of the substrate control manager simulated by the analog circuit.

[0111] In step S12, with the motherboard connected to the prototype verification board, power is supplied to the analog circuit through the motherboard power supply terminal, and a clock signal is provided to the analog circuit through the motherboard clock circuit, so as to perform a second verification of the substrate control manager simulated by the analog circuit.

[0112] In some embodiments, the analog circuit includes a plurality of interconnected verification chips, each of which has program code programmed into it. When the program code is run, it is used to simulate the function of the baseboard control manager.

[0113] The first verification of the board control manager for analog circuit simulation includes:

[0114] Verify the correctness of the program code.

[0115] In some embodiments, if the program code passes verification, a second verification is performed on the substrate control manager simulated by the analog circuit, including:

[0116] Verify the functionality of the communication lines between the prototype verification board and the motherboard; and / or

[0117] Verify whether the motherboard's communication lines are functioning properly.

[0118] The principles of prototype verification methods can be found in the relevant introduction to the prototype verification system mentioned above, and will not be repeated here.

[0119] Although the implementation method of the present invention has been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A prototype verification system, characterized by, The system includes: Motherboard, including the motherboard power supply and motherboard clock circuit; The prototype verification board includes a power supply terminal, a clock circuit, and an analog circuit. The analog circuit is used to simulate a baseboard control manager that manages the motherboard, wherein: When the motherboard and the prototype verification board are not connected, the power supply terminal of the verification board is used to supply power to the analog circuit, and the clock circuit of the verification board is used to provide a clock signal to the analog circuit to perform a first verification of the baseboard control manager simulated by the analog circuit. If the first verification is successful, connect the motherboard to the prototype verification board; When the motherboard is connected to the prototype verification board, the motherboard power supply terminal is used to supply power to the analog circuit, and the motherboard clock circuit is used to provide a clock signal to the analog circuit to perform a second verification of the baseboard control manager simulated by the analog circuit.

2. The system of claim 1, wherein, The simulation circuit includes multiple interconnected verification chips, which are used together to simulate the substrate control manager.

3. The system as described in claim 2, characterized in that, The interconnected verification chips communicate based on a first protocol; The verification board clock circuit includes a first clock circuit, which is used to provide a clock signal of a first frequency for the first protocol when the verification chips communicate based on the first protocol.

4. The system as described in claim 2, characterized in that, Among the plurality of verification chips, at least some of the verification chips include double-rate synchronous dynamic random access memory; The verification board clock circuit includes a second clock circuit, which is used to provide a second frequency clock signal for the double-rate synchronous dynamic random access memory.

5. The system as described in claim 2, characterized in that, The analog circuit simulates the baseboard control manager, which has several different functions; Among the multiple interconnected verification chips, at least some of the verification chips are used for different verification functions.

6. The system as described in claim 1, characterized in that, The motherboard includes a motherboard port, and the prototype verification board includes a verification board port. The motherboard and the prototype verification board are connected through the motherboard port and the verification board port. When the motherboard and the prototype verification board are connected, the motherboard and the prototype verification board communicate based on a second protocol.

7. The system as described in claim 6, characterized in that, When the motherboard is connected to the prototype verification board, the power supply terminal of the verification board is connected to the power supply terminal of the motherboard. The motherboard provides a first voltage to the prototype verification board through the motherboard power supply terminal and the verification board power supply terminal, and the motherboard provides a second voltage to the prototype verification board through the motherboard port and the verification board port.

8. The system as described in claim 2, characterized in that, The verification chip contains program code, which, when executed, is used to simulate the function of the baseboard control manager. The first verification of the baseboard control manager simulated by the analog circuit includes verifying the correctness of the program code.

9. The system as described in claim 8, characterized in that, If the program code passes verification, a second verification is performed on the baseboard control manager simulated by the analog circuit, including verifying whether the communication line between the prototype verification board and the motherboard is normal, and / or verifying whether the communication line of the motherboard is normal.

10. A prototype verification method, characterized in that, The method is applied to a prototype verification system, the prototype verification system including a motherboard and a prototype verification board, the prototype verification board including analog circuitry for simulating a baseboard control manager that manages the motherboard; the method includes: When the motherboard and the prototype verification board are not connected, the analog circuit is powered by the verification board power supply terminal provided on the prototype verification board, and a clock signal is provided to the analog circuit by the verification board clock circuit provided on the prototype verification board, so as to perform a first verification of the baseboard control manager simulated by the analog circuit. If the first verification is successful, connect the motherboard to the prototype verification board; When the motherboard is connected to the prototype verification board, the analog circuit is powered by the motherboard power supply terminal provided on the motherboard, and a clock signal is provided to the analog circuit by the motherboard clock circuit provided on the motherboard, so as to perform a second verification of the baseboard control manager simulated by the analog circuit.

11. The method as described in claim 10, characterized in that, The simulation circuit includes multiple interconnected verification chips, each containing program code. When the program code is executed, it is used to simulate the function of the baseboard control manager. The first verification of the substrate control manager simulated by the analog circuit includes: The correctness of the program code is verified.

12. The method as described in claim 11, characterized in that, If the program code passes verification, the second verification of the baseboard control manager simulated by the analog circuit includes: Verify whether the communication line between the prototype verification board and the motherboard is normal; and / or The communication lines of the motherboard are verified to be functioning properly.

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