Logic cell for integrated circuits, integrated circuit and design method thereof

Abstract

A logic unit for an integrated circuit, an integrated circuit and a design method thereof are provided. In the logic unit, one of a P-type semiconductor and an N-type semiconductor is located in a first semiconductor region; the other is located in a second semiconductor region; a first voltage connection part and a second voltage connection part both extend along a first direction and respectively electrically connect the first semiconductor region and a first voltage and the second semiconductor region and a second voltage; at least one first transistor and at least one second transistor both have a fin-type transistor structure and are respectively located in a first transistor region and a second transistor region; at least one gate connection part is located in a gate connection region and respectively leads out a gate of the at least one first transistor and a gate of the at least one second transistor extending along a second direction; a positive projection of the first transistor region and the second transistor region along a third direction at least partially overlaps a positive projection of the first semiconductor region and the second semiconductor region along the third direction, and the first direction, the second direction and the third direction intersect each other.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a logic cell for integrated circuits, integrated circuits, and a design method for integrated circuits. Background Technology

[0002] In analog integrated circuit design, a standard cell library is designed based on the circuit's power consumption, speed, and other requirements to build an integrated circuit layout library. The design requirements of this layout library are not only to ensure the correctness of the design rules for individual logic cells, but also to ensure the correctness of the design rules when splicing logic cells.

[0003] However, with the development of Fin Field-Effect Transistors (FFETs), the process has introduced more mask layers and more design rules. The application of Double Pattern Technology (DPT) has made the design rules of the metal layer more complex, resulting in some new design rule requirements. This has required analog layout engineers to spend more time dealing with the newly introduced design rules when processing logic cells. Summary of the Invention

[0004] To address at least one aspect of the above-mentioned problems, embodiments of this disclosure provide a logic cell for an integrated circuit, an integrated circuit, and a method for designing an integrated circuit.

[0005] In one aspect, a logic unit for an integrated circuit is provided, the logic unit comprising: a first semiconductor region, wherein one of a P-type semiconductor and an N-type semiconductor is located in the first semiconductor region; a second semiconductor region, wherein the other of a P-type semiconductor and an N-type semiconductor is located in the second semiconductor region; a first voltage connection portion for electrically connecting the first semiconductor region to a first voltage; a second voltage connection portion for electrically connecting the second semiconductor region to a second voltage; a first transistor region, wherein at least one first transistor is located in the first transistor region; a second transistor region, wherein at least one second transistor is located in the second transistor region; and a gate connection region, wherein at least one gate connection portion is located in the gate connection region, wherein the at least one first transistor has a finned transistor structure, and the at least one second transistor has a finned transistor structure. The transistor structure includes at least one first transistor and at least one second transistor whose gates extend along a second direction, and at least one first voltage connection portion and at least one second voltage connection portion whose gates extend along a first direction, the first direction and the second direction intersecting; at least one gate connection portion is used to lead out the gates of at least one first transistor and at least one second transistor respectively; the orthogonal projection of the first transistor region along a third direction at least partially overlaps with the orthogonal projection of the first semiconductor region along a third direction, the orthogonal projection of the second transistor region along a third direction at least partially overlaps with the orthogonal projection of the second semiconductor region along a third direction, the third direction being perpendicular to both the first direction and the second direction; and the first voltage connection portion, the first transistor region, the gate connection region, the second transistor region and the second voltage connection portion are arranged sequentially along the second direction.

[0006] According to some exemplary embodiments, the size of the first transistor region is designed to accommodate 2 to 6 fins; and / or, the size of the second transistor region is designed to accommodate 2 to 6 fins.

[0007] According to some exemplary embodiments, the logic unit further includes a plurality of first metal traces, at least one of the first metal traces being used to electrically connect the first connection portion and the first voltage, and at least another of the first metal traces being used to electrically connect the second connection portion and the second voltage; the logic unit further includes a plurality of second metal traces, the plurality of second metal traces being used to lead out at least one electrode of the at least one first transistor and the at least one second transistor; and the line width of the first metal trace is greater than the line width of the second metal trace.

[0008] On the other hand, an integrated circuit is provided, which includes a plurality of logic units, which are spliced ​​together to form the integrated circuit, and at least one of the plurality of logic units is a logic unit as described above.

[0009] According to some exemplary embodiments, the plurality of logic units include a first logic unit and a plurality of second logic units. The first logic unit is located in the middle region of the integrated circuit, and the plurality of second logic units are located on both sides of the first logic unit in a first direction. The plurality of second logic units are used to terminate the extension of the active regions of the at least one first transistor and the at least one second transistor in the first direction and to make the integrated circuit meet the design rules in the first direction.

[0010] According to some exemplary embodiments, the plurality of logic units further includes a plurality of third logic units located on both sides of the first logic unit in a second direction. The plurality of third logic units are used to terminate the extension of the gates of the at least one first transistor and the at least one second transistor in the second direction and to make the integrated circuit meet the design rules in the second direction.

[0011] According to some exemplary embodiments, the plurality of logic units further includes a plurality of fourth logic units, one of which is located in a first direction between the first logic unit and one of the second logic units, and another of which is located in a first direction between the first logic unit and another of the second logic units; the transistors in the first logic unit and the second logic unit have different threshold voltages, and the fourth logic unit is used to transition between the different threshold voltages between the transistors in the first logic unit and the second logic unit.

[0012] According to some exemplary embodiments, the integrated circuit includes a plurality of first logic units, two of which are connected to each other in a first direction, the transistors in the two logic units have the same threshold voltage, and the two logic units share a gate; and / or,

[0013] The integrated circuit includes a plurality of first logic units, two of which are spliced ​​together in a first direction, the transistors in the two logic units have different threshold voltages, and the adjacent gates in the two logic units are spaced apart.

[0014] According to some exemplary embodiments, the integrated circuit includes a plurality of first logic units, two of the plurality of first logic units being spliced ​​together in a second direction, the two logic units sharing a first connection portion or a second connection portion; the two logic units are arranged symmetrically with respect to an axis of symmetry, the axis of symmetry extending along a first direction and extending through the shared first connection portion or second connection portion.

[0015] In another aspect, a method for designing an integrated circuit is provided, the method comprising: providing a logic cell library, wherein the logic cell library includes a plurality of logic cells, at least one of the plurality of logic cells being a logic cell as described above; and selecting a plurality of logic cells from the logic cell library and assembling the plurality of logic cells to form an integrated circuit.

[0016] According to the embodiments of this disclosure, by adopting the layout method provided by the embodiments of this disclosure, it is beneficial to improve the efficiency of drawing integrated circuit layouts, reduce the time for fixing design rule violations, and reduce the splicing distance of devices and logic units, thereby improving the area utilization rate of integrated circuit layouts. Attached Figure Description

[0017] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0018] Figure 1 This is a plan view of a logic unit according to an embodiment of the present disclosure;

[0019] Figure 2 This is a plan view of a logic unit according to an embodiment of the present disclosure, including a first metal trace and a second metal trace.

[0020] Figure 3 This is a planar schematic diagram of an integrated circuit according to an embodiment of the present disclosure;

[0021] Figure 4 This is a planar schematic diagram showing that a plurality of first logic units of an integrated circuit according to an embodiment of the present disclosure are overlapped and spliced ​​in a first direction;

[0022] Figure 5 This is a planar schematic diagram of a plurality of first logic units of an integrated circuit according to an embodiment of the present disclosure, which are spliced ​​together in a first direction without overlap.

[0023] Figure 6 This is a planar schematic diagram showing that a plurality of first logic units of an integrated circuit according to an embodiment of the present disclosure are overlapped and spliced ​​in a second direction; and

[0024] Figure 7 This is a flowchart of an integrated circuit design method according to an embodiment of the present disclosure.

[0025] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0026] The technical solutions of this disclosure will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of this disclosure and should not be construed as a limitation thereof.

[0027] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0028] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0029] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0030] The various exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. In the drawings, similar reference numerals always refer to similar elements. Repeated descriptions may be omitted.

[0031] In the following description, the structure of the logic unit and integrated circuit according to the example embodiment is described in three-dimensional space using a first direction X, a second direction Y, and a third direction Z. The first direction X can be a row direction, the second direction Y can be a column direction, and the third direction Z can be a vertical direction. The first direction X, the second direction Y, and the third direction Z can intersect, for example, they can be orthogonal or perpendicular to each other.

[0032] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics, such as fin field-effect transistors. In the embodiments of this disclosure, the transistor may include a gate, a first electrode, and a second electrode, wherein the first electrode may represent one of the source and drain, and the second electrode may represent the other of the source and drain.

[0033] The channel of a fin field-effect transistor (FET) consists of tall, thin fins protruding from an insulating substrate. The source and drain terminals are located at its two ends, respectively, while the three gates are attached to its sidewalls and top for auxiliary current control. The fin structure increases the area of ​​the gate surrounding the channel, strengthening the gate's control over the channel. This can alleviate the short-channel effect that occurs in planar devices, improve circuit control, and reduce leakage current. It can also shorten the gate length of the transistor, eliminating the need for a highly doped channel, thereby reducing impurity ion scattering effects and increasing channel carrier mobility.

[0034] Some exemplary embodiments of this disclosure provide a logic unit for an integrated circuit, the logic unit comprising: a first semiconductor region, wherein one of a P-type semiconductor and an N-type semiconductor is located in the first semiconductor region; a second semiconductor region, wherein the other of a P-type semiconductor and an N-type semiconductor is located in the second semiconductor region; a first voltage connection portion for electrically connecting the first semiconductor region to a first voltage; a second voltage connection portion for electrically connecting the second semiconductor region to a second voltage; a first transistor region, wherein at least one first transistor is located in the first transistor region; a second transistor region, wherein at least one second transistor is located in the second transistor region; and a gate connection region, wherein at least one gate connection portion is located in the gate connection region.

[0035] For example, at least one first transistor has a finned transistor structure, at least one second transistor has a finned transistor structure, the gate of at least one first transistor and the gate of at least one second transistor both extend along a second direction, the first voltage connection portion and the second voltage connection portion both extend along a first direction, and the first direction and the second direction intersect.

[0036] For example, at least one gate connection is used to lead out the gate of at least one first transistor and the gate of at least one second transistor, respectively.

[0037] For example, the orthographic projection of the first transistor region along a third direction at least partially overlaps with the orthographic projection of the first semiconductor region along a third direction, and the orthographic projection of the second transistor region along a third direction at least partially overlaps with the orthographic projection of the second semiconductor region along a third direction, wherein the third direction is perpendicular to both the first direction and the second direction.

[0038] For example, the first voltage connection portion, the first transistor region, the gate connection region, the second transistor region, and the second voltage connection portion are arranged sequentially along the second direction.

[0039] By adopting the layout method provided by the embodiments of this disclosure, it is beneficial to improve the efficiency of drawing integrated circuit layouts, reduce the time for fixing design rule violations, and reduce the splicing distance of devices and logic units, thereby improving the area utilization of integrated circuit layouts.

[0040] Figure 1 This is a plan view of a logic unit according to an embodiment of the present disclosure.

[0041] refer to Figure 1 According to embodiments of the present disclosure, the logic unit 100 may include a first semiconductor region 101, a second semiconductor region 102, a first voltage connection portion 103, a second voltage connection portion 104, a first transistor region 105, a second transistor region 106, and a gate connection region 107. The logic unit 100 may be used in an integrated circuit.

[0042] One of the P-type and N-type semiconductors can be located in the first semiconductor region 101, and the other can be located in the second semiconductor region 102. The first voltage connection portion 103 can be used to electrically connect the first semiconductor region 101 to a first voltage, thereby electrically connecting the P-type or N-type semiconductor located in the first semiconductor region 101 to the first voltage. The second voltage connection portion 104 can be used to electrically connect the second semiconductor region 102 to a second voltage, thereby electrically connecting the N-type or P-type semiconductor located in the second semiconductor region 102 to the second voltage. When the P-type semiconductor is located in the first semiconductor region 101, the first voltage can be a ground voltage, and the second voltage can be a power supply voltage. When the P-type semiconductor is located in the second semiconductor region 102, the second voltage can be a ground voltage, and the first voltage can be a power supply voltage. By providing the first voltage connection portion 103 and the second voltage connection portion 104, the latch-up effect of the integrated circuit can be reduced.

[0043] The dimensions of the first voltage connection portion 103 and the second voltage connection portion 104 can be designed according to the application scenario of the logic unit 100. For example, the dimensions of the first voltage connection portion 103 can be designed to accommodate four fins, and the dimensions of the second voltage connection portion 104 can be designed to accommodate four fins. The width of the first voltage connection portion 103 can be set to 0.154 μm, and the width of the second voltage connection portion 104 can be set to 0.154 μm.

[0044] At least one first transistor may be located in the first transistor region 105, and at least one second transistor may be located in the second transistor region 106. At least one gate connection portion 108 may be located in the gate connection region 107. The first transistor may be a PMOS transistor, and the second transistor may be an NMOS transistor.

[0045] At least one first transistor has a finned transistor structure, and at least one second transistor has a finned transistor structure. The first and second transistors can be finned field-effect transistors with a finned transistor structure. For example... Figure 1 As shown, the gate 109 of at least one first transistor and the gate 109 of at least one second transistor both extend along the second direction Y, and the first voltage connection portion 103 and the second voltage connection portion 104 both extend along the first direction X. The first direction X and the second direction Y intersect.

[0046] According to some exemplary embodiments, at least one gate connection portion 108 can be used to respectively lead out the gate 109 of at least one first transistor and the gate 109 of at least one second transistor. The gate 109 of the first transistor and the gate 109 of the second transistor can be electrically connected to the upper metal traces through the gate connection portion 108, for example... Figure 1 It includes three gate connection portions 108, and the gate 109 of the first transistor can be connected through... Figure 1 The gate connection portion 108 in the upper left corner is electrically connected to the upper metal trace, and the gate 109 of the second transistor can be connected via... Figure 1 The gate connection portion 108 in the lower left corner is electrically connected to the upper metal trace. The gate 109 of the first transistor and the gate 109 of the second transistor can also be connected via... Figure 1 The gate connection 108 on the right side is electrically connected to the metal trace on the upper layer.

[0047] like Figure 1 As shown, the orthographic projection of the first transistor region 105 along the third direction Z at least partially overlaps with the orthographic projection of the first semiconductor region 101 along the third direction Z, and the orthographic projection of the second transistor region 106 along the third direction Z at least partially overlaps with the orthographic projection of the second semiconductor region 102 along the third direction Z. The third direction Z is perpendicular to both the third direction X and the second direction Y. The first transistor region 105 and the second transistor region 106 can be located on top of the first semiconductor region 101 and the second semiconductor region 102, so that the first transistor region 105 and the second transistor region 106 respectively partially cover the first semiconductor region 101 and the second semiconductor region 102.

[0048] The orthographic projection of the gate connection region 107 along the third direction Z at least partially overlaps with the orthographic projection of the first semiconductor region 101 and the second semiconductor region 102 along the third direction Z, so that the gate 109 of the first transistor and the gate 109 of the second transistor located in the first semiconductor region 101 and the second semiconductor region 102 are electrically connected to the upper metal trace through the gate connection portion 108.

[0049] like Figure 1As shown, the first voltage connection portion 103, the first transistor region 105, the gate connection region 107, the second transistor region 106, and the second voltage connection portion 104 can be arranged sequentially along the second direction Y, but are not limited thereto. For example, the first voltage connection portion 103, the first transistor region 105, the gate connection region 107, the second transistor region 106, and the second voltage connection portion 104 can be arranged sequentially in a direction opposite to the second direction Y.

[0050] According to the embodiments of this disclosure, by adopting the layout method provided by the embodiments of this disclosure, it is beneficial to improve the efficiency of drawing integrated circuit layouts, reduce the time for fixing design rule violations, and reduce the splicing distance of devices and logic units, thereby improving the area utilization rate of integrated circuit layouts.

[0051] According to embodiments of this disclosure, the size of the first transistor region can be designed to accommodate 2 to 6 fins. The size of the first transistor region can be designed according to the application scenario of the logic unit. For example, in the case of fabricating an inverter circuit, the size of the first transistor region can be designed to accommodate 6 fins, and in the case of fabricating an amplifier circuit, the size of the first transistor region can be designed to accommodate 4 fins.

[0052] According to embodiments of this disclosure, the size of the second transistor region can be designed to accommodate 2 to 6 fins. The size of the second transistor region can be designed according to the application scenario of the logic unit. For example, in the case of fabricating an inverter circuit, the size of the second transistor region can be designed to accommodate 6 fins, and in the case of fabricating an amplifier circuit, the size of the second transistor region can be designed to accommodate 4 fins.

[0053] Figure 2 This is a plan view of a logic unit according to an embodiment of the present disclosure, including a first metal trace and a second metal trace.

[0054] According to embodiments of this disclosure, the logic unit may further include a plurality of first metal traces, at least one of which can be used to electrically connect a first connection portion and a first voltage, and at least another first metal trace can be used to electrically connect a second connection portion and a second voltage. For example... Figures 1 to 2 As shown, the logic unit has two first metal traces 201, which can be arranged opposite each other on both sides of the logic unit. Figure 2 The first metal trace 201 can be located on the upper layer of the first connection portion 103 to electrically connect the first connection portion 103 to the first voltage. The first metal trace 201 can be located on the upper layer of the second connection portion 104 to electrically connect the second connection portion 104 to the second voltage. The first metal trace can be a metal wire.

[0055] According to embodiments of this disclosure, such as Figure 2 As shown, the logic unit may further include multiple second metal traces, which can be used to bring out at least one electrode of at least one first transistor and at least one second transistor. Figure 2 As shown, the logic unit has two second metal traces 202, which can be arranged opposite each other on both sides of the logic unit. Figure 2 The second metal trace 202 extends along the second direction Y (left and right sides of the first transistor), and further, the second metal trace 202 can bend along the second direction Y, and the bending angle of the second metal trace 202 can be 90°. The second metal trace 202 can be located on the upper layer of the first transistor to lead out the electrode of the first transistor. The electrode of the first transistor can be at least one of the source, drain, and gate of the first transistor. The second metal trace 202 can be located on the upper layer of the second transistor to lead out the electrode of the second transistor. The electrode of the second transistor can be at least one of the source, drain, and gate of the second transistor. The second metal trace 202 can be a signal line. Figure 2 Gate 209 in the middle can be with Figure 1 The gate 109 is the same.

[0056] The line width of the first metal trace is greater than the line width of the second metal trace. For example, the line width of the first metal trace can be set to 0.112 μm, the line width of the second metal trace can be set to 0.04 μm, and the distance between the two metal traces can be set to 0.08 μm.

[0057] According to embodiments of this disclosure, Virtuso's WSP tool can be used to create tracks for the first and second metal traces, allowing layout engineers to route metal traces on fixed tracks, thereby aligning the metal tracks of different logic units with each other.

[0058] According to embodiments of this disclosure, by adopting the layout method provided by embodiments of this disclosure, logic units with different attributes can be designed. The attributes of the logic unit may include functional information, length information, distance information, fin number information of the first transistor region and the second transistor region, drive strength information, and threshold voltage information, etc.

[0059] For example, a logic unit can be designed as follows:

[0060] inv_l16_p90_p4n4_d1_lvt: A logic unit with inv function, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0061] buf_l16_p90_p4n4_d1_lvt: A logic unit with buf functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0062] nond2_l16_p90_p4n4_d1_lvt: A logic unit with nond2 functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0063] nond3_l16_p90_p4n4_d1_lvt: A logic unit with nond3 functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0064] nor2_l16_p90_p4n4_d1_lvt: A logic cell with nor2 functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0065] nor3_l16_p90_p4n4_d1_lvt: A logic cell with nor3 functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0066] trans_l16_p90_p4n4_d1_lvt: A logic unit with trans function, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0067] trigate_l16_p90_p4n4_d1_lvt: A logic unit with trigate functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0068] trinot_l16_p90_p4n4_d1_lvt: A logic unit with trinot functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type of lvt;

[0069] xor2_l16_p90_p4n4_d1_lvt: A logic unit with XOR2 functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, first drive strength, and threshold voltage type LVT.

[0070] mux2_l16_p90_p4n4_d1_lvt: A logic unit with mux2 functionality, 16nm long and 90nm apart, with 4 fins in the first transistor region and 4 fins in the second transistor region, a first drive strength, and a threshold voltage type of lvt.

[0071] Some exemplary embodiments of this disclosure also provide an integrated circuit. The integrated circuit may include multiple logic units, which can be assembled to form an integrated circuit, and at least one of the multiple logic units can be the aforementioned logic unit 100.

[0072] Figure 3 This is a planar schematic diagram of an integrated circuit according to an embodiment of the present disclosure.

[0073] According to embodiments of this disclosure, a plurality of logic units in an integrated circuit may include a first logic unit and a plurality of second logic units. The first logic unit may be located in the middle region of the integrated circuit, and the plurality of second logic units may be located on both sides of the first logic unit in a first direction. The plurality of second logic units may be used to terminate the extension of the active regions of at least one first transistor and at least one second transistor in the first direction and may enable the integrated circuit to meet design rules in the first direction.

[0074] The first logic unit can be the basic unit of an integrated circuit, serving as the primary area for creating and placing MOSFETs and wiring metal. The MOSFET can include at least one of a first transistor, a second transistor, a P-type semiconductor, and an N-type semiconductor. The wiring metal can include at least one of a first metal trace and a second metal trace.

[0075] like Figure 3 As shown, the integrated circuit may include one first logic unit L1 and two second logic units L2. The two second logic units L2 are located on either side of the first logic unit L1. Figure 3 (on the left and right sides of the circuit), the two second logic units L2 can terminate the extension of the active regions of at least one first transistor T1 and at least one second transistor T2 in the first direction X, thereby correcting DRC (Design Rule Check) errors and making the integrated circuit meet the design rules in the first direction X.

[0076] According to embodiments of this disclosure, the plurality of logic units further includes a plurality of third logic units, which are located on both sides of the first logic unit in a second direction. The plurality of third logic units are used to terminate the extension of the gates of at least one first transistor and at least one second transistor in the second direction and to make the integrated circuit meet the design rules in the second direction.

[0077] like Figure 3 As shown, the integrated circuit includes two third logic units L3. The two third logic units L3 are located on either side of the first logic unit L1. Figure 3 (On the upper and lower sides of the circuit), the two third logic units L3 can terminate the extension of the gates of at least one first transistor T1 and at least one second transistor T2 in the second direction Y, thereby correcting DRC (Design Rule Check) errors and enabling the integrated circuit to meet the design rules in the second direction Y.

[0078] According to embodiments of this disclosure, the plurality of logic units further includes a plurality of fourth logic units, one of which is located between the first logic unit and a second logic unit in a first direction, and another of the plurality of fourth logic units is located between the first logic unit and another second logic unit in the first direction. Figure 3 As shown, the integrated circuit includes two fourth logic units L4. The two fourth logic units L4 are located between the first logic unit L1 and the two second logic units L2, respectively.

[0079] The transistors in the first logic unit L1 and the second logic unit L2 can have different threshold voltages, and the fourth logic unit L4 can be used to transition between the different threshold voltages of the transistors in the first logic unit L1 and the second logic unit L2.

[0080] Figure 4 This is a planar schematic diagram of a plurality of first logic units of an integrated circuit according to an embodiment of the present disclosure being overlapped and spliced ​​in a first direction.

[0081] According to an embodiment of this disclosure, the integrated circuit includes a plurality of first logic units, two of the plurality of first logic units are spliced ​​together in a first direction, the transistors in the two logic units have the same threshold voltage, and the two logic units can share a gate.

[0082] like Figure 4As shown, two logic units are spliced ​​together in the first direction X. The two logic units can be an inv logic unit 410 and a buf logic unit 420, respectively. The inv logic unit 410 can include five gates 409, and the buf logic unit 420 can include six gates 409. When the transistors in the inv logic unit 410 and the buf logic unit 420 have the same threshold voltage, the inv logic unit 410 and the buf logic unit 420 can share a single gate 409. In this case, only ten gates 409 need to be designed, which can reduce the splicing distance between devices and logic units and improve the area utilization of the integrated circuit layout. Figure 4 Gate 409 in the middle can be with Figure 1 The gate 109 is the same.

[0083] Figure 5 This is a planar schematic diagram of a plurality of first logic units of an integrated circuit according to an embodiment of the present disclosure, which are spliced ​​together in a first direction without overlap.

[0084] According to an embodiment of this disclosure, the integrated circuit includes a plurality of first logic units, two of the plurality of first logic units are spliced ​​together in a first direction, the transistors in the two logic units have different threshold voltages, and two adjacent gates in the two logic units are spaced apart.

[0085] like Figure 5 As shown, two logic units are joined together in the first direction X. These two logic units can be an inv logic unit 510 and a buf logic unit 520. The inv logic unit 510 may include five gates 509, and the buf logic unit 520 may include six gates 509. When the transistor threshold voltages in the inv logic unit 510 and the buf logic unit 520 are different, two adjacent gates 409 in the inv logic unit 510 and the buf logic unit 520 can be spaced apart. The spacing between the two gates 409 can be set to 0.09 μm. Figure 5 Gate 509 in the middle can be with Figure 1 The gate 109 in the middle can be the same.

[0086] Figure 6 This is a planar schematic diagram showing that a plurality of first logic units of an integrated circuit according to an embodiment of the present disclosure are overlapped and spliced ​​in a second direction.

[0087] According to an embodiment of this disclosure, the integrated circuit includes a plurality of first logic units, two of which are spliced ​​together in a second direction, and the two logic units share a first connection portion or a second connection portion; the two logic units are arranged symmetrically with respect to an axis of symmetry, the axis of symmetry extending along a first direction and extending through the shared first connection portion or second connection portion.

[0088] like Figure 6 As shown, two logic units 600 are joined together in the second direction Y, and the two logic units share a first connection portion 601. The two logic units 600 are arranged symmetrically with respect to an axis of symmetry 602, which extends along the first direction X and passes through the shared first connection portion 601. The first connection portion 601 can be replaced by a second connection portion. Figure 6 Gate 609 in the middle can be with Figure 1 The gate 109 in the middle can be the same.

[0089] Figure 7 This is a flowchart of an integrated circuit design method according to an embodiment of the present disclosure.

[0090] Method 700 can be executed by a design tool. In some example embodiments, the design tool may include multiple instructions executed by a processor. An integrated circuit can be defined by multiple logic units, and an integrated circuit can be designed using a cell library that includes information about the multiple logic units.

[0091] like Figure 7 As shown, the method 700 may include the following operations S710 to S720.

[0092] When operating the S710, a logic unit library is provided.

[0093] When operating the S720, multiple logic units are selected from the logic unit library and combined to form an integrated circuit.

[0094] According to embodiments of this disclosure, the logic unit library may include multiple logic units, and at least one of the multiple logic units may be the aforementioned logic unit 100.

[0095] The logic unit library may also include modular macrocells and input / output units. Modular macrocells may include ROM (Read-Only Memory) and RAM (Random Access Memory). Logic units may also include inverters, AND gates, registers, selectors, full adders, combinational logic circuits, sequential logic circuits, latches, and registers, etc.

[0096] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0097] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A logic unit for an integrated circuit, characterized in that, The logic unit includes: The first semiconductor region, wherein one of the P-type semiconductor and the N-type semiconductor is located in the first semiconductor region; The second semiconductor region, wherein the other of the P-type semiconductor and the N-type semiconductor is located in the second semiconductor region; A first voltage connection portion is used to electrically connect the first semiconductor region to a first voltage; The second voltage connection portion is used to electrically connect the second semiconductor region to the second voltage; A first transistor region, wherein at least one first transistor is located in the first transistor region; The second transistor region, at least one second transistor is located in the second transistor region; A gate connection region, wherein at least one gate connection portion is located in the gate connection region. Wherein, the at least one first transistor has a fin transistor structure, the at least one second transistor has a fin transistor structure, the gate of the at least one first transistor and the gate of the at least one second transistor both extend along a second direction, the first voltage connection portion and the second voltage connection portion both extend along a first direction, and the first direction and the second direction intersect. The at least one gate connection portion is used to lead out the gate of the at least one first transistor and the gate of the at least one second transistor, respectively; The orthographic projection of the first transistor region along a third direction at least partially overlaps with the orthographic projection of the first semiconductor region along a third direction, and the orthographic projection of the second transistor region along a third direction at least partially overlaps with the orthographic projection of the second semiconductor region along a third direction, wherein the third direction is perpendicular to both the first direction and the second direction; and The first voltage connection portion, the first transistor region, the gate connection region, the second transistor region, and the second voltage connection portion are arranged sequentially along the second direction.

2. The logic unit according to claim 1, characterized in that, The size of the first transistor region is designed to accommodate 2 to 6 fins; and / or the size of the second transistor region is designed to accommodate 2 to 6 fins.

3. The logic unit according to claim 1, characterized in that, The logic unit further includes a plurality of first metal traces, at least one of the first metal traces being used to electrically connect the first connection portion and the first voltage, and at least another first metal trace being used to electrically connect the second connection portion and the second voltage; The logic unit further includes a plurality of second metal traces, the plurality of second metal traces being used to lead out at least one electrode of the at least one first transistor and at least one second transistor; and The line width of the first metal trace is greater than the line width of the second metal trace.

4. An integrated circuit, characterized in that, The integrated circuit includes multiple logic units, which are assembled to form the integrated circuit, and at least one of the multiple logic units is a logic unit as described in any one of claims 1 to 3.

5. The integrated circuit according to claim 4, characterized in that, The plurality of logic units include a first logic unit and a plurality of second logic units. The first logic unit is located in the middle region of the integrated circuit, and the plurality of second logic units are located on both sides of the first logic unit in a first direction. The plurality of second logic units are used to terminate the extension of the active regions of the at least one first transistor and the at least one second transistor in the first direction and to make the integrated circuit meet the design rules in the first direction.

6. The integrated circuit according to claim 5, characterized in that, The plurality of logic units further includes a plurality of third logic units located on both sides of the first logic unit in the second direction. The plurality of third logic units are used to terminate the extension of the gates of the at least one first transistor and the at least one second transistor in the second direction and to make the integrated circuit meet the design rules in the second direction.

7. The integrated circuit according to claim 4, characterized in that, The plurality of logic units further includes a plurality of fourth logic units, one of which is located in a first direction between a first logic unit and a second logic unit, and another of which is located in a first direction between a first logic unit and another second logic unit. The transistors in the first logic unit and the second logic unit have different threshold voltages, and the fourth logic unit is used to transition between the different threshold voltages of the transistors in the first logic unit and the second logic unit.

8. The integrated circuit according to claim 4, characterized in that, The integrated circuit includes a plurality of first logic units, two logic units of which are spliced ​​together in a first direction, the transistors in the two logic units have the same threshold voltage, and the two logic units share a single gate; and / or, The integrated circuit includes a plurality of first logic units, two of which are spliced ​​together in a first direction, the transistors in the two logic units have different threshold voltages, and two adjacent gates in the two logic units are spaced apart.

9. The integrated circuit according to claim 4, characterized in that, The integrated circuit includes a plurality of first logic units, two of which are spliced ​​together in a second direction, and the two logic units share a first connection portion or a second connection portion; the two logic units are arranged symmetrically with respect to an axis of symmetry, which extends along a first direction and passes through the shared first connection portion or second connection portion.

10. A method for designing an integrated circuit, characterized in that, The method includes: A logic unit library is provided, wherein the logic unit library includes a plurality of logic units, at least one of the plurality of logic units being a logic unit as described in any one of claims 1 to 3; and Multiple logic units are selected from the logic unit library, and the multiple logic units are spliced ​​together to form an integrated circuit.

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