Chip layout legalization detection method and device, electronic equipment and storage medium

Abstract

The application discloses a chip layout legalization detection method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring the to-be-detected edge information corresponding to each unit, and determining the edge range corresponding to the to-be-detected edge information; determining a detection window according to the edge range; determining the unit distribution information in each detection window according to the detection window, and determining a chip layout legalization detection result according to the unit distribution information. By acquiring the to-be-detected edge information corresponding to each unit in the chip, the corresponding edge range is determined, and then the corresponding detection window of each unit is generated. The unit distribution information in the corresponding range can be determined by the detection window, and then the legalization detection result of the chip unit layout is determined, so that the effectiveness and efficiency of the chip layout legalization detection for the unit edge violation phenomenon can be improved.

Description

Technical Field

[0001] This application relates to the technical field of integrated circuit design, and specifically to a chip layout legality detection method, apparatus, electronic device, and storage medium. Background Technology

[0002] In the field of integrated circuit design, there are three stages: overall placement, legalized placement, and detailed placement. In the legalized placement stage, it is necessary to determine whether each cell conforms to the corresponding placement legality, that is, whether there are any violations at the cell edges that do not comply with design specifications. Cell edge violations refer to the phenomenon of adjacent cells that may cause violations, and are divided into two categories: horizontal and vertical.

[0003] Currently, for very large-scale integrated circuit design, chip size has been significantly reduced. For mixed row and high cell layouts, there is a lack of effective layout detection methods and tools. Therefore, it is particularly important to improve the effectiveness of chip layout legalization detection for cell edge violations.

[0004] The background description is provided for the purpose of understanding the relevant technologies in this field and is not intended as an admission of prior art. Summary of the Invention

[0005] Therefore, the present invention aims to provide a chip layout legality detection method, apparatus, electronic device, and storage medium, which determines the corresponding edge range by obtaining the edge information to be detected corresponding to each unit in the chip, and then generates a corresponding detection window for each unit. The detection window can determine the unit distribution information within the corresponding range, and then determine the legality detection result of the chip unit layout, which can improve the effectiveness and efficiency of chip layout legality detection for unit edge violations.

[0006] In a first aspect, embodiments of the present invention provide a chip layout legality detection method, the method comprising:

[0007] Obtain the edge information to be detected corresponding to each unit, and determine the edge range of YFZN2022041A corresponding to the edge information to be detected;

[0008] The detection window is determined based on the edge range;

[0009] Based on the detection window, determine the cell distribution information within each detection window, and based on the cell distribution information, determine the chip layout legality detection result.

[0010] As an optional implementation, the step of obtaining the edge information to be detected corresponding to each unit and determining the edge range corresponding to the edge information to be detected includes:

[0011] Obtain the initial edge information corresponding to each unit;

[0012] Perform a flipping process in a first direction and / or a second direction on each of the units, and obtain the target edge information after the flipping process;

[0013] The initial edge information and / or the target edge information are used as the edge information to be detected;

[0014] Based on the edge information to be detected, the edge range corresponding to the edge information to be detected is determined.

[0015] As an optional implementation, determining the edge range corresponding to the edge information to be detected based on the edge information to be detected includes:

[0016] Based on the edge information to be detected, multiple edge types are determined;

[0017] Determine the edge space corresponding to each edge type, and determine the target distance between each edge type;

[0018] The edge space and the target distance are used as the edge range.

[0019] As an optional implementation, determining the detection window based on the edge range includes:

[0020] Based on the edge range, the unit information of the corresponding unit is determined; the unit information includes one or more of the following: first coordinates, second coordinates, first edge position, second edge position, first height, and second height;

[0021] Based on the unit information, the detection window information is determined; the detection window information includes one or more of the following: third coordinate, fourth coordinate, window width, and window height;

[0022] The detection window is determined based on the detection window information.

[0023] As an optional implementation, the third coordinate is determined in the following way:

[0024] The third coordinate is determined based on the sum of the first coordinate and the first edge position;

[0025] Furthermore, the fourth coordinate is determined in the following manner:

[0026] The fourth coordinate is determined based on the sum of the second coordinate and the first height; YFZN2022041A

[0027] Furthermore, the window width is determined in the following manner:

[0028] The window width is determined based on the difference between the second edge position and the first edge position;

[0029] Furthermore, the window height is determined in the following manner:

[0030] The window height is determined based on the second height.

[0031] As an optional implementation, determining the unit distribution information within each detection window based on the detection window includes:

[0032] Determine the detection bitmap based on the detection window;

[0033] Based on the detection bitmap, determine the number of units and the unit type within the detection window range, as the unit distribution information;

[0034] The step of determining the chip layout legality detection result based on the unit distribution information includes:

[0035] If the number of units and / or the unit type do not meet the preset conditions, the chip is determined to not meet the layout legalization conditions.

[0036] In a second aspect of this invention, a chip layout legitimacy detection device is provided, the device comprising:

[0037] An edge determination module is used to acquire the edge information to be detected corresponding to each unit and determine the edge range corresponding to the edge information to be detected.

[0038] A window determination module is used to determine a detection window based on the edge range;

[0039] The legality detection module is used to determine the cell distribution information within each detection window based on the detection window, and to determine the chip layout legality detection result based on the cell distribution information.

[0040] As an optional implementation, the edge determination module acquires the edge information to be detected corresponding to each unit, and determines the specific method for determining the edge range corresponding to the edge information to be detected, including:

[0041] Obtain the initial edge information corresponding to each unit;

[0042] Perform a flipping process in a first direction and / or a second direction on each of the units, and obtain the target edge information after the flipping process;

[0043] The initial edge information and / or the target edge information are used as the edge information to be detected;

[0044] Based on the edge information to be detected, the edge range corresponding to the edge information to be detected is determined.

[0045] As an optional implementation, the edge determination module determines the specific method of the edge range corresponding to the edge information to be detected based on the edge information to be detected, including:

[0046] YFZN2022041A

[0047] Based on the edge information to be detected, multiple edge types are determined;

[0048] Determine the edge space corresponding to each edge type, and determine the target distance between each edge type;

[0049] The edge space and the target distance are used as the edge range.

[0050] As an optional implementation, the window determination module determines the specific method of the detection window based on the edge range, including:

[0051] Based on the edge range, the unit information of the corresponding unit is determined; the unit information includes one or more of the following: first coordinates, second coordinates, first edge position, second edge position, first height, and second height;

[0052] Based on the unit information, the detection window information is determined; the detection window information includes one or more of the following: third coordinate, fourth coordinate, window width, and window height;

[0053] The detection window is determined based on the detection window information.

[0054] As an optional implementation method,

[0055] The third coordinate is determined by the window determination module in the following way:

[0056] The third coordinate is determined based on the sum of the first coordinate and the first edge position;

[0057] Furthermore, the fourth coordinate is determined by the window determination module in the following manner:

[0058] The fourth coordinate is determined based on the sum of the second coordinate and the first height;

[0059] Furthermore, the window width is determined by the window determination module in the following manner:

[0060] The window width is determined based on the difference between the second edge position and the first edge position;

[0061] Furthermore, the window height is determined by the window determination module in the following manner:

[0062] The window height is determined based on the second height.

[0063] As an optional implementation, the legalization monitoring module determines the specific method of the unit distribution information within each detection window according to the detection window, including:

[0064] Determine the detection bitmap based on the detection window;

[0065] Based on the detection bitmap, determine the number of units and the unit type within the detection window range, as the unit distribution information;

[0066] The step of determining the chip layout legality detection result based on the unit distribution information includes:

[0067] If the number of units and / or the unit type do not meet the preset conditions, the chip is determined to not meet the layout legalization conditions.

[0068] In a third aspect, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the chip layout legality detection method of any embodiment of the present invention.

[0069] In a fourth aspect, embodiments of the present invention provide an electronic device, including: a processor and a memory storing a computer program, wherein the processor is configured to execute a chip layout legality detection method according to any embodiment of the present invention when running the computer program.

[0070] In the chip layout legality detection method used in this embodiment of the invention, the corresponding edge range is determined by obtaining the edge information to be detected corresponding to each unit in the chip, and then a corresponding detection window is generated for each unit. The detection window can determine the unit distribution information within the corresponding range, and then determine the legality detection result of the chip unit layout. This can improve the effectiveness and efficiency of chip layout legality detection for unit edge violations.

[0071] Other optional features and technical effects of the embodiments of the present invention are partly described below and partly apparent from reading this document. Attached Figure Description

[0072] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The elements shown are not limited to the scale shown in the drawings, and the same or similar reference numerals in the drawings denote the same or similar elements, wherein:

[0073] Figure 1An example flowchart of a chip layout legality detection method according to an embodiment of the present invention is shown;

[0074] Figure 2 Another example flowchart of the chip layout legality detection method according to an embodiment of the present invention is shown;

[0075] Figure 3 An example application scenario diagram of the chip layout legality detection method according to an embodiment of the present invention is shown;

[0076] Figure 4 The diagram illustrates another example application scenario of the chip layout legality detection method according to an embodiment of the present invention;

[0077] Figure 5 An exemplary structural diagram of a chip layout legalization detection apparatus according to an embodiment of the present invention is shown;

[0078] Figure 6 An exemplary structural schematic diagram of an electronic device capable of implementing the method according to an embodiment of the present invention is shown. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0080] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0081] In the field of integrated circuit design, there are three stages: overall placement, legalized placement, and detailed placement. In the legalized placement stage, it is necessary to determine whether each cell conforms to the corresponding placement legality, that is, whether there are any violations at the cell edges that do not comply with design specifications. Cell edge violations refer to the phenomenon of adjacent cells that may cause violations, which are divided into two categories: horizontal and vertical. This will affect the quality of chip design. Furthermore, if the conditions for legalized placement are not met, subsequent detailed placement will be difficult to carry out. Legalization checks can include checking whether parameters such as cell position, cell type, and cell characteristics within a preset range conform to preset placement rules.

[0082] Currently, for very large-scale integrated circuit design, due to the significant reduction in chip size, there is a lack of effective layout detection methods and tools for mixed row and height cell layouts. Therefore, it is particularly important to improve the effectiveness of chip layout legalization detection for cell edge violations.

[0083] In the chip layout legality detection method used in this embodiment of the invention, the corresponding edge range is determined by obtaining the edge information to be detected corresponding to each unit in the chip, and then a corresponding detection window is generated for each unit. The detection window can determine the unit distribution information within the corresponding range, and then determine the legality detection result of the chip unit layout. This can improve the effectiveness and efficiency of chip layout legality detection for unit edge violations.

[0084] YFZN2022041A

[0085] Example 1

[0086] Please see Figure 1 , Figure 1 This is an example flowchart of a chip layout legality detection method disclosed in an embodiment of the present invention. Figure 1 As shown, the chip layout legality detection method may include the following operations:

[0087] S101. Obtain the edge information to be detected corresponding to each unit, and determine the edge range corresponding to the edge information to be detected;

[0088] Based on the input file, edge information for various edge types corresponding to each unit can be obtained, thereby determining the corresponding edge range. The edge range can include the edge space and the minimum distance that needs to be maintained between edges, as detailed in subsequent implementation methods.

[0089] S102. Determine the detection window based on the edge range;

[0090] The detection window can coincide with the edge range, or it can be designed based on the information indicated by the edge range. The detection window can be used to determine the violation of the unit edge layout within the window. Specifically, it can be used to determine whether parameters such as unit position, unit type, and unit characteristics conform to preset layout rules and other unit distribution information.

[0091] S103. Based on the detection window, determine the unit distribution information within each detection window, and based on the unit distribution information, determine the chip layout legality detection result.

[0092] As mentioned above, the detection window of the corresponding unit can be further determined based on the edge information to be detected in each unit. Then, by determining the unit distribution information within the detection window, the legality detection result of the chip unit layout can be determined.

[0093] By obtaining the edge information to be detected for each unit in the chip, the corresponding edge range is determined, and then a corresponding detection window is generated for each unit. The detection window can determine the unit distribution information within the corresponding range, and thus determine the legality detection result of the chip unit layout. This can improve the effectiveness and efficiency of chip layout legality detection for unit edge violations.

[0094] As an optional implementation, the step of obtaining the edge information to be detected corresponding to each unit and determining the edge range corresponding to the edge information to be detected includes:

[0095] Obtain the initial edge information corresponding to each unit;

[0096] Perform a flipping process in a first direction and / or a second direction on each of the units, and obtain the target edge information after the flipping process;

[0097] The initial edge information and / or the target edge information are used as the edge information to be detected;

[0098] Based on the edge information to be detected, the edge range corresponding to the edge information to be detected is determined.

[0099] The edge information to be detected may include only the initial edge information of each unit before processing. Since the layout legalization detection process may involve image flipping or even rotation, target edge information corresponding to the initial edge information can be obtained by pre-flipping to enrich the data and improve the accuracy and effectiveness of layout legalization detection. For details, please refer to the implementation method in Embodiment 2.

[0100] Furthermore, as an optional implementation, the images of each unit may be subjected to rotation or scaling, or a combination of these processes may be implemented to obtain target edge information. This is an extension scheme that is easy for those skilled in the art to conceive of, and will not be elaborated here.

[0101] By obtaining richer and more accurate edge information through flipping processing, the accuracy and effectiveness of chip layout legalization detection for cell edge violations can be improved.

[0102] As an optional implementation, determining the edge range corresponding to the edge information to be detected based on the edge information to be detected includes:

[0103] Based on the edge information to be detected, multiple edge types are determined;

[0104] Determine the edge space corresponding to each edge type, and determine the target distance between each edge type;

[0105] The edge space and the target distance are used as the edge range.

[0106] A unit may include multiple edge types, and different edge types may include different edge spaces. When edges of different types are adjacent, there may also be a preset target distance between the edges. In the subsequent detection process, it is necessary to ensure that the edge space and target distance corresponding to each edge type meet the corresponding preset conditions. For details, please refer to the implementation method in Embodiment 2.

[0107] By using the edge information to be detected for each unit, multiple edge types can be identified. This allows for the determination of the edge space corresponding to each edge type and the target distance between each pair of edge types, thereby improving the accuracy of the edge range and ultimately enhancing the accuracy and effectiveness of chip layout legalization detection for violations at unit edges.

[0108] This embodiment provides a chip layout legality detection method. The method includes: acquiring edge information to be detected corresponding to each unit, and determining the edge range corresponding to the edge information to be detected; determining a detection window based on the edge range; determining unit distribution information within each detection window based on the detection window, and determining the chip layout legality detection result based on the unit distribution information. By acquiring the edge information to be detected corresponding to each unit in the chip to determine the corresponding edge range, and then generating a corresponding detection window for each unit, the detection window can determine the unit distribution information within the corresponding range, thereby determining the chip unit layout legality detection result, which can improve the effectiveness and efficiency of chip layout legality detection for unit edge violations.

[0109] Example 2

[0110] Please see Figure 2 , Figure 2 This is an example flowchart of another chip layout legality detection method disclosed in an embodiment of the present invention. Figure 2 As shown, based on any other embodiment, the method includes:

[0111] S201. Obtain the edge information to be detected corresponding to each unit, and determine the edge range corresponding to the edge information to be detected;

[0112] For a detailed description of S201 and subsequent S205, please refer to the relevant descriptions of S101 and S103 in Embodiment 1, which will not be repeated here.

[0113] S202. Based on the edge range, determine the unit information of the corresponding unit; the unit information includes one or more of the following: first coordinates, second coordinates, first edge position, second edge position, first height and second height;

[0114] S203. Determine the detection window information based on the unit information; the detection window information includes one or more of the following: third coordinate, fourth coordinate, window width, and window height;

[0115] S204. Determine the detection window based on the detection window information;

[0116] S205. Based on the detection windows, determine the unit distribution information within each detection window, and based on the unit distribution information, determine the chip layout legality detection result.

[0117] The first coordinate and the second coordinate are used to indicate the position of the unit, the first height and the second height are used to indicate the shape or occupied area of ​​the unit, and the first edge position and the second edge position are used to indicate the position of the edge corresponding to the unit.

[0118] In addition, the third and fourth coordinates can be used to indicate the position of the detection window, and the window width and window height can be used to indicate the shape of the detection window.

[0119] By using preset conditions, the parameters in the detection window information can be specifically determined according to the parameters in the unit information, and then referred to the next implementation method for execution.

[0120] By determining the specific cell information of the corresponding cell through the edge range, the detection window information used to indicate the detection window can be further determined, which improves the accuracy of the determined detection window, thereby improving the accuracy and effectiveness of chip layout legalization detection for cell edge violations.

[0121] As an optional implementation method,

[0122] The third coordinate was determined in the following way:

[0123] The third coordinate is determined based on the sum of the first coordinate and the first edge position;

[0124] Furthermore, the fourth coordinate is determined in the following manner:

[0125] The fourth coordinate is determined based on the sum of the second coordinate and the first height;

[0126] Furthermore, the window width is determined in the following manner:

[0127] The window width is determined based on the difference between the second edge position and the first edge position;

[0128] Furthermore, the window height is determined in the following manner:

[0129] The window height is determined based on the second height.

[0130] By setting preset conditions, the parameters in the detection window information can be determined based on the parameters in the cell information, which improves the accuracy of the determined detection window and thus improves the accuracy and effectiveness of chip layout legalization detection for cell edge violations.

[0131] Please see Figure 3 , Figure 3 This is an example application scenario diagram of the chip layout legality detection method according to an embodiment of the present invention. For example... Figure 3 As shown in the figure, 1a is a target unit, Group1 and Group2 indicate two types of edges on the target unit, and 1b, 1c and 1d are used to indicate the flipping methods in different directions. As described in the relevant content of Embodiment 1, the edge information to be detected may only include the initial edge information of each unit before processing. Since the layout legalization detection process may involve image flipping or even rotation, the target edge information corresponding to the initial edge information can also be obtained by performing flipping processing in advance. Therefore, the four images 1a to 1d can all be used as the edge information to be detected to enrich the edge information data, thereby improving the accuracy and effectiveness of layout legalization detection.

[0132] Please see Figure 4 , Figure 4 This is another example application scenario diagram of the chip layout legality detection method according to an embodiment of the present invention. For example... Figure 4 As shown, layout violations at the edges of units can be detected using a defined detection window. Specifically, assuming that units c1 and c2 overlap vertically and that unit c2 has an edge at its bottom, the overlap between the detection window of unit c1 and unit c2 indicates a violation at that position. In addition, detection methods include determining whether parameters such as unit position, unit type, and unit characteristics conform to preset layout rules and other unit distribution information.

[0133] As an optional implementation, determining the unit distribution information within each detection window based on the detection window includes:

[0134] Determine the detection bitmap based on the detection window;

[0135] Based on the detection bitmap, determine the number of units and the unit type within the detection window range, as the unit distribution information;

[0136] The step of determining the chip layout legality detection result based on the unit distribution information includes:

[0137] If the number of units and / or the unit type do not meet the preset conditions, the chip is determined to not meet the layout legalization conditions.

[0138] The detection bitmap can be used to indicate the portion of the detection window where detection information is acquired. By determining whether other units exist within the detection bitmap range, it can be determined whether a unit has an edge violation. Taking the detection of whether the top of a unit has a violation as an example, all units are first traversed, and units with bottom edges are recorded, including their position, size, and the edge type of their bottom edges. The corresponding detection window can then be generated using the aforementioned method, thus obtaining the detection bitmap. Using this detection bitmap, if it is determined that other units exist within the detection bitmap range, it can be determined that a chip layout in that part does not meet the layout legality conditions.

[0139] By using the detection bitmap corresponding to the detection window, it is possible to determine whether the number and type of cells within the detection window meet the preset conditions, which can improve the effectiveness of chip layout legalization detection for cell edge violations.

[0140] Example 3

[0141] In some embodiments, the chip layout legality detection apparatus may incorporate the chip layout legality detection method features of any embodiment, and vice versa.

[0142] Embodiment 3 of the present invention also provides a chip layout legalization detection device to implement the aforementioned method. Please refer to [link to related documentation]. Figure 5 , Figure 5 This is an exemplary structural diagram of a chip layout legalization detection device disclosed in an embodiment of the present invention. Figure 5 As shown, based on any other embodiment, the apparatus includes:

[0143] The edge determination module 31 is used to acquire the edge information to be detected corresponding to each unit and determine the edge range corresponding to the edge information to be detected;

[0144] The window determination module 32 is used to determine the detection window based on the edge range;

[0145] The legalization detection module 33 is used to determine the unit distribution information within each detection window based on the detection window, and to determine the chip layout legalization detection result based on the unit distribution information.

[0146] By obtaining the edge information to be detected for each unit in the chip, the corresponding edge range is determined, and then a corresponding detection window is generated for each unit. The detection window can determine the unit distribution information within the corresponding range, and thus determine the legality detection result of the chip unit layout. This can improve the effectiveness and efficiency of chip layout legality detection for unit edge violations.

[0147] As an optional implementation, the edge determination module 31 acquires the edge information to be detected corresponding to each unit, and determines the specific method for determining the edge range corresponding to the edge information to be detected, including:

[0148] Obtain the initial edge information corresponding to each unit;

[0149] Perform a flipping process in a first direction and / or a second direction on each of the units, and obtain the target edge information after the flipping process;

[0150] The initial edge information and / or the target edge information are used as the edge information to be detected;

[0151] Based on the edge information to be detected, the edge range corresponding to the edge information to be detected is determined.

[0152] By obtaining richer and more accurate edge information through flipping processing, the accuracy and effectiveness of chip layout legalization detection for cell edge violations can be improved.

[0153] As an optional implementation, the edge determination module 31 determines the specific method of the edge range corresponding to the edge information to be detected based on the edge information to be detected, including:

[0154] Based on the edge information to be detected, multiple edge types are determined;

[0155] Determine the edge space corresponding to each edge type, and determine the target distance between each edge type;

[0156] The edge space and the target distance are used as the edge range.

[0157] By using the edge information to be detected for each unit, multiple edge types can be identified. This allows for the determination of the edge space corresponding to each edge type and the target distance between each pair of edge types, thereby improving the accuracy of the edge range and ultimately enhancing the accuracy and effectiveness of chip layout legalization detection for violations at unit edges.

[0158] As an optional implementation, the window determination module 32 determines the specific method of the detection window based on the edge range, including:

[0159] Based on the edge range, determine the unit information of the corresponding unit; the unit information includes one or more of the following: first coordinates, second coordinates, first edge position, second edge position, and YFZN2022041A.

[0160] First altitude and second altitude;

[0161] Based on the unit information, the detection window information is determined; the detection window information includes one or more of the following: third coordinate, fourth coordinate, window width, and window height;

[0162] The detection window is determined based on the detection window information.

[0163] By determining the specific cell information of the corresponding cell through the edge range, the detection window information used to indicate the detection window can be further determined, which improves the accuracy of the determined detection window, thereby improving the accuracy and effectiveness of chip layout legalization detection for cell edge violations.

[0164] As an optional implementation method,

[0165] The third coordinate is determined by the window determination module 32 in the following manner:

[0166] The third coordinate is determined based on the sum of the first coordinate and the first edge position;

[0167] Furthermore, the fourth coordinate is determined by the window determination module 32 in the following manner:

[0168] The fourth coordinate is determined based on the sum of the second coordinate and the first height;

[0169] Furthermore, the window width is determined by the window determination module 32 in the following manner:

[0170] The window width is determined based on the difference between the second edge position and the first edge position;

[0171] Furthermore, the window height is determined by the window determination module 32 in the following manner:

[0172] The window height is determined based on the second height.

[0173] By setting preset conditions, the parameters in the detection window information can be determined based on the parameters in the cell information, which improves the accuracy of the determined detection window and thus improves the accuracy and effectiveness of chip layout legalization detection for cell edge violations.

[0174] As an optional implementation, the legalization monitoring module 33 determines the specific method of the unit distribution information within each detection window according to the detection window, including:

[0175] Determine the detection bitmap based on the detection window;

[0176] Based on the detection bitmap, determine the number of units and the unit type within the detection window range, as the unit distribution information;

[0177] By using the detection bitmap corresponding to the detection window, it is possible to determine whether the number and type of cells within the detection window meet the preset conditions, which can improve the effectiveness of chip layout legalization detection for cell edge violations.

[0178] Example 4

[0179] In an embodiment of the present invention, an electronic device is provided, including: a processor and a memory storing a computer program, wherein the processor is configured to execute a chip layout legality detection method according to any embodiment of the present invention when running the computer program.

[0180] Figure 6 The diagram illustrates a method for implementing embodiments of the present invention or an electronic device 1000 for implementing embodiments of the present invention. In some embodiments, it may include more or fewer electronic devices than illustrated. In some embodiments, it may be implemented using a single or multiple electronic devices. In some embodiments, it may be implemented using cloud-based or distributed electronic devices.

[0181] like Figure 6 As shown, the electronic device 1000 includes a processor 1001, which can perform various appropriate operations and processes based on programs and / or data stored in read-only memory (ROM) 1002 or programs and / or data loaded from storage portion 1008 into random access memory (RAM) 1003. The processor 1001 may be a multi-core processor or may contain multiple processors. In some embodiments, the processor 1001 may include a general-purpose main processor and one or more special coprocessors, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), digital signal processor (DSP), etc. Various programs and data required for the operation of the electronic device 1000 are also stored in RAM 1003. The processor 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0182] The processor and memory described above are used together to execute programs stored in the memory. When the program is executed by a computer, it can implement the methods, steps, or functions described in the above embodiments.

[0183] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, touchscreen, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 1010 as needed so that computer programs read from it can be installed into storage section 1008 as needed. Figure 6 The diagram only shows a portion of the components and does not imply that the computer system 1000 only includes... Figure 6 The components shown.

[0184] The systems, devices, modules, or units described in the above embodiments can be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, smartphone, personal computer, laptop computer, in-vehicle human-machine interface device, personal digital assistant, media player, navigation device, game console, tablet computer, wearable device, smart TV, Internet of Things system, smart home, industrial computer, server, or a combination thereof.

[0185] Although not shown, in this embodiment of the invention, a storage medium is provided storing a computer program configured to execute, when run, any file-difference-based compilation method of this embodiment of the invention.

[0186] Storage media in embodiments of the present invention include articles that are permanent and non-permanent, removable and non-removable, capable of storing information by any method or technology. Examples of storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0187] The methods, programs, systems, apparatuses, etc., in the embodiments of the present invention can be executed or implemented in one or more networked computers, or practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected via a communication network.

[0188] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.

[0189] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of the present invention do not necessarily have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0190] This document describes several embodiments of the present invention; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, terms such as "an embodiment," "some embodiments," "example," and "specific YFZN2022041A" are used.

[0191] The terms "example" or "some examples" are intended to apply to at least one embodiment or example of the invention, but not all embodiments. These terms do not necessarily refer to the same embodiment or example. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of those different embodiments or examples.

[0192] The exemplary systems and methods of the present invention have been specifically shown and described with reference to the above embodiments, which are merely examples of the best mode for implementing the systems and methods. Those skilled in the art will understand that various changes can be made to the embodiments of the systems and methods described herein without departing from the spirit and scope of the invention as defined in the appended claims when implementing the systems and / or methods.

Claims

1. A method for detecting the legitimacy of chip layout, characterized in that, The method includes: Obtain the edge information to be detected corresponding to each unit, and determine the edge range corresponding to the edge information to be detected; Based on the edge range, a detection window is determined, including: Based on the edge range, the unit information of the corresponding unit is determined; the unit information includes one or more of the following: first coordinates, second coordinates, first edge position, second edge position, first height, and second height; Based on the unit information, detection window information is determined; the detection window information includes one or more of the following: third coordinate, fourth coordinate, window width, and window height; wherein, The third coordinate is determined based on the sum of the first coordinate and the first edge position; the fourth coordinate is determined based on the sum of the second coordinate and the first height; the window width is determined based on the difference between the second edge position and the first edge position; and the window height is determined based on the second height. The detection window is determined based on the detection window information; Based on the detection window, determine the cell distribution information within each detection window, and based on the cell distribution information, determine the chip layout legality detection result.

2. The method according to claim 1, characterized in that, The step of acquiring the edge information to be detected corresponding to each unit and determining the edge range corresponding to the edge information to be detected includes: Obtain the initial edge information corresponding to each unit; Perform a flipping process in a first direction and / or a second direction on each of the units, and obtain the target edge information after the flipping process; The initial edge information and / or the target edge information are used as the edge information to be detected; Based on the edge information to be detected, the edge range corresponding to the edge information to be detected is determined.

3. The method according to claim 2, wherein determining the edge range corresponding to the edge information to be detected based on the edge information to be detected includes: Based on the edge information to be detected, multiple edge types are determined; Determine the edge space corresponding to each edge type, and determine the target distance between each edge type; The edge space and the target distance are used as the edge range.

4. The method according to claim 1, characterized in that, The step of determining the unit distribution information within each detection window based on the detection window includes: Determine the detection bitmap based on the detection window; Based on the detection bitmap, determine the number of units and the unit type within the detection window range, as the unit distribution information; The step of determining the chip layout legality detection result based on the unit distribution information includes: If the number of units and / or the unit type do not meet the preset conditions, the chip is determined to not meet the layout legalization conditions.

5. A chip layout legality detection device, characterized in that, The device includes: An edge determination module is used to acquire the edge information to be detected corresponding to each unit and determine the edge range corresponding to the edge information to be detected. A window determination module is used to determine a detection window based on the edge range; the window determination module is configured to: Based on the edge range, the unit information of the corresponding unit is determined; the unit information includes one or more of the following: first coordinates, second coordinates, first edge position, second edge position, first height, and second height; Based on the unit information, detection window information is determined; the detection window information includes one or more of the following: third coordinate, fourth coordinate, window width, and window height; wherein, The third coordinate is determined based on the sum of the first coordinate and the first edge position; the fourth coordinate is determined based on the sum of the second coordinate and the first height; the window width is determined based on the difference between the second edge position and the first edge position; and the window height is determined based on the second height. The detection window is determined based on the detection window information; The legality detection module is used to determine the cell distribution information within each detection window based on the detection window, and to determine the chip layout legality detection result based on the cell distribution information.

6. The apparatus according to claim 5, characterized in that, The edge determination module acquires the edge information to be detected corresponding to each unit, and determines the specific method for determining the edge range corresponding to the edge information to be detected, including: Obtain the initial edge information corresponding to each unit; Perform a flipping process in a first direction and / or a second direction on each of the units, and obtain the target edge information after the flipping process; The initial edge information and / or the target edge information are used as the edge information to be detected; Based on the edge information to be detected, the edge range corresponding to the edge information to be detected is determined.

7. A storage medium having a computer program stored thereon, wherein, The program is executed by the processor to implement the chip layout legality detection method as described in any one of claims 1-4.

8. An electronic device, characterized in that, include: The processor and the memory storing a computer program, the processor being configured to implement the chip layout legality detection method according to any one of claims 1-4 when running the computer program.

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