Fgpa-based target detection target detection method and system

Abstract

The application discloses a target for target detection and a detection method and system thereof based on FPGA, and relates to the field of target detection. The target is composed of a white rectangle and a black rectangular frame surrounding the white rectangle. The method sets a first two-dimensional array to store row pixel coordinates of the target, sets a second two-dimensional array to store white pixel block coordinates of the current row pixels of the target, and calculates the mass center of the target based on the first two-dimensional array after the two are associated. The system comprises an FPGA for implementing the detection method, a camera for collecting images, and a host computer for receiving data. The application is convenient for implementing the target detection algorithm on the FPGA, can reduce the memory occupation during the implementation of the algorithm, does not need a DSP chip and a RAM chip, and is low in system cost.

Description

Technical Field

[0001] This invention relates to the field of target detection, specifically to a target detection method and system based on FGPA. Background Technology

[0002] Target detection is an important component of visible light-based non-contact measurement technology, with wide applications in measurement, monitoring, and counting. To improve the accuracy of target detection, carefully designed cooperative markers (targets) are usually affixed to the surface of the target. Detection of the target is then performed instead of detecting the natural object, achieving higher detection accuracy.

[0003] The current standard process for target detection is as follows: First, image data is acquired using a data acquisition card and sent to a host computer. Then, the host computer calls an image processing algorithm to detect the target. In scenarios with high real-time requirements, the data transmission bandwidth and the CPU processing power of the host computer often fail to meet these requirements. Image acquisition cards typically use FPGA chips to acquire image data. If the target detection algorithm can be ported to an FPGA chip, bandwidth can be saved, and the fast processing power of the FPGA can be utilized. Therefore, porting the target detection algorithm to an FPGA chip is a hot research direction in engineering practice. This direction can be further subdivided into two sub-directions: one is the FPGA+DSP approach, where the FPGA controls the data flow and the DSP runs the target detection algorithm; the other is where both data flow control and the target detection algorithm run in the FPGA. Furthermore, commonly used targets include... Figure 1 The examples shown are several. The detection processes for these targets are all quite complex and not easily implemented in an FPGA.

[0004] In existing technical literature [Liu Peng, Wang Xiaoman, Zhong Gang, et al. Target dynamic detection and tracking technology based on DSP and FPGA [J]. Journal of Jilin University (Information Science Edition), 2010, 27(6):8-12.], the authors studied dynamic target images in the target range based on DSP and FPGA digital image processing technology, proposed a detection scheme, and found the target in the target range in the image captured by the CCD system in the weapon equipment dynamic detection and tracking accuracy test system, and marked the bullseye, thereby achieving accurate target aiming. However, it has the following problems: 1. The target design is not conducive to retrieval. The literature uses cross-shaped targets, which have fewer effective pixels and are prone to being lost in situations such as out-of-focus or overexposure. In addition, the cross-shaped target retrieval algorithm is relatively complex and not easy to port.

[0005] 2. High system cost. The system designed in the literature requires an additional DSP chip, which increases the system cost.

[0006] 3. It cannot be ported to FPGA chips with limited memory, or requires an additional RAM chip. According to the algorithm used in the literature, target retrieval needs to be performed after receiving the amplified image. Taking a 1920*1080 resolution, 8-bit single-channel digital image as an example, one image requires... Ordinary FPGA chips typically have less than [a certain amount of memory]. .

[0007] 4. Not suitable for multi-target detection. The algorithm used in the literature can only perform single-target detection. In real-world scenarios, there may be multiple targets, requiring the simultaneous detection of the coordinates of these targets.

[0008] With the development of image acquisition technology, image resolution is constantly improving, requiring more memory, while users are also placing higher demands on the real-time performance of algorithms. How to simultaneously meet the needs of large data volumes and high real-time performance is a valuable research direction. FPGA, as the core chip of image acquisition cards, possesses extremely high data processing performance. If image processing algorithms can be ported to FPGA, the performance of the entire system will be greatly improved. Summary of the Invention

[0009] This invention provides a target detection method and system based on FPGA to solve the problem that existing technologies cannot achieve multiple target detection using only FPGA.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The target for object detection consists of a white rectangle and a black bounding box surrounding the white rectangle.

[0011] The target detection method based on FGPA is as follows: The FPGA acquires the image data of the multiple targets mentioned above. For each target, the FPGA acquires the pixel data of each row of the target line by line. The FPGA establishes a first two-dimensional array in its internal memory to store the starting coordinates (x, y, y) of each row of pixels for each target in the image. 起 y 起 ) and ending coordinates (x) 结 y 结 ), where (x 起 y 起 x represents the coordinates of the first pixel in each row of pixels in the image. 起 y represents the column coordinate of the first pixel in each row of pixels in the image. 起 This represents the row coordinate of the first pixel in each row of pixels in the image; (x 结 y 结 x is the coordinate of the last pixel in each row of pixels in the image. 结The y-coordinate represents the column coordinate of the last pixel in each row of pixels in the image. 结 This represents the row coordinates of the last pixel in each row of pixels in the image; the start and end coordinates of pixels in each row of the same target are stored in the same row of the first two-dimensional array in the order of being acquired row by row, and the start and end coordinates of pixels in each row of different targets are stored in different rows of the first two-dimensional array. When the FPGA acquires the current row pixel data of each target, it retrieves the white pixel blocks in the current row pixel data of each target and establishes a second two-dimensional array in its internal memory to store the interval coordinates of the white pixel blocks in the current row pixels of each target in the image. The interval coordinates of the white pixel blocks in the current row pixels of the same target are stored in the same row of the second two-dimensional array, and the interval coordinates of the white pixel blocks in the current row pixels of different targets are stored in different rows of the second two-dimensional array. The FPGA searches the second two-dimensional array and the first two-dimensional array. When it finds that the row coordinate of a white pixel block in the corresponding row of a target in the second two-dimensional array is adjacent to the row coordinate of the end of a row of pixels in the corresponding row of the same target in the first two-dimensional array, the interval coordinate of the retrieved white pixel block is added to the end of the row of pixels in the first two-dimensional array that is adjacent to the row coordinate of the corresponding row of the same target. This completes the association between the start and end coordinates of the row pixels of each target in the first two-dimensional array and the white pixel blocks in the current row pixels of each target in the second two-dimensional array. After association is completed, each row in the second two-dimensional array used to store the interval coordinates of white pixel blocks in the current row of pixels of each target is cleared to store the interval coordinates of white pixel blocks in the subsequent rows of pixels of the corresponding target in the image. The above process is repeated until the start and end coordinates of all rows of pixels of each target are associated with the white pixel blocks of all rows of the corresponding target, and a new first two-dimensional array is obtained. The FPGA iterates through the new first two-dimensional array and calculates the centroid of each target based on the start and end coordinates of each row of pixels of each target stored in the new first two-dimensional array, as well as the interval coordinates of the associated white pixel blocks.

[0012] Furthermore, in each row of the first two-dimensional array, the first byte is used to indicate whether the row is occupied.

[0013] Furthermore, in each row of the first two-dimensional array, the second and third bytes are used to indicate the total number of rows containing the corresponding target row pixels.

[0014] Furthermore, when the FPGA acquires the current row of pixel data of a target, it retrieves the white pixel blocks in the current row of pixel data of the target, removes the white pixel blocks whose length is greater than or equal to a preset threshold, and then stores the interval coordinates of each white pixel block whose length is less than the preset threshold in the corresponding row of the second two-dimensional array.

[0015] Furthermore, when the FPGA searches the second two-dimensional array and the first two-dimensional array, if the first two-dimensional array is found to be empty, it directly stores the interval coordinates of the white pixel block in the current row of each target in the second two-dimensional array in the blank position in the first two-dimensional array where the start and end coordinates of the corresponding target's current row of pixels should be stored.

[0016] Furthermore, when any white pixel block in the current row of a target in the second two-dimensional array cannot be associated with the first two-dimensional array, the FPGA creates a new row corresponding to the target in the first two-dimensional array and stores the interval coordinates of each white pixel block in the current row of the target in the second two-dimensional array in the corresponding row of the first two-dimensional array.

[0017] Furthermore, when associating each target, the total column span of each row of pixels of the target in the first two-dimensional array is calculated in the image. If the total column span is not within the preset threshold range, then the row corresponding to the target is deleted from the first two-dimensional array and the second two-dimensional array respectively.

[0018] Furthermore, after obtaining the new first two-dimensional array, the new first two-dimensional array is traversed, and the total row span of each row of pixels of each target in the image is calculated. If the total row span is not within the set threshold range, the row corresponding to the target is removed from the new first two-dimensional array.

[0019] The target detection system based on FPGA includes an FPGA. The data input port of the FPGA is connected to an image acquisition device, and the data output port of the FPGA is connected to a host computer through an I / O board. The FPGA executes the detection method described above.

[0020] This invention addresses the shortcomings of the literature "Target Dynamic Detection and Tracking Technology Based on DSP and FPGA" by making targeted improvements. The target pattern is redesigned, reducing the complexity of the target detection algorithm and improving the stability of image acquisition. This invention does not require additional DSP and RAM chips, reducing system cost and facilitating portability to existing image acquisition systems. The target detection algorithm primarily retrieves targets through row scanning, and since the FPGA also acquires image data row by row, it achieves immediate processing upon acquisition, with image data occupying minimal memory, making it easy to port to FPGAs with limited memory. The target detection algorithm supports simultaneous detection of multiple targets, expanding the system's application scope.

[0021] This invention facilitates the implementation of a target detection algorithm on an FPGA. During detection, only a small amount of data needs to be cached, and interfering targets are dynamically cleared, further reducing memory usage and making it easy to port to FPGA chips with limited memory. The algorithm supports simultaneous detection of multiple targets at the sub-pixel level, enabling its wide range of applications. Interference is eliminated through various conditional thresholds during detection, demonstrating strong resistance to background interference. The core of the entire system is the FPGA chip, eliminating the need for DSP and RAM chips, resulting in low system cost. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of existing target detection technology, in which: (a) is a concentric circle target; (b) is a cross-shaped target; (c) is a square array target; and (d) is a circular target.

[0023] Figure 2 This is a schematic diagram of Embodiment 1 of the present invention.

[0024] Figure 3 This is a flowchart of the method in Embodiment 2 of the present invention.

[0025] Figure 4 This is a schematic diagram of the storage principle of the first two-dimensional array PixeList in Embodiment 2 of the present invention.

[0026] Figure 5 This is a schematic diagram of the storage principle of the second two-dimensional array PixelRowList in Embodiment 2 of the present invention.

[0027] Figure 6 This is a schematic diagram of the system structure of Embodiment 3 of the present invention.

[0028] Figure 7 This is a schematic diagram of the FPGA internal algorithm recognition program instruction in Embodiment 3 of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the embodiments will be described in detail below with reference to the accompanying drawings and examples. This will allow for a full understanding of how the present invention uses technical means to solve technical problems and achieve corresponding technical effects, and to facilitate its implementation. The embodiments of the present invention and the various features within them can be combined with each other without conflict, and all resulting technical solutions are within the protection scope of the present invention.

[0030] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products or devices. Example

[0032] This embodiment discloses a target detection target suitable for FPGA detection, such as Figure 2 As shown, it includes a white rectangle and a black rectangular frame surrounding the white rectangle, with the white rectangle and the black rectangular frame being concentric. In this embodiment, the white rectangle is preferably a shape with equal length and width, i.e., a white square; the black rectangular frame is preferably formed with equal length and width, i.e., a black square frame. Example

[0033] This embodiment discloses a target detection method based on FGPA. This method detects the target detection targets described in Embodiment 1, such as... Figure 3 As shown, the process is as follows: (1) The target described in Example 1 is set at multiple positions on the target object. Images of each target are acquired by a CMOS camera, and the acquired image data is transmitted to the FPGA by the CMOS camera. When the FPGA acquires the image data of each target, it acquires the pixel data of each row of the target in the order of row scanning of the target, and then binarizes the pixel data of each row.

[0034] (2) When the FPGA acquires image data and performs binarization, a first two-dimensional array PixeList is established in the FPGA's internal RAM to store the starting coordinates (x, y, x) of each row of pixels of each target in the image. 起 y 起 ) and ending coordinates (x) 结 y 结 Among them: (x) 起 y 起 x represents the coordinates of the first pixel in each row of pixels in the image. 起 y represents the column coordinate of the first pixel in each row of pixels in the image. 起 This represents the row coordinate of the first pixel in each row of pixels in the image; (x 结 y 结 x is the coordinate of the last pixel in each row of pixels in the image. 结 The y-coordinate represents the column coordinate of the last pixel in each row of pixels in the image. 结 This represents the row coordinates of the last pixel in each row of pixels within the image.

[0035] For a single pixel in a row of a target, since they belong to the same row in the image, their row coordinate y in the starting coordinates of the image is... 起 The row coordinate y in the ending coordinates 结 Same, meaning the y-coordinates of pixels in the same row of a target. 起 =y 结 For example, a target has M columns and N rows of pixels. The starting coordinates of the first row of pixels in the image are (1,1) and the ending coordinates are (M,1). The starting coordinates of the second row of pixels in the image are (1,2) and the ending coordinates are (M,2), and so on. The starting coordinates of the Nth row of pixels in the image are (1,N) and the ending coordinates are (M,N).

[0036] In the first two-dimensional array PixeList, the start and end coordinates of pixels in each row of the same target are stored in the same row of the first two-dimensional array PixeList in the order they are obtained row by row. The corresponding data for different targets are stored in different rows of the first two-dimensional array PixeList. Figure 4 Taking the three targets A, B, and C as an example, the first row of the first two-dimensional array PixeList stores the corresponding data of each row of pixels for target A; the second row stores the corresponding data of each row of pixels for target B; and the third row stores the corresponding data of each row of pixels for target C. This continues until there are Z targets, at which point the corresponding data of the Zth target is stored in the Zth row of the first two-dimensional array PixeList.

[0037] In the first two-dimensional array PixeList, the first byte of each row stores a boolean variable to indicate whether the row is occupied, i.e., whether there is target data stored there. When the boolean variable is 1, it means that the row has been used, and when the boolean variable is 0, it means that the row has not been used. In this embodiment, the initial value of the boolean variable of the first byte of each row in the first two-dimensional array PixeList is 0. When target data is stored there, the boolean variable is set to 1.

[0038] In the first two-dimensional array PixeList, the second and third bytes of each row together store a 16-bit counter, which represents the total number of rows of pixels corresponding to the target row stored in that row. The second and third bytes of each row in the first two-dimensional array PixeList are initially 0. When the FPGA stores the corresponding data of each row of a target into the first two-dimensional array PixeList, the counter counts to obtain the total number of rows of pixels corresponding to the target row.

[0039] The remaining bytes of each row in the first two-dimensional array PixeList are used to store the start and end coordinates of the pixels in each row of the target, i.e., the start coordinates (x, y, x).起 y 起 ) and ending coordinates (x) 结 y 结 For example, the first row of the first two-dimensional array PixeList corresponds to target A. The first row of PixeList contains a Boolean scalar and a counter, respectively. The rows following the first row store the starting coordinates (1,1) and ending coordinates (M,1) of the first row of pixels in target A, the starting coordinates (1,2) and ending coordinates (M,2) of the second row of pixels in target A, and so on, up to the starting coordinates (1,N) and ending coordinates (M,N) of the Nth row of pixels in target A. In other words, by scanning row by row, the starting and ending coordinates of each row of pixels for each target are stored in the corresponding row position in the first two-dimensional array PixeList. 起 y 起 x 结 y 结 Each coordinate is represented by two bytes, so the start and end coordinates of a row of pixels on a target occupy a total of eight bytes. If a target has N rows of pixels, then the start and end coordinates of the N rows of pixels occupy a total of 8N bytes.

[0040] When the FPGA acquires the current row pixel data for each target, it first scans the current row pixel data of each target, retrieves white pixel blocks in the current row pixel data of each target, and removes white pixel blocks whose length is greater than or equal to a preset threshold. The FPGA then creates a second two-dimensional array, PixelRowList, in its internal memory. The data in the second two-dimensional array PixelRowList is initially 0, and it is used to store the interval coordinates of the remaining white pixel blocks in the image after removal from the current row pixel data of each target. The interval coordinates of white pixel blocks in the same target's current row pixel data are stored in the same row of the second two-dimensional array, while the interval coordinates of white pixel blocks in different target's current row pixel data are stored in different rows of the second two-dimensional array.

[0041] by Figure 5 Taking the second two-dimensional array PixelRowList as an example, the first row of the second two-dimensional array PixelRowList is used to store the interval coordinates of each remaining white pixel block in the current row of the first target. The second row of the second two-dimensional array PixelRowList is used to store the interval coordinates of each remaining white pixel block in the current row of the second target, and so on. The Zth row of the second two-dimensional array PixelRowList is used to store the interval coordinates of each remaining white pixel block in the current row of the Zth target.

[0042] Since each row in the second two-dimensional array PixelRowList stores the coordinates of white pixel blocks representing the same target and the same current row in the image, the row coordinates of all white pixel blocks stored in each row of the second two-dimensional array PixelRowList are the same. Figure 5 Taking the target A corresponding to the first row of the second two-dimensional array PixelRowList as an example, the current row of pixels in target A is the last row (i.e., row N) of the target. The row coordinates of each white pixel block in the last row of target A are all N, but the column spans of each white pixel block may be different. Therefore, the column coordinates of each white pixel block in the Nth row of target A are all range values. For example, the first white pixel block in the Nth row of target A has 3 white pixels, and their coordinates in the image are (1, N), (2, N), (...). If the first white pixel block has coordinates (1-3, N), then the coordinates of the first white pixel block in the image are (1-3, N); the second white pixel block in the Nth row of the target A has 4 white pixels, and the coordinates of these white pixels in the image are (5, N), (6, N), (7, N), (8, N) respectively. Therefore, the coordinates of the second white pixel block in the image are (5-8, N); and so on. The first row of the second two-dimensional array PixelRowList stores the coordinates of each white pixel block in the Nth row of the target A, such as (1-3, N), (5-8, N), etc.

[0043] The FPGA retrieves the second two-dimensional array PixelRowList and the first two-dimensional array PixeList. When the first two-dimensional array PixeList is found to be empty, the interval coordinates of the white pixel block in the current row of each target in the second two-dimensional array PixelRowList are directly stored in the blank positions in the first two-dimensional array PixeList where the start and end coordinates of the corresponding target current row of pixels should be stored.

[0044] If the first two-dimensional array `PixeList` is not empty, and the row coordinates of a white pixel block stored in the corresponding row of a target in the second two-dimensional array `PixelRowList` are found to be adjacent to the row coordinates of the end coordinates of a row of pixels stored in the corresponding row of the target in the first two-dimensional array `PixeList`, then the range coordinates of the retrieved white pixel block are added to the end coordinates of the adjacent row of pixels in the first two-dimensional array `PixeList`. This completes the association between the start and end coordinates of the row pixels of each target in the first two-dimensional array `PixeList` and the white pixel blocks in the current row of pixels of each target in the second two-dimensional array `PixelRowList`. For example, when a white pixel block with the range coordinates (5-9,8) in the 8th row of pixels of a target is retrieved in the second two-dimensional array `PixelRowList`, then the range coordinates (5-9,8) of the white pixel block are added to the row coordinates of the end coordinates of the corresponding row of pixels in the first two-dimensional array `PixeList`, i.e., the row coordinates of the adjacent row of pixels. 结 =7 row pixel end coordinate (x 结 Following , 7), this completes the white pixel block with coordinates (5-9,8) in the current 8th row of the target, and connects it with the end coordinate of the row of pixels in the first two-dimensional array PixeList with coordinates (x, 7). 结 The association of the 7th row of pixels in , 7).

[0045] When the FPGA detects that any white pixel block in the current row of a target in the second two-dimensional array PixelRowList cannot be associated with the first two-dimensional array PixeList, the FPGA creates a new row corresponding to the target in the first two-dimensional array PixeList and stores the interval coordinates of each white pixel block in the current row of the target in the second two-dimensional array PixelRowList in the newly created row corresponding to the target in the first two-dimensional array PixeList.

[0046] When each target is associated, the total column span of each row of pixels in the image is calculated based on the start and end coordinates of the pixels in each row of the target in the first two-dimensional array PixeList. If the total column span is not within the preset threshold range, the row corresponding to the target is deleted from both the first two-dimensional array PixeList and the second two-dimensional array PixelRowList.

[0047] After the association is completed, each row in the second two-dimensional array PixelRowList, which is used to store the interval coordinates of the white pixel block in the current row of pixels of each target, is cleared to store the interval coordinates of the white pixel block in the subsequent row of pixels of the corresponding target in the image. The above process is repeated until the start and end coordinates of all rows of pixels of each target are associated with the white pixel blocks of all rows of the corresponding target, and a new first two-dimensional array PixeList is obtained.

[0048] (3) After the association is completed, first traverse the new first two-dimensional array PixeList. Based on the start and end coordinates of each row of pixels of each target in the image, calculate the total row span of each row of pixels of each target in the image. If the total row span is not within the set threshold range, remove the row of data corresponding to the target from the new first two-dimensional array PixeList.

[0049] Then, based on the start and end coordinates of each row of pixels for each target stored in the new first two-dimensional array PixeList, and the interval coordinates of the associated white pixel blocks, the centroid of the corresponding target is calculated. After obtaining the centroids of each target, the target object can be obtained based on the positional relationship of each target on the target object. Example

[0050] This embodiment discloses an FGPA-based target detection system that implements the detection method described in Embodiment 2, such as... Figure 6 As shown, the system includes a CMOS camera as an image acquisition device, an FPGA, and a host computer. The CMOS camera can achieve a maximum frame rate of 2500fps. This embodiment enables real-time target recognition and position coordinate output at 2500fps. Image data from the CMOS camera is output to the FPGA via LVDS, where it is received and buffered. The FPGA then transmits the image data to the ARM on the I / O board via a coaxial cable. The I / O board then transmits the data to the host computer via a gigabit network. Simultaneously, after the FPGA performs detection according to the detection method described in Embodiment 2, it outputs the detection result data to the ARM on the I / O board via a coaxial cable. The I / O board then transmits the data to the host computer via an RS422 interface. The recognition algorithm of this invention runs in the FPGA's internal RAM, performing real-time target detection. Position data is output through the RS422 interface of the I / O board, with one position data packet output for each frame.

[0051] The FPGA's internal RAM stores the algorithm recognition program instructions, which consist of six main sub-modules. These modules work in conjunction with the clock reset module (CLK_RST_GEN) and the I2C register configuration module (i2c_slave_app) to complete their functions. The CLK_RST_GEN module provides the system clock and reset, while the i2c_slave_app is responsible for parsing external control commands and configuring the corresponding registers.

[0052] The six sub-modules are Pre_Process, Verify_Line, Verify_Region, Protocol, RS422_Tx, and Decode_Timestamp. These modules collectively handle image data input, preprocessing, recognition, and protocol output. The location of each module and the data flow are as follows: Figure 7 As shown.

[0053] The `Decode_Timestamp` module parses the image frame header, which is located in the first 32 frames of each image data stream, totaling 1024 bytes. This module buffers and reassembles the frame header data, extracts the timestamp data, and outputs it. As shown in the diagram above, the output of this module is connected to the `Protocol` module, which encapsulates the timestamp information into the protocol packet.

[0054] The Pre_Process module primarily handles image data preprocessing, including binarization, data caching, and median filtering. Third-order median filtering is used to remove potential salt-and-pepper pixel noise from the original image, improving the adaptability of the recognition algorithm. Binarization performs binarization on pixel data based on a brightness threshold. This operation removes a large amount of redundant information from the image, making the target information more prominent and facilitating subsequent recognition. Binarization also significantly reduces the amount of image data, the number of cache registers, and FPGA resource consumption, thereby improving efficiency.

[0055] Verify_Line and Verify_Region are the core recognition modules, working together to identify the target region and output the coordinates of the target's center point. Since the image is input row by row, the Verify_Line module identifies possible valid pixels in each row and the X-axis coordinates of its left and right boundaries based on preset parameters for target width features, and uses this output as input to Verify_Region. Verify_Region performs a matching test on the output of the Verify_Line module based on the target's width and height features. If the row number of a region matches the target's height feature, and the difference in X-coordinates between adjacent rows is within a preset threshold, the region is considered valid. Verify_Region then records the boundary pixels of the region and calculates the region's centroid, i.e., the pixel coordinates of the target's center point.

[0056] The Protocol module is responsible for caching the coordinates of all targets and outputting data according to the protocol at the end of the frame. Internally, this module contains a FiFO unit that caches target coordinate data. When the end-of-frame marker arrives, the module first outputs the protocol frame header and timestamp data, followed by the target coordinate data, and finally the protocol frame trailer.

[0057] The RS422_Tx module is a data output module, whose function is to convert input protocol data packets into standard RS422 serial port data for output. The data is then transmitted to the host computer for real-time control.

[0058] When the algorithm recognition program runs, the PC host computer first needs to configure the module parameters, mainly the target's length, width, brightness, and other feature parameters. Then, the acquisition software controls the entry into high-speed acquisition mode. After receiving the image data, the recognition module first performs image preprocessing, then identifies the valid row information and valid region information, and calculates the target center coordinates and caches them in FiFO. When the frame ends, if there is target data in FiFO, the coordinate data is sent sequentially through the RS422 serial port according to the protocol.

[0059] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. These embodiments are merely descriptions of preferred embodiments and are not intended to limit the scope or concept of the invention. The specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. Such combinations, as long as they do not violate the spirit of the present invention, should also be considered as part of this disclosure. To avoid unnecessary repetition, the present invention will not further describe the various possible combinations.

[0060] This invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this invention and without departing from the design idea of ​​this invention, all modifications and improvements made by those skilled in the art to the technical solutions of this invention should fall within the protection scope of this invention. The technical content for which protection is sought in this invention has been fully described in the claims.

Claims

1. A target detection method based on FGPA, characterized in that, The process is as follows: The FPGA acquires image data of multiple targets, each target consisting of a white rectangle and a black bounding box surrounding the white rectangle; for each target, the FPGA acquires the pixel data of each row of the target line by line. The FPGA establishes a first two-dimensional array in its internal memory to store the starting coordinates (x, y, y) of each row of pixels for each target in the image. 起 y 起 ) and ending coordinates (x) 结 y 结 ), where (x 起 y 起 x represents the coordinates of the first pixel in each row of pixels in the image. 起 y represents the column coordinate of the first pixel in each row of pixels in the image. 起 This represents the row coordinate of the first pixel in each row of pixels in the image; (x 结 y 结 x is the coordinate of the last pixel in each row of pixels in the image. 结 The y-coordinate represents the column coordinate of the last pixel in each row of pixels in the image. 结 This represents the row coordinates of the last pixel in each row of pixels in the image; the start and end coordinates of pixels in each row of the same target are stored in the same row of the first two-dimensional array in the order of being acquired row by row, and the start and end coordinates of pixels in each row of different targets are stored in different rows of the first two-dimensional array. When the FPGA acquires the current row pixel data of each target, it retrieves the white pixel blocks in the current row pixel data of each target and establishes a second two-dimensional array in its internal memory to store the interval coordinates of the white pixel blocks in the current row pixels of each target in the image. The interval coordinates of the white pixel blocks in the current row pixels of the same target are stored in the same row of the second two-dimensional array, and the interval coordinates of the white pixel blocks in the current row pixels of different targets are stored in different rows of the second two-dimensional array. The FPGA searches the second two-dimensional array and the first two-dimensional array. When it finds that the row coordinate of a white pixel block in the corresponding row of a target in the second two-dimensional array is adjacent to the row coordinate of the end of a row of pixels in the corresponding row of the same target in the first two-dimensional array, the interval coordinate of the retrieved white pixel block is added to the end of the row of pixels in the first two-dimensional array that is adjacent to the row coordinate of the corresponding row of the same target. This completes the association between the start and end coordinates of the row pixels of each target in the first two-dimensional array and the white pixel blocks in the current row pixels of each target in the second two-dimensional array. After association is completed, each row in the second two-dimensional array used to store the interval coordinates of white pixel blocks in the current row of pixels of each target is cleared to store the interval coordinates of white pixel blocks in the subsequent rows of pixels of the corresponding target in the image. The above process is repeated until the start and end coordinates of all rows of pixels of each target are associated with the white pixel blocks of all rows of the corresponding target, and a new first two-dimensional array is obtained. The FPGA iterates through the new first two-dimensional array and calculates the centroid of each target based on the start and end coordinates of each row of pixels of each target stored in the new first two-dimensional array, as well as the interval coordinates of the associated white pixel blocks.

2. The target detection method based on FGPA according to claim 1, characterized in that, In each row of the first two-dimensional array, the first byte is used to indicate whether the row is occupied.

3. The target detection method based on FGPA according to claim 1, characterized in that, In each row of the first two-dimensional array, the second and third bytes are used to indicate the total number of rows containing the corresponding target row pixels.

4. The target detection method based on FGPA according to claim 1, characterized in that, When the FPGA acquires the current row of pixel data of a target, it retrieves the white pixel blocks in the current row of pixel data of the target, removes the white pixel blocks whose length is greater than or equal to a preset threshold, and then stores the interval coordinates of each white pixel block whose length is less than the preset threshold in the corresponding row of the second two-dimensional array.

5. The target detection method based on FGPA according to claim 1, characterized in that, When the FPGA searches the second two-dimensional array and the first two-dimensional array, if the first two-dimensional array is found to be empty, the FPGA directly stores the interval coordinates of the white pixel block in the current row of each target in the second two-dimensional array in the blank position in the first two-dimensional array where the start and end coordinates of the corresponding target current row pixel should be stored.

6. The target detection method based on FGPA according to claim 1, characterized in that, When any white pixel block in the current row of a target in the second two-dimensional array cannot be associated with the first two-dimensional array, the FPGA creates a new row corresponding to the target in the first two-dimensional array and stores the interval coordinates of each white pixel block in the current row of the target in the second two-dimensional array in the corresponding row of the first two-dimensional array.

7. The target detection method based on FGPA according to claim 1, characterized in that, When each target is associated, the total column span of each row of pixels of the target in the first two-dimensional array is calculated in the image. If the total column span is not within the preset threshold range, then the row corresponding to the target is deleted from the first two-dimensional array and the second two-dimensional array respectively.

8. The target detection method based on FGPA according to claim 1, characterized in that, After obtaining the new first two-dimensional array, iterate through the new first two-dimensional array and calculate the total row span of each row of pixels of each target in the image. If the total row span is not within the set threshold range, remove the row corresponding to the target from the new first two-dimensional array.

9. A target detection system based on FGPA, characterized in that, The device includes an FPGA, whose data input port is connected to an image acquisition device, and whose data output port is connected to a host computer via an I / O board. The FPGA executes the detection method as described in any one of claims 1-8.

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