Local amplification circuit, data readout method and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a local amplification circuit, a data readout method and a memory. The local amplification circuit comprises a write control transistor, a column selection transistor, a first control NMOS transistor, a second control NMOS transistor and a pre-charge module. The write control transistor connects a global data line to a local data line based on a write enable signal. The column selection transistor connects a bit line to the local data line based on a column selection signal. The gate of the first control NMOS transistor is connected to the local data line. One end of the source or the drain of the first control NMOS transistor is connected to the global data line, and the other end of the source or the drain of the first control NMOS transistor is connected to a read control transistor. The gate of the second control NMOS transistor is connected to a complementary local data line. One end of the source or the drain of the second control NMOS transistor is connected to a complementary global data line, and the other end of the source or the drain of the second control NMOS transistor is connected to the read control transistor. The pre-charge module is configured to pre-charge the local data line to a first preset level. The read control transistor pulls up / pulls down the terminals connected to the first control NMOS transistor and the second control NMOS transistor to a second preset level based on a read enable signal, so as to shorten a time interval between the column selection signal and the read enable signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a local amplifier circuit, a data readout method, and a memory. Background Technology

[0002] During the data readout process, the data is sequentially transferred from the bit line / complementary bit line to the local data line / complementary local data line, and then to the global data line / complementary global data line. The data transfer from the local data line / complementary local data line to the global data line / complementary global data line is implemented based on the local amplifier circuit.

[0003] When performing a read operation, the local amplifier circuit needs to wait for data to be transmitted from the bit line / complementary bit line to the local data line / complementary local data line before providing a read enable signal to further read the data to the global data line / complementary global data line. If the read enable signal is provided before the data has been fully transmitted to the local data line / complementary local data line, both the local data line / complementary local data line will be at a high level, and the local data line / complementary local data line will be discharged simultaneously, causing read errors in the local amplifier circuit or unnecessary power consumption. The time interval between the column select signal and the read enable signal will affect the performance of the memory.

[0004] Therefore, there is an urgent need to design a signal readout circuit to shorten the time interval between the provision of the column select signal and the provision of the read enable signal, thereby optimizing the performance of the memory. Summary of the Invention

[0005] This disclosure provides a local amplifier circuit, a data readout method, and a memory. During the data readout stage, the time interval between the column select signal and the read enable signal is shortened to accelerate the data readout of the memory.

[0006] This disclosure provides a local amplification circuit, including: a write control transistor configured to connect a global data line to a local data line and a complementary global data line to a complementary local data line based on a write enable signal; a column select transistor configured to connect a bit line to a local data line and a complementary bit line to a complementary local data line based on a column select signal; a first control NMOS transistor with its gate connected to a local data line, and one end of its source or drain connected to a global data line, and the other end connected to a read control transistor; and a second control NMOS transistor with its gate connected to the complementary local data line, and one end of its source or drain connected to a global data line. One end is connected to the complementary global data line, and the other end is connected to the read control transistor; the precharge module is connected to the local data line and the complementary local data line, and is used to precharge the local data line and the complementary local data line to a first preset level, the first preset level being less than the threshold voltage of the first control NMOS transistor and less than the threshold voltage of the second control NMOS transistor; the read control transistor is configured to pull up / pull down the terminals of the first control NMOS transistor and the second control NMOS transistor connected to the read control transistor to a second preset level based on the read enable signal; the second preset level is opposite to the precharge level of the global data line and the complementary global data line.

[0007] Based on the local amplification circuit provided in this embodiment, the local data line and complementary local data line are precharged to a first preset level by the precharge module. The first preset level is insufficient to turn on the first control NMOS transistor and the second control NMOS transistor. During the data writing stage, a write enable signal is provided, and the data on the global data line and the complementary global data line is transmitted to the local data line and the complementary local data line. Since the read control transistor cannot be turned on, the conduction of the first control NMOS transistor and the second control NMOS transistor does not affect the data writing of the memory. During the data reading stage, a read enable signal can be provided in advance. At this time, since the first control NMOS transistor and the second control NMOS transistor cannot be turned on, the data reading of the memory is not affected. When the column select signal is provided, the data on the bit line and the complementary bit line is synchronized to the local data line and the complementary local data line. The first control NMOS transistor or the second control NMOS transistor is turned on, thereby turning on the corresponding read path and transmitting the data on the local data line and the complementary local data line to the global data line and the complementary global data line. Thus, during the data reading stage, the time interval between the column select signal and the read enable signal is shortened, and the data reading of the memory is accelerated.

[0008] In addition, the first preset level is 0.

[0009] In addition, the precharge module includes a precharge MOSFET. The gate of the precharge MOSFET is used to receive the precharge signal. One end of the source or drain is connected to the local data line and the complementary local data line, and the other end is grounded.

[0010] In addition, the global data line and the complementary global data line are precharged at a low level before data is read out, and the second preset level is high.

[0011] In addition, the global data line and the complementary global data line are precharged at a high level before data is read out, and the second preset level is low.

[0012] In addition, the write control transistor includes: a first write MOS transistor, whose gate is used to receive a write enable signal, whose source is connected to the global data line, and whose drain is connected to the local data line; and a second write MOS transistor, whose gate is used to receive a write enable signal, whose source is connected to the complementary global data line, and whose drain is connected to the complementary local data line.

[0013] In addition, the first and second write MOSFETs are PMOS transistors. Since PMOS transistors have a stronger pull-up capability than NMOS transistors, using PMOS transistors for the first and second write MOSFETs can accelerate the pull-up of the local data line or complementary local data line to a high level after the read enable signal is provided.

[0014] Additionally, the column select transistor includes: a first column select MOS transistor, whose gate is used to receive the column select signal, whose source is connected to the local data line, and whose drain is connected to the bit line; and a second column select MOS transistor, whose gate is used to receive the column select signal, whose source is connected to the complementary local data line, and whose drain is connected to the complementary bit line.

[0015] In addition, the first and second column select MOSFETs are PMOS transistors. Since PMOS transistors have stronger pull-up capabilities than NMOS transistors, using PMOS transistors for the first and second column select transistors can accelerate the pull-up of the local data line or complementary local data line to a high level after the column select signal is provided.

[0016] In addition, the read control transistor includes: a first read MOS transistor, whose gate is used to receive a read enable signal, whose source is connected to a first control NMOS transistor, and whose drain is used to receive a first preset level; and a second read MOS transistor, whose gate is used to receive a read enable signal, whose source is connected to a second control NMOS transistor, and whose drain is used to receive a first preset level.

[0017] This disclosure also provides a data readout method applied to the aforementioned local amplifier circuit, comprising: before the readout stage, pre-charging the local data line and complementary local data line to a first preset level, and pre-charging the global data line and complementary global data line to a pre-charge level; during the readout stage, providing a read enable signal, pulling the global data line high / low to a second preset level when a first control NMOS transistor is turned on, and pulling the complementary global data line high / low to a second preset level when a second control NMOS transistor is turned on; providing a column select signal to synchronize the bit line level to the local data line and the complementary bit line level to the complementary local data line; wherein the read enable signal is provided no later than the moment when the global data line or the complementary global data line undergoes a potential change based on the column select signal.

[0018] Based on the local amplifier circuit provided in this embodiment, the time interval between the column select signal and the read enable signal is shortened during the data readout stage, thereby accelerating the data readout of the memory.

[0019] In addition, the read enable signal is provided no later than the column select signal.

[0020] In addition, the read enable signal and column select signal are provided simultaneously.

[0021] This disclosure also provides a memory that uses the aforementioned local amplifier circuit for writing and reading data.

[0022] In addition, the memory includes: DRAM, SDRAM, DDR-SDRAM, DDR2-SDRAM, DDR3-SDRAM, DDR4-SDRAM, LPDDR4-SDRAM, DDR5-SDRAM, LPDDR5-SDRAM, GDDR5-SDRAM and GDDR6-SDRAM. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a local amplifier circuit provided in an embodiment of the present disclosure;

[0024] Figure 2 A timing diagram illustrating the provision of a read enable signal and a column select signal according to an embodiment of this disclosure;

[0025] Figure 3 and Figure 4 A timing diagram is provided for the signal when reading data from a local data line / complementary local data line to a global data line / complementary global data line according to an embodiment of the present disclosure;

[0026] Figure 5 This is a schematic diagram of the structure of a pre-charging module provided in an embodiment of the present disclosure;

[0027] Figure 6 This is a schematic diagram of another local amplifier circuit provided in an embodiment of the present disclosure;

[0028] Figure 7 This is a schematic flowchart of a data readout method provided in another embodiment of the present disclosure. Detailed Implementation

[0029] During the data readout process, the data is sequentially transferred from the bit line / complementary bit line to the local data line / complementary local data line, and then to the global data line / complementary global data line. The data transfer from the local data line / complementary local data line to the global data line / complementary global data line is implemented based on the local amplifier circuit.

[0030] When performing a read operation, the local amplifier circuit needs to wait for data to be transmitted from the bit line / complementary bit line to the local data line / complementary local data line before providing a read enable signal to further read the data to the global data line / complementary global data line. If the read enable signal is provided before the data has been fully transmitted to the local data line / complementary local data line, both the local data line / complementary local data line will be at a high level, and the local data line / complementary local data line will be discharged simultaneously, causing read errors in the local amplifier circuit or unnecessary power consumption. The time interval between the column select signal and the read enable signal will affect the performance of the memory.

[0031] This disclosure provides a local amplifier circuit that shortens the time interval between the column select signal and the read enable signal during the data readout stage, thereby accelerating the data readout from the memory.

[0032] It will be understood by those skilled in the art that many technical details have been presented in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Figure 1 This is a schematic diagram of the local amplifier circuit provided in this embodiment. Figure 2 This is a timing diagram illustrating the read enable signal and column select signal provided in this embodiment. Figure 3 and Figure 4 This embodiment provides a timing diagram of the signals when reading data from the local data line / complementary local data line to the global data line / complementary global data line. Figure 5 This is a schematic diagram of the pre-charging module provided in this embodiment. Figure 6 This is a schematic diagram of another local amplifier circuit provided in this embodiment. The local amplifier circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0034] refer to Figure 1 Local amplifier circuit, including:

[0035] The write control transistor 101 is configured to connect the global data line YIO to the local data line LIO and connect the complementary global data line YIO- to the complementary local data line LIO- based on the write enable signal WrEn.

[0036] The write enable signal WrEn is used to turn on the write control transistor 101; the global data line YIO and the complementary global data line YIO- are used to transmit inverted data, that is, the global data line YIO transmits high-level data and the complementary global data line YIO- transmits low-level data; the global data line YIO transmits low-level data and the complementary global data line YIO- transmits high-level data; in addition, the local data line LIO and the complementary local data line LIO- are also used to transmit inverted data.

[0037] The column select transistor 102 is configured to connect the bit line BL to the local data line LIO and the complementary bit line BLB to the complementary local data line based on the column select signal CSL.

[0038] The column select signal CSL is used to turn on the column select transistor 102; the bit line BL and the complementary bit line BLB are used to transmit inverted data, and memory cells are connected to the bit line BL and the complementary bit line BLB. When data is transmitted from the local data line LIO to the bit line BL, or from the complementary local data line LIO- to the complementary bit line BLB, it is the data storage stage of the memory; when data is transmitted from the bit line BL to the local data line LIO, or from the complementary bit line BLB to the complementary local data line LIO-, it is the data reading stage of the memory.

[0039] The first control NMOS transistor 110 has its gate connected to the local data line LIO, one end of its source or drain connected to the global data line YIO, and the other end connected to the read control transistor 103.

[0040] The second control NMOS transistor 120 has its gate connected to the complementary local data line LIO-, one end of its source or drain connected to the complementary global data line YIO-, and the other end connected to the read control transistor 103.

[0041] The first control NMOS transistor 110 is controlled by the level of the local data line LIO. When the local data line LIO is high, the first control NMOS transistor 110 is turned on, and one of the source and drain terminals of the read control transistor 103 is connected to the global data line YIO. When the local data line LIO is low, the first control NMOS transistor 110 is turned off. The second control NMOS transistor 120 is controlled by the level of the complementary local data line LIO-. When the complementary local data line LIO- is high, the second control NMOS transistor 120 is turned on, and one of the source and drain terminals of the read control transistor 103 is connected to the complementary global data line YIO-. When the complementary local data line LIO- is low, the second control NMOS transistor 120 is turned off.

[0042] The pre-charge module 104 is connected to the local data line LIO and the complementary local data line LIO-, and is used to pre-charge the local data line LIO and the complementary local data line LIO- to a first preset level V1. The first preset level V1 is less than the threshold voltage of the first control NMOS transistor and less than the threshold voltage of the second control NMOS transistor.

[0043] The read control transistor 103 is configured to pull up / pull down the terminals of the first control NMOS transistor and the second control NMOS transistor connected to the read control transistor 103 to a second preset level V2 based on the read enable signal RdEn. The second preset level V2 is opposite to the precharge level of the global data line YIO and the complementary global data line YIO-.

[0044] The read enable signal RdEn is used to turn on the read control transistor 103. When the read control transistor 103 and the first control NMOS transistor 110 are turned on, the read control transistor 103 pulls up / down the global data line YIO to the second preset level V2. When the read control transistor 103 and the second control NMOS transistor 120 are turned on, the read control transistor 103 pulls up / down the complementary global data line YIO- to the second preset level V2. The second preset level V2 is opposite to the precharge level of the global data line YIO and the complementary global data line YIO-.

[0045] Based on the local amplification circuit provided in this embodiment, the local data line LIO and the complementary local data line LIO- are precharged to a first preset level V1 by the precharge module 104. The first preset level V1 is insufficient to turn on the first control NMOS transistor 110 and the second control NMOS transistor 120. During the data writing phase, a write enable signal WrEn is provided, and data is transmitted from the global data line YIO and the complementary global data line YIO- to the local data line LIO and the complementary local data line LIO-. Since the read control transistor 103 cannot be turned on, the conduction of the first control NMOS transistor 110 and the second control NMOS transistor 120 does not affect the data writing of the memory. During the data reading phase, a read enable signal can be provided in advance. At this time, since the first control NMOS transistor 110 and the second control NMOS transistor 120 cannot be turned on, it does not affect the data readout of the memory. When the column select signal CSL is provided, the data on the bit line BL and the complementary bit line BLB are synchronized to the local data line LIO and the complementary local data line LIO-. The first control NMOS transistor 110 or the second control NMOS transistor 120 is turned on, thereby turning on the corresponding readout path and transmitting the data on the local data line LIO and the complementary local data line LIO- to the global data line YIO and the complementary global data line YIO-. This shortens the time interval between the column select signal CSL and the read enable signal RdEn during the data readout stage, thus speeding up the data readout of the memory.

[0046] It should be noted that the reference Figure 2 Based on the local amplification circuit provided in this embodiment, since there is a time delay of t1 between the provision of the column select signal CSL and the completion of the changes in the local data line LIO and the complementary local data line LIO-, it is only necessary to ensure that the read enable signal RdEn is provided before the changes in the local data line LIO and the complementary local data line LIO- are completed. This can also speed up the data reading of the memory. That is, in some embodiments, the read enable signal can be provided within the time period t1.

[0047] In some embodiments, reference Figure 3 Before data is read out, the global data line YIO and the complementary global data line YIO- are precharged at a low level, and the second preset level V2 is high. At this time, when the read control transistor 103 and the first control NMOS transistor 110 are turned on, the global data line YIO is pulled up to a high level, and when the read control transistor 103 and the second control NMOS transistor 120 are turned on, the complementary global data line YIO- is pulled up to a high level.

[0048] In some embodiments, reference Figure 4Before data is read out, the global data line YIO and the complementary global data line YIO- are precharged at a high level, and the second preset level V2 is low. At this time, when the read control transistor 103 and the first control NMOS transistor 110 are turned on, the global data line YIO is pulled down to a low level, and when the read control transistor 103 and the second control NMOS transistor 120 are turned on, the complementary global data line YIO- is pulled down to a low level.

[0049] In some embodiments, the first preset level is 0, that is, the local data line LIO and the complementary local data line LIO- are discharged before the data read or data write stage.

[0050] Specifically, refer to Figure 5 The precharge module 104 includes a precharge MOSFET 105. The gate of the precharge MOSFET 105 is used to receive the precharge signal PRE. One end of the source or drain is connected to the local data line LIO and the complementary local data line LIO-, and the other end is grounded to GND, thereby realizing the discharge of the local data line LIO and the complementary local data line LIO- controlled by the precharge signal PRE.

[0051] In some embodiments, continue to refer to Figure 1 The write control transistor 101 includes:

[0052] First write MOSFET <11> The gate is used to receive the write enable signal WrEn, the source is connected to the global data line YIO, and the drain is connected to the local data line LIO.

[0053] Second write MOSFET <12> The gate is used to receive the write enable signal WrEn, the source is connected to the complementary global data line YIO-, and the drain is connected to the complementary local data line LIO-.

[0054] In this embodiment, the first write MOS transistor <11> Second write MOSFET <12> The first transistor is an NMOS transistor; since PMOS transistors have a stronger pull-up capability than NMOS transistors, in some embodiments, the first write MOS transistor is used. <11> Second write MOSFET <12> It is a PMOS transistor, which can accelerate the pull-up of the local data line LIO or the complementary local data line LIO- to a high level after the write enable signal WrEn is provided.

[0055] In some embodiments, continue to refer to Figure 1 The column selection transistor 102 includes:

[0056] The first column selects transistors. <21> The gate is used to receive the column select signal CSL, the source is connected to the local data line LIO, and the drain is connected to the bit line BL.

[0057] The second column selects transistors. <22> The gate is used to receive the column select signal CSL, the source is connected to the complementary local data line LIO-, and the drain is connected to the complementary bit line BLB.

[0058] In this embodiment, the first column selects transistors. <21> Second column select transistor <22> For NMOS transistors; since PMOS transistors have stronger pull-up capabilities than NMOS transistors, in some embodiments, the first column of selection transistors is used. <21> Second column select transistor <22> It is a PMOS transistor, which can accelerate the pull-up of the local data line LIO or the complementary local data line LIO- to a high level after the column select signal CSL is provided.

[0059] Specifically, when the first MOS transistor is written <11> Second write MOSFET <12> For PMOS transistors, the first column selects transistors. <21> Second column select transistor <22> For PMOS transistors, please refer to the corresponding circuit diagram. Figure 6 .

[0060] In some embodiments, continue to refer to Figure 1 The read control transistor 103 includes:

[0061] First read MOSFET <31> The gate is used to receive the read enable signal RdEn, the source is connected to the first control NMOS transistor 110, and the drain is used to receive the first preset level V1.

[0062] Second read MOSFET <32> The gate is used to receive the read enable signal RdEn, the source is connected to the second control NMOS transistor 120, and the drain is used to receive the first preset level V1.

[0063] In this embodiment, the first read MOS transistor <31> Second read MOSFET <32> The first MOS transistor is an NMOS transistor. Since PMOS transistors have a stronger pull-up capability than NMOS transistors, and NMOS transistors have a stronger pull-down capability than PMOS transistors, in some embodiments, the first MOS transistor can be flexibly configured according to the magnitude of the first preset level V1. <31> Second read MOSFET <32> The type; for example, when the first preset level V1 is high, the first read MOS transistor <31> Second read MOSFET <32> For NMOS transistors, when the first preset level V1 is low, the first read MOS transistor... <31> Second read MOSFET <32> It is a PMOS transistor.

[0064] It should be noted that the specific connection method of the "source" and "drain" for the various types of MOSFETs mentioned above does not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be used.

[0065] It should be noted that the features disclosed in the monitoring circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new circuit embodiments.

[0066] Based on the local amplification circuit provided in this embodiment, the local data line LIO and the complementary local data line LIO- are precharged to a first preset level V1 by the precharge module 104. The first preset level V1 is insufficient to turn on the first control NMOS transistor 110 and the second control NMOS transistor 120. During the data writing phase, a write enable signal WrEn is provided, and data is transmitted from the global data line YIO and the complementary global data line YIO- to the local data line LIO and the complementary local data line LIO-. Since the read control transistor 103 cannot be turned on, the conduction of the first control NMOS transistor 110 and the second control NMOS transistor 120 does not affect the data writing of the memory. During the data reading phase, a read enable signal can be provided in advance. At this time, since the first control NMOS transistor 110 and the second control NMOS transistor 120 cannot be turned on, it does not affect the data readout of the memory. When the column select signal CSL is provided, the data on the bit line BL and the complementary bit line BLB are synchronized to the local data line LIO and the complementary local data line LIO-. The first control NMOS transistor 110 or the second control NMOS transistor 120 is turned on, thereby turning on the corresponding readout path and transmitting the data on the local data line LIO and the complementary local data line LIO- to the global data line YIO and the complementary global data line YIO-. This shortens the time interval between the column select signal CSL and the read enable signal RdEn during the data readout stage, thus speeding up the data readout of the memory.

[0067] Another embodiment of this disclosure provides a data readout method. Based on the local amplification circuit provided in this embodiment, the time interval between the column selection signal and the read enable signal is shortened during the data readout stage, thereby accelerating the data readout of the memory.

[0068] Figure 7 This is a flowchart illustrating the data reading method provided in this embodiment. The following is a detailed description of the data reading method provided in this embodiment with reference to the accompanying drawings:

[0069] refer to Figure 7 Data readout methods include:

[0070] Step 201: Precharge the local data line and the complementary local data line to a first preset level, and precharge the global data line and the complementary global data line to a precharge level.

[0071] Specifically, prior to the readout phase, the local and data lines and the complementary local and data lines are precharged to a first preset level, and the global data lines and the complementary global data lines are precharged to a precharge level.

[0072] Step 202: Provide a read enable signal and a column select signal. The read enable signal is provided no later than the moment when the global data line or complementary global data line changes its potential based on the column select signal.

[0073] Specifically, during the readout phase, a read enable signal is provided. When the first control NMOS transistor is turned on, the global data line is pulled high / low to a second preset level. When the second control NMOS transistor is turned on, the complementary global data line is pulled high / low to a second preset level. A column select signal is provided to synchronize the bit line level to the local data line and the complementary bit line level to the complementary local data line. The read enable signal is provided no later than the moment when the global data line or the complementary global data line changes its potential based on the column select signal.

[0074] The local data line and complementary local data line are precharged to a first preset level by a precharge module. This first preset level is insufficient to turn on the first and second control NMOS transistors. During the data writing phase, a write enable signal is provided, and data is transmitted from the global data line and complementary global data line to the local data line and complementary local data line. Since the read control transistor cannot be turned on, the conduction of the first and second control NMOS transistors does not affect the data writing process. During the data reading phase, a read enable signal can be provided in advance. Since the first and second control NMOS transistors cannot be turned on, data reading from the memory is not affected. When a column select signal is provided, the data on the bit line and complementary bit line is synchronized to the local data line and complementary local data line. The first or second control NMOS transistor is turned on, thereby opening the corresponding read path and transmitting data from the local data line and complementary local data line to the global data line and complementary global data line. This shortens the time interval between the column select signal and the read enable signal during the data reading phase, accelerating the data reading process from the memory.

[0075] Combination Figure 2 Since there is a time delay of t1 between the provision of the column select signal CSL and the completion of the changes in the local data line LIO and the complementary local data line LIO-, it is only necessary to ensure that the read enable signal RdEn is provided before the changes in the local data line LIO and the complementary local data line LIO- are completed. This can also speed up the data reading from the memory. That is, in some embodiments, the read enable signal can be provided within the time period t1; in some embodiments, the time of the read enable signal is no later than the time of the provision of the column select signal; in some embodiments, the read enable signal and the column select signal are provided simultaneously.

[0076] It should be noted that the description of the data readout method above is similar to the description of the local amplifier circuit embodiment above, and has similar beneficial effects as the local amplifier circuit embodiment, therefore it will not be repeated. For technical details not disclosed in the data readout method of this disclosure embodiment, please refer to the description of the local amplifier circuit in this disclosure embodiment for understanding.

[0077] The stage divisions of the above statistical methods are only for clarity of description. In practice, they can be merged into one statistical stage or some statistical stages can be split into multiple statistical stages. As long as the logic of the statistical methods is the same, they are all within the scope of protection of this patent. In addition, any insignificant modifications or introductions to the above statistical methods, without changing the core design of the above statistical methods, are also within the scope of protection of this patent.

[0078] Another embodiment of this disclosure provides a memory that uses the local amplifier circuit provided in the above embodiments to write and read data, thereby shortening the time interval between the column select signal and the read enable signal and speeding up the data reading of the memory.

[0079] In some embodiments, the memory is a dynamic random access memory (DRAM) chip.

[0080] In some embodiments, the memory is a dynamic random access memory (SRAM) chip.

[0081] In some embodiments, the memory is a dynamic random access memory (SDRAM) chip, wherein the memory of the SDRAM chip conforms to the DDR memory specification.

[0082] In some embodiments, the memory is a dynamic random access memory (SDRAM) chip, wherein the memory of the SDRAM chip conforms to the DDR2 memory specification.

[0083] In some embodiments, the memory is a dynamic random access memory (SDRAM) chip, wherein the memory of the SDRAM chip conforms to the DDR3 memory specification.

[0084] In some embodiments, the memory is a dynamic random access memory (SDRAM) chip, wherein the memory of the SDRAM chip conforms to the DDR4 or LPDDR4 memory specifications.

[0085] In some embodiments, the memory is a dynamic random access memory (SDRAM) chip, wherein the memory of the SDRAM chip conforms to the DDR5 or LPDDR5 memory specification.

[0086] In some embodiments, the memory is a dynamic random access memory (SDRAM) chip, wherein the memory of the SDRAM chip conforms to the GDDR5 or GDDR6 memory specifications.

[0087] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A local amplifier circuit, characterized in that, include: The write control transistor is configured to connect the global data line to the local data line and the complementary global data line to the complementary local data line based on the write enable signal. A column select transistor is configured to connect a bit line to the local data line and a complementary bit line to the complementary local data line based on a column select signal. The first control NMOS transistor has its gate connected to the local data line, one end of its source or drain connected to the global data line, and the other end connected to the read control transistor. The second control NMOS transistor has its gate connected to the complementary local data line, one end of its source or drain connected to the complementary global data line, and the other end connected to the read control transistor. A pre-charge module, connected to the local data line and the complementary local data line, is used to pre-charge the local data line and the complementary local data line to a first preset level, the first preset level being less than the threshold voltage of the first control NMOS transistor and less than the threshold voltage of the second control NMOS transistor; the pre-charge module is configured such that the first control NMOS transistor and the second control NMOS transistor are initially in a cut-off state before data is read out; The read control transistor is configured to pull up / pull down the terminals of the first control NMOS transistor and the second control NMOS transistor connected to the read control transistor to a second preset level based on a read enable signal; wherein the read enable signal is provided no later than the time when the local data line or the complementary local data line undergoes a potential change based on the column select signal; The second preset level is opposite to the precharge level of the global data line and the complementary global data line.

2. The local amplifier circuit according to claim 1, characterized in that, The first preset level is 0.

3. The local amplifier circuit according to claim 2, characterized in that, The pre-charge module includes a pre-charge MOS transistor. The gate of the pre-charge MOS transistor is used to receive a pre-charge signal. One end of the source or drain is connected to the local data line and the complementary local data line, and the other end is grounded.

4. The local amplifier circuit according to claim 1, characterized in that, The global data line and the complementary global data line are precharged at a low level before data is read out, and the second preset level is high.

5. The local amplifier circuit according to claim 1, characterized in that, The global data line and the complementary global data line are precharged at a high level before data is read out, and the second preset level is low.

6. The local amplifier circuit according to claim 1, characterized in that, The write control transistor includes: The first write MOS transistor has its gate used to receive the write enable signal, its source connected to the global data line, and its drain connected to the local data line. The second write MOS transistor has its gate used to receive the write enable signal, its source connected to the complementary global data line, and its drain connected to the complementary local data line.

7. The local amplifier circuit according to claim 6, characterized in that, The first write MOS transistor and the second write MOS transistor are PMOS transistors.

8. The local amplifier circuit according to claim 1, characterized in that, The column selection transistor includes: The first column selects the MOS transistor, with its gate used to receive the column select signal, its source connected to the local data line, and its drain connected to the bit line. The second column selects a MOS transistor, with its gate used to receive the column select signal, its source connected to the complementary local data line, and its drain connected to the complementary bit line.

9. The local amplifier circuit according to claim 8, characterized in that, The first column selects MOS transistors and the second column selects PMOS transistors.

10. The local amplifier circuit according to claim 1, characterized in that, The read control transistor includes: The first read MOS transistor has a gate for receiving the read enable signal, a source connected to the first control NMOS transistor, and a drain for receiving the first preset level. The second read MOS transistor has its gate used to receive the read enable signal, its source connected to the second control NMOS transistor, and its drain used to receive the first preset level.

11. A data readout method, applied to the local amplifier circuit according to any one of claims 1 to 10, characterized in that, include: Before the readout phase, the local data line and the complementary local data line are precharged to a first preset level, and the global data line and the complementary global data line are precharged to a precharge level. The first and second control NMOS transistors are initially in the off state before data is read out; During the readout phase, a read enable signal is provided. When the first control NMOS transistor is turned on, the global data line is pulled high / low to a second preset level. When the second control NMOS transistor is turned on, the complementary global data line is pulled high / low to a second preset level. Provide a column select signal to synchronize the bit line level to the local data line and the complementary bit line level to the complementary local data line; The read enable signal is provided no later than the moment when the local data line or the complementary local data line undergoes a potential change based on the column select signal.

12. The data reading method according to claim 11, characterized in that, The read enable signal is provided no later than the column select signal.

13. The data reading method according to claim 12, characterized in that, The read enable signal and the column select signal are provided simultaneously.

14. A memory, characterized in that, Data is written and read using the local amplifier circuit described in any one of claims 1 to 10.

15. The memory according to claim 14, characterized in that, The memory includes: DRAM, SDRAM, DDR-SDRAM, DDR2-SDRAM, DDR3-SDRAM, DDR4-SDRAM, LPDDR4-SDRAM, DDR5-SDRAM, LPDDR5-SDRAM, GDDR5-SDRAM and GDDR6-SDRAM.

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