Word line drive circuit, word line drive method, and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a word line driving circuit, a word line driving method and a memory, which comprises: a driving inverter, an input end of the driving inverter being configured to receive a word line control signal, and an output end of the driving inverter being configured to output a word line driving signal, the word line driving signal being configured to drive at least one sub-word line driver; the sub-word line driver comprising a first input end, a second input end, a third input end and an output end; the sub-word line driver being configured to synchronize data inputted by the second input end or data inputted by the third input end to the output end based on data inputted by the first input end; a first control module, an output end of the first control module being connected to the second input end, and the first control module being configured to pull up a first driving signal based on a first control signal; and a second control module, an output end of the second control module being connected to the second input end, and the second control module being configured to pull down the first driving signal based on the first control signal, and a voltage pull-down rate of the first driving signal satisfying a preset value, so as to improve the reliability of a PMOS in the sub-word line driving circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a word line driving circuit, a word line driving method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. The selection of the capacitor is controlled by a transistor connected in series with the capacitor, and the selection of the transistor is controlled by word lines and bit lines.

[0003] During the word line driving process of DRAM, the gate-source voltage difference of PMOS in the sub-word line driving circuit in the waiting state is relatively large, resulting in a serious PMOS leakage problem, which reduces the reliability of the sub-word line driving circuit.

[0004] How to reduce the leakage current of the sub-line drive circuit is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a word line driving circuit, a word line driving method, and a memory. When the sub-word line driving circuit is in a waiting state, the leakage current of the sub-word line driving circuit is reduced to improve the reliability of the sub-word line driving circuit.

[0006] This disclosure provides a word line driving circuit, including: a driving inverter with an input terminal for receiving a word line control signal and an output terminal for outputting a word line driving signal, the word line driving signal driving at least one sub-word line driver; the sub-word line driver includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal for receiving the word line driving signal, the second input terminal for receiving a first driving signal, the third input terminal for receiving a word line shutdown voltage, and the output terminal for connecting to a word line; the sub-word line driver is configured to synchronize data input from the second input terminal or the third input terminal to the output terminal based on data input from the first input terminal; a first control module with its output terminal connected to the second input terminal, configured to pull up the first driving signal based on the first control signal; a second control module with its output terminal connected to the second input terminal, configured to pull down the first driving signal based on the first control signal, and the voltage pull-down rate of the first driving signal satisfies a preset value; the first control module and the second control module are activated based on different levels of the first control signal.

[0007] During the driving phase, the first control module pulls up the first driving signal based on the first control signal. The word line driving signal controls the sub-word line driver to synchronize the data input from the second input terminal to the word line, that is, to transmit the pulled-up first driving signal to the word line to turn on the corresponding word line. During the transition from the driving phase to the waiting phase, the word line driving signal controls the sub-word line driver to synchronize the data input from the third input terminal to the word line, that is, to transmit the word line shutdown voltage to the word line to turn off the corresponding word line. The second control module pulls down the first driving signal based on the first control signal. At this time, the word line driving signal received by the first input terminal of the sub-word line driver is at a high level, and the first driving signal received by the second input terminal is at a low level. There is a voltage difference between the first input terminal and the second input terminal. By limiting the voltage pull-down rate of the first driving signal by the second control module, the first driving signal shows a slow decreasing trend during the waiting phase, thereby reducing the average voltage difference between the first input terminal and the second input terminal of the sub-word line driver during the waiting process, thereby reducing the leakage current of the sub-word line driving circuit and improving the reliability of the sub-word line driving circuit.

[0008] In addition, the preset value for the voltage pull-down rate of the first drive signal is: the voltage pull-down rate is less than 5V / ns.

[0009] Additionally, the sub-word line driver includes: a driving PMOS transistor and a first driving NMOS transistor; the gate of the first driving NMOS transistor and the gate of the driving PMOS transistor are connected as a first input terminal; the source of the driving PMOS transistor serves as a second input terminal; the source of the first driving NMOS transistor serves as a third input terminal; the drain of the driving PMOS transistor and the drain of the first driving NMOS transistor serve as output terminals; during the waiting phase, the word line driving signal received by the gate of the driving PMOS transistor is at a high level, and the first driving signal received by the source is at a low level. The driving PMOS transistor experiences leakage current at both its gate and source. By limiting the voltage pull-down rate of the first driving signal through the second control module, the first driving signal exhibits a slow decreasing trend during the waiting phase, thereby reducing the average voltage difference between the gate and source of the driving PMOS transistor during the waiting phase, thus reducing the leakage current of the driving PMOS transistor and improving the reliability of the sub-word line driving circuit.

[0010] In addition, the word line driving circuit also includes: a control inverter and a second driving NMOS transistor; the input terminal of the control inverter is used to receive a second control signal, and the output terminal is used to output a second driving signal; the source of the second driving NMOS transistor is connected to the source of the first driving NMOS transistor; the gate of the second driving NMOS transistor is used to receive the second driving signal; the drain of the second driving NMOS transistor is used to connect to the word line; the word line voltage is synchronously pulled down by the second driving NMOS transistor to improve the pull-down rate of the word line potential.

[0011] In addition, the first control module includes a first MOSFET, and the second control module includes a second MOSFET. The drain of the first MOSFET and the drain of the second MOSFET are connected together and connected to the second input terminal. The gate of the first MOSFET and the gate of the second MOSFET are connected together and used to receive a first control signal. The source of the first MOSFET is used to receive the word line turn-on voltage, and the source of the second MOSFET is grounded. When the second MOSFET is turned on, the voltage pull-down rate of the first drive signal meets a preset value. By limiting the pull-down rate of the first drive signal when the second MOSFET is turned on, the pull-down rate of the first drive signal by the second control module is realized.

[0012] Additionally, the first control module includes a first MOSFET, and the second control module includes a second MOSFET and a third MOSFET. The drains of the first and third MOSFETs are connected and connected to the second input terminal. The source of the third MOSFET is connected to the drain of the second MOSFET. The gates of the first and second MOSFETs are connected and used to receive a first control signal. The source of the first MOSFET is used to receive the word line turn-on voltage, the source of the second MOSFET is grounded, and the gate of the third MOSFET is used to receive a floating control signal. Under the same overdrive voltage, the signal conduction capability of the third MOSFET is less than that of the second MOSFET. The signal conduction capability of the OS transistor is such that when the second and third MOS transistors are both turned on, the voltage pull-down rate of the first drive signal meets the preset value. By adding a third MOS transistor, under the same overdrive voltage, the signal conduction capability of the third MOS transistor is less than that of the second MOS transistor. When the third MOS transistor is turned on, the voltage pull-down rate of the second MOS transistor to the first drive signal FXT is slowed down, thereby realizing the pull-down rate of the first drive signal by the second control module. In addition, the third MOS transistor is used to avoid the voltage difference between the gate and drain of the second NMOS transistor being too large and damaging when the first NMOS transistor is turned on.

[0013] In addition, the first MOSFET is a PMOS and the second MOSFET is an NMOS.

[0014] In addition, the third MOSFET is an NMOS.

[0015] Additionally, the driving inverter includes a sub-driving PMOS transistor and a sub-driving NMOS transistor; the source of the sub-driving PMOS transistor is used to receive a first power supply voltage, the source of the sub-driving NMOS transistor is used to receive a second power supply voltage, the drains of the sub-driving PMOS transistor and the drains of the sub-driving NMOS transistor are connected to output a word line driving signal, and the gates of the sub-driving PMOS transistor and the gates of the sub-driving NMOS transistor are connected to receive a word line control signal; of the first power supply voltage and the second power supply voltage, one is a high-level voltage and the other is a low-level voltage.

[0016] Additionally, the control inverter includes a control PMOS transistor and a control NMOS transistor; the source of the control PMOS transistor is used to receive a third power supply voltage, the source of the control NMOS transistor is used to receive a fourth power supply voltage, the drains of the control PMOS transistor and the drains of the control NMOS transistor are connected to output a second drive signal, and the gates of the control PMOS transistor and the gates of the control NMOS transistor are connected to receive a second control signal; of the third power supply voltage and the fourth power supply voltage, one is a high-level voltage and the other is a low-level voltage.

[0017] In addition, the high-level voltage is the internal power supply voltage of the memory to which the word line drive circuit belongs, or the word line enable voltage, while the low-level voltage is 0 or the word line disable voltage.

[0018] In addition, both the low-level and high-level voltages are provided by external voltages.

[0019] This disclosure also provides a word line driving method applied to the above-mentioned word line driving circuit, including: in the driving phase, providing a word line control signal to synchronize data input from the second input terminal to the output terminal, and simultaneously providing a first control signal to enable the first control module to pull up the first driving signal; in the waiting phase, stopping the provision of the word line control signal, synchronizing data input from the third input terminal to the output terminal, and simultaneously providing a first control signal to enable the second control module to pull down the first driving signal, wherein the voltage pull-down rate of the second control module for the first driving signal satisfies a preset value.

[0020] During the driving phase, the first control module pulls up the first driving signal based on the first control signal. The word line driving signal controls the sub-word line driver to synchronize the data input from the second input terminal to the word line, that is, to transmit the pulled-up first driving signal to the word line to turn on the corresponding word line. During the transition from the driving phase to the waiting phase, the word line driving signal controls the sub-word line driver to synchronize the data input from the third input terminal to the word line, that is, to transmit the word line shutdown voltage to the word line to turn off the corresponding word line. The second control module pulls down the first driving signal based on the first control signal. At this time, the word line driving signal received by the first input terminal of the sub-word line driver is at a high level, and the first driving signal received by the second input terminal is at a low level. There is a voltage difference between the first input terminal and the second input terminal. By limiting the voltage pull-down rate of the first driving signal by the second control module, the first driving signal shows a slow decreasing trend during the waiting phase, thereby reducing the average voltage difference between the first input terminal and the second input terminal of the sub-word line driver during the waiting process, thereby reducing the leakage current of the sub-word line driving circuit and improving the reliability of the sub-word line driving circuit.

[0021] In addition, the word line driving method further includes: providing a second control signal during the driving phase to turn off the second driving MOSFET; and providing a second control signal during the waiting phase to turn on the second driving MOSFET while simultaneously pulling down the word line potential.

[0022] This disclosure also provides a memory in which the word line driving circuit described above is used for word line control. Attached Figure Description

[0023] Figure 1 A schematic diagram of the circuit structure of the word line driving circuit provided in the embodiments of this disclosure; Figure 2 A schematic diagram of the structure of the first control module and the second control module provided in the embodiments of this disclosure; Figure 3 Another schematic diagram of the structure of the first control module and the second control module provided in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the circuit structure for driving an inverter provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the circuit structure for controlling the inverter provided in an embodiment of the present disclosure; Figure 6 This is a timing diagram of each signal in the driving phase and the waiting phase, provided for another embodiment of this disclosure. Detailed Implementation

[0024] During the word line driving process of DRAM, the gate-source voltage difference of PMOS in the sub-word line driving circuit in the waiting state is relatively large, resulting in a serious PMOS leakage problem, which reduces the reliability of the sub-word line driving circuit. How to reduce the leakage current of the sub-word line driving circuit is a technical problem that urgently needs to be solved.

[0025] This disclosure provides a word line driving circuit that reduces leakage current in the sub-word line driving circuit when the sub-word line driving circuit is in a waiting state, thereby improving the reliability of the sub-word line driving circuit.

[0026] It will be understood by those skilled in the art that many technical details have been presented in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 This is a schematic diagram of the circuit structure of the word line driving circuit provided in this embodiment. Figure 2 This is a schematic diagram of the structure of the first control module and the second control module provided in this embodiment. Figure 3 This is another structural diagram of the first control module and the second control module provided in this embodiment. Figure 4 This is a schematic diagram of the circuit structure for driving the inverter provided in this embodiment. Figure 5This is a schematic diagram of the circuit structure for controlling the inverter provided in this embodiment. Figure 6 The following is a timing diagram of each signal in the driving phase and the waiting phase provided in this embodiment. The word line driving circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings: refer to Figure 1 The word line driving circuit includes: a driving inverter 101, at least one sub-word line driver 102, a first control module 113, a second control module 123, and a control inverter 104.

[0028] The inverter 101 is driven by receiving word line control signals MWL at its input and outputting word line drive signals MWLB at its output. The word line drive signals MWLB are used to drive at least one sub-word line driver 102. That is, each word line control signal MWL controls at least one sub-word line driver 102, thereby controlling multiple word lines WL.

[0029] For the sub-word line driver 102, the sub-word line driver 102 includes a first input terminal S1, a second input terminal S2, a third input terminal S3, and an output terminal S. The first input terminal S1 is used to receive the word line drive signal MWLB, the second input terminal S2 is used to receive the first drive signal FXT, and the third input terminal S3 is used to receive the word line shutdown voltage V. KK The output terminal S is used to connect the word line WL.

[0030] The sub-word driver 102 is configured to synchronize data input to the second input S2 or the third input S3 to the output S based on the data input to the first input S1.

[0031] The first control module 113, whose output terminal is connected to the source of the driving PMOS transistor 132, is configured to pull up the first driving signal FXT based on the first control signal K1.

[0032] The second control module 123, whose output terminal is connected to the source of the driving PMOS transistor 132, is configured to pull down the first driving signal FXT based on the first control signal K1, and the voltage pull-down rate of the first driving signal FXT satisfies a preset value. The first control module 113 and the second control module 123 are started based on different levels of the first control signal K1.

[0033] The first control module 113 and the second control module 123 are started based on different levels of the first control signal K1; for example, if the first control module 113 is started based on the high level of the first control signal K1, then the second control module 123 is started based on the low level of the first control signal K1; if the first control module 113 is started based on the low level of the first control signal K1, then the second control module 123 is started based on the high level of the first control signal K1.

[0034] During the driving phase, the first control module 113 pulls up the first driving signal FXT based on the first control signal K1, and the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input at the second input terminal S2 to the word line WL, that is, to transmit the pulled-up first driving signal FXT to the word line WL to turn on the corresponding word line WL; during the transition from the driving phase to the waiting phase, the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input at the third input terminal S3 to the word line WL, that is, to turn on the word line turn-off voltage V KK The signal is transmitted to the word line WL to close the corresponding word line WL. The second control module 123 pulls down the first drive signal FXT based on the first control signal K1. At this time, the word line drive signal MWLB received by the first input terminal S1 of the sub-word line driver 102 is at a high level, and the first drive signal FXT received by the second input terminal S2 is at a low level. There is a voltage difference between the first input terminal S1 and the second input terminal S2. By limiting the voltage pull-down rate of the first drive signal FXT by the second control module 123, the first drive signal FXT shows a slow decreasing trend during the waiting stage, thereby reducing the average voltage difference between the first input terminal S1 and the second input terminal S2 of the sub-word line driver 102 during the waiting process, thereby reducing the leakage current of the sub-word line drive circuit and improving the reliability of the sub-word line drive circuit.

[0035] In some embodiments, continue to refer to Figure 1 The sub-word line driver 102 includes a driving PMOS transistor 132 and a first driving NMOS transistor 112.

[0036] In this configuration, the gate of the first driving NMOS transistor 112 is connected to the gate of the driving PMOS transistor, serving as the first input terminal S1. The source of the driving PMOS transistor 132 serves as the second input terminal S2, the source of the first driving NMOS transistor serves as the third input terminal S3, and the drain of the driving PMOS transistor 132 and the drain of the first driving NMOS transistor 112 serve as the output terminal S.

[0037] The word line drive signal MWLB simultaneously controls the drive PMOS transistor 132 and the first drive NMOS transistor 112. When the word line drive signal MWLB is high, the first drive NMOS transistor 112 is turned on, and the word line turn-off voltage V... KK The signal is transmitted to word line WL, thereby turning off word line WL; when word line drive signal MWLB is low, drive PMOS transistor 132 is turned on, and the first drive signal FXT is transmitted to word line WL, thereby turning on word line WL.

[0038] It should be noted that in other embodiments, the driving PMOS transistor can also be an NMOS transistor, while the first NMOS transistor and the second NMOS transistor are PMOS transistors, that is, the high-level word line driving signal MWLB is used as the enable signal for the bit line WL, and the low-level word line driving signal MWLB is used as the enable signal for the bit line WL.

[0039] In some embodiments, continue to refer to Figure 1 The word line driving circuit also includes: a control inverter 104 and a second driving NMOS transistor 122.

[0040] The input terminal of the control inverter 104 is used to receive the second control signal K2, and the output terminal S is used to output the second drive signal FXB. The source of the second drive NMOS transistor 122 is connected to the source of the first drive NMOS transistor 112. The gate of the second drive NMOS transistor is used to receive the second drive signal FXB, and the drain of the second drive NMOS transistor is used to connect to the word line WL.

[0041] Turn off word line voltage V KK During transmission to word line WL, the word line may be too long, causing the word line shutdown voltage V to be interrupted. KK The efficiency of transmitting to the entire word line WL is too low. Therefore, when the first NMOS transistor 112 is turned on, the second NMOS transistor 122 is turned on through the second drive signal FXB, simultaneously providing the word line turn-off voltage V to the word line WL at another point on the word line WL. KK This is to ensure that the word line WL is closed and to speed up the closing efficiency of the word line WL.

[0042] In some embodiments, the preset value of the voltage pull-down rate of the first drive signal is: the voltage pull-down rate is less than 5V / ns. Specifically, the second control module 123 can pull down the first drive signal FXT at a rate of 5V / 10ns, 5V / 50ns, 5V / 100ns, 5V / 500ns, 3V / 10ns, 3V / 50ns, 3V / 100ns, or 3V / 500ns based on the first control signal K1. Since the turn-on voltage of word line WL is typically 2V~5V, that is, when the first drive signal FXT is used to drive word line WL, its potential is 2V~5V. In order to reduce the gate-source voltage difference of driving PMOS transistor 132, this application reduces the pull-down rate of the second control module 123 on the first drive signal FXT, thereby increasing the source potential of driving PMOS transistor 132, which reduces the gate-source voltage difference of driving PMOS transistor 132. In addition, by reducing the pull-down rate of the second control module 123 on the first drive signal FXT to the nanosecond level, the gate-source voltage difference of driving PMOS transistor 132 is effectively reduced without affecting the normal operation of the memory.

[0043] In some embodiments, reference Figure 2 The first control module 113 includes a first MOSFET, and the second control module 123 includes a second MOSFET. The drains of the first and second MOSFETs are connected together and connected to the second input terminal S2. The gates of the first and second MOSFETs are connected together and used to receive a first control signal K1. The source of the first MOSFET is used to receive the word line turn-on voltage V. PP The source of the second MOSFET is grounded to GND. When the second MOSFET is turned on, the voltage pull-down rate of the first drive signal FXT meets the preset value.

[0044] The second control module 123 controls the pull-down rate of the first drive signal FXT when the second MOSFET is turned on. In some embodiments, the pull-down rate of the second MOSFET is limited by reasonably setting the aspect ratio of the active region. In some embodiments, the pull-down rate of the second MOSFET is limited by increasing the thickness of the gate oxide layer to increase the threshold voltage of the second MOSFET.

[0045] In some embodiments, reference Figure 3 The first control module 113 includes a first MOSFET, and the second control module 123 includes a second MOSFET and a third MOSFET. The drains of the first MOSFET and the third MOSFET are connected together and connected to the second input terminal S2. The source of the third MOSFET is connected to the drain of the second MOSFET. The gates of the first MOSFET and the second MOSFET are connected together and used to receive the first control signal FXT. The source of the first MOSFET is used to receive the word line turn-on voltage V. PP The source of the second MOSFET is grounded to GND, and the gate of the third MOSFET is used to receive the floating control signal K3. Under the same overdrive voltage, the signal conduction capability of the third MOSFET is less than that of the second MOSFET. When the second and third MOSFETs are both turned on, the voltage pull-down rate of the first drive signal FXT meets the preset value.

[0046] By adding a third MOSFET, under the same overdrive voltage, the signal conduction capability of the third MOSFET is less than that of the second MOSFET. When the third MOSFET is turned on, the voltage pull-down rate of the second MOSFET to the first drive signal FXT is slowed down, thereby realizing the pull-down rate of the second control module 123 to the first drive signal FXT. In addition, the third MOSFET is used to prevent the voltage difference between the gate and source of the second NMOS transistor from being too large and causing damage when the first NMOS transistor is turned on.

[0047] In some embodiments, by reasonably setting the active region width-to-length ratio of the third MOS transistor, the pull-down rate of the third MOS transistor is limited, thereby limiting the pull-down rate of the third MOS transistor and the second MOS transistor connected in series. In some embodiments, by increasing the thickness of the gate oxide layer, the threshold voltage of the second MOS transistor is increased, thereby limiting the pull-down rate of the second MOS transistor, thereby limiting the pull-down rate of the third MOS transistor and the second MOS transistor connected in series.

[0048] for Figure 2 and Figure 3 In some examples of the circuits of the first control module 113 and the second control module 123 shown, the signal conduction capability of the first MOS transistor is the same as that of the second MOS transistor. Since PMOS transistors have a stronger voltage pull-up capability and NMOS transistors have a stronger voltage pull-down capability, in this embodiment, the first MOS transistor is a PMOS and the second MOS transistor is an NMOS transistor, thereby enhancing the pull-up / pull-down rate of the first control module 113 and the second control module 123 during the driving phase. In other embodiments, the first MOS transistor can also be an NMOS transistor and the second MOS transistor can also be a PMOS transistor.

[0049] Furthermore, for Figure 3 In the circuit shown, when the third MOSFET and the second MOSFET are of the same type, it facilitates the control of the pull-up / pull-down rate of the second control module 123. Furthermore, when the MOSFETs are of the same type, their layout can be located in the same active region, reducing the layout area of ​​the second control module 123. In this embodiment, the third MOSFET is an NMOS; in other embodiments, the third MOSFET can also be a PMOS. Additionally, in some embodiments, the type of the third MOSFET can be different from the type of the second MOSFET, i.e., one of the second and third MOSFETs is an NMOS, and the other is a PMOS.

[0050] In some embodiments, reference Figure 4 The driving inverter 101 includes a sub-driving PMOS transistor 111 and a sub-driving NMOS transistor 121. The gates of the sub-driving PMOS transistor 111 and the NMOS transistor 121 are connected to receive a word line control signal MWL. The drains of the sub-driving PMOS transistor 111 and the NMOS transistor 121 are connected to output a word line driving signal MWLB. The source of the sub-driving PMOS transistor 111 receives a first power supply voltage, and the source of the sub-driving NMOS transistor receives a second power supply voltage. One of the first and second power supply voltages is a high-level voltage, and the other is a low-level voltage.

[0051] In some embodiments, reference Figure 5The inverter 104 includes a control PMOS transistor 114 and a control NMOS transistor 124. The source of the control PMOS transistor 114 receives a third power supply voltage, and the source of the control NMOS transistor 124 receives a fourth power supply voltage. The drains of the control PMOS transistor 114 and the control NMOS transistor 124 are connected to output a second drive signal. The gates of the control PMOS transistor 114 and the control NMOS transistor 124 are connected to receive a second control signal K2. Of the third and fourth power supply voltages, one is a high-level voltage and the other is a low-level voltage.

[0052] for Figure 4 and Figure 5 In some embodiments of the circuit, the sub-driving PMOS transistor 111 can also be an NMOS transistor, and correspondingly, the sub-driving NMOS transistor 121 can also be a PMOS transistor; in some embodiments, the control PMOS transistor 114 can also be an NMOS transistor, and correspondingly, the control NMOS transistor 124 can also be a PMOS transistor.

[0053] In one example, the high-level voltage is the internal power supply voltage V of the memory described by the word line driver circuit 101. DD Or word line turn-on voltage V PP Low-level voltage is 0 or word line off voltage V KK .

[0054] It should be noted that since the high level in the control inverter 104 is only used to control the on / off state of the second driving NMOS transistor 122, it does not affect the potential of the word line WL, which is the internal power supply voltage V of the memory described by the word line driving circuit 101. DD Using the high-level voltage in the control inverter 104 can reduce the overall power consumption of the word line drive circuit.

[0055] In one example, the low-level voltage and the high-level voltage are provided by an external voltage.

[0056] During the driving phase, the first control module 113 pulls up the first driving signal FXT based on the first control signal K1, and the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input at the second input terminal S2 to the word line WL, that is, to transmit the pulled-up first driving signal FXT to the word line WL to turn on the corresponding word line WL; during the transition from the driving phase to the waiting phase, the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input at the third input terminal S3 to the word line WL, that is, to turn on the word line turn-off voltage V KKThe signal is transmitted to the word line WL to close the corresponding word line WL. The second control module 123 pulls down the first drive signal FXT based on the first control signal K1. At this time, the word line drive signal MWLB received by the first input terminal S1 of the sub-word line driver 102 is at a high level, and the first drive signal FXT received by the second input terminal S2 is at a low level. There is a voltage difference between the first input terminal S1 and the second input terminal S2. By limiting the voltage pull-down rate of the first drive signal FXT by the second control module 123, the first drive signal FXT shows a slow decreasing trend during the waiting stage, thereby reducing the average voltage difference between the first input terminal S1 and the second input terminal S2 of the sub-word line driver 102 during the waiting process, thereby reducing the leakage current of the sub-word line drive circuit and improving the reliability of the sub-word line drive circuit.

[0057] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0058] It should be noted that the features disclosed in the word line driving circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new refresh circuit embodiments.

[0059] Another embodiment of this disclosure provides a word line driving method applied to the above-described word line driving circuit to improve the reliability of the PMOS in the sub-word line driving circuit.

[0060] Figure 6 The following is a timing diagram of each signal in the driving phase and the waiting phase provided in this embodiment. The word line driving method provided in this embodiment will be further described in detail below with reference to the accompanying drawings: refer to Figure 6 and combined Figures 1-5 Word line driving methods include: During the driving phase, a word line control signal MWL is provided to synchronize the data input at the second input terminal S2 to the output terminal S. At the same time, a first control signal K1 is provided to enable the first control module 113 to pull up the first driving signal FXT.

[0061] During the waiting phase, the word line control signal MWL is stopped, the data input at the third input terminal S3 is synchronized to the output terminal S, and the first control signal K1 is provided to enable the second control module 123 to pull down the first drive signal FXT. The voltage pull-down rate of the second control module 123 on the first drive signal FXT meets the preset value.

[0062] During the driving phase, the first control module 113 pulls up the first driving signal FXT based on the first control signal K1, and the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input from the second input terminal S2 to the word line WL, that is, to transmit the pulled-up first driving signal FXT to the word line WL to turn on the corresponding word line WL; during the transition from the driving phase to the waiting phase, the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input from the third input terminal S3 to the word line WL, that is, to transmit the word line shutdown voltage VKK to the word line WL to turn off the corresponding word line WL, and the second control module 123 pulls down the first driving signal K1 based on the first control signal K1. When the word line driver 102 receives the word line driving signal FXT at its first input terminal S1, the word line driving signal MWLB is at a high level, and the first driving signal FXT received at its second input terminal S2 is at a low level. There is a voltage difference between the first input terminal S1 and the second input terminal S2. By limiting the voltage pull-down rate of the first driving signal FXT through the second control module 123, the first driving signal FXT exhibits a slow decreasing trend during the waiting phase, thereby reducing the average voltage difference between the first input terminal S1 and the second input terminal S2 during the waiting process of the word line driver 102, thereby reducing the leakage current of the word line driving circuit and improving the reliability of the word line driving circuit.

[0063] In some embodiments, the preset value of the voltage pull-down rate of the first drive signal is: the voltage pull-down rate is less than 5V / ns. Specifically, the second control module 123 can pull down the first drive signal FXT at a rate of 5V / 10ns, 5V / 50ns, 5V / 100ns, 5V / 500ns, 3V / 10ns, 3V / 50ns, 3V / 100ns, or 3V / 500ns based on the first control signal K1. Since the turn-on voltage of word line WL is typically 2V~5V, that is, when the first drive signal FXT is used to drive word line WL, its potential is 2V~5V. In order to reduce the gate-source voltage difference of driving PMOS transistor 132, this application reduces the pull-down rate of the second control module 123 on the first drive signal FXT, thereby increasing the source potential of driving PMOS transistor 132, which reduces the gate-source voltage difference of driving PMOS transistor 132. In addition, by reducing the pull-down rate of the second control module 123 on the first drive signal FXT to the nanosecond level, the gate-source voltage difference of driving PMOS transistor 132 is effectively reduced without affecting the normal operation of the memory.

[0064] In some embodiments, the word line driving method further includes: During the driving phase, a second control signal K2 is provided to turn off the second driving MOSFET; during the waiting phase, a second control signal K2 is provided to turn on the second driving MOSFET and simultaneously pull down the potential of the word line WL.

[0065] Turn off word line voltage V KK During transmission to word line WL, the word line may be too long, causing the word line shutdown voltage V to be interrupted. KK The efficiency of transmitting to the entire word line WL is too low. Therefore, when the first NMOS transistor 112 is turned on, the second NMOS transistor 122 is turned on through the second drive signal FXB, simultaneously providing the word line turn-off voltage V to the word line WL at another point on the word line WL. KK This is to ensure that the word line WL is closed and to speed up the closing efficiency of the word line WL.

[0066] Another embodiment of this disclosure provides a memory in which the above-described word line driving circuit is used to control the word lines in the memory. When the sub-word line driving circuit is in a waiting state, the gate-source voltage difference of the PMOS in the sub-word line driving circuit is reduced, thereby reducing the leakage current of the PMOS gate-source and improving the reliability of the PMOS in the sub-word line driving circuit.

[0067] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR2 memory specification.

[0068] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR3 memory specification.

[0069] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR4 memory specification.

[0070] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR5 memory specification.

[0071] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A word line driving circuit, characterized in that, include: A driver inverter is used to receive word line control signals at its input terminal and to output word line drive signals at its output terminal. The word line drive signals are used to drive at least one sub-word line driver. The sub-word line driver includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive the word line driving signal, the second input terminal is used to receive the first driving signal, the third input terminal is used to receive the word line shutdown voltage, and the output terminal is used to connect to the word line. The sub-word line driver is configured to synchronize data input from the second input terminal or the third input terminal to the output terminal based on the data input from the first input terminal; The first control module, whose output is connected to the second input, is configured to pull up the first drive signal based on the first control signal during the drive phase. The second control module, with its output terminal connected to the second input terminal, is configured to, during the transition from the driving phase to the waiting phase, pull down the first driving signal based on the first control signal, and the voltage pull-down rate of the first driving signal is less than 5V / ns, so that the first driving signal exhibits a slow decreasing trend during the waiting phase. The first control module and the second control module are activated based on different levels of the first control signal.

2. The word line driving circuit according to claim 1, characterized in that, The sub-word line driver includes: a driving PMOS transistor and a first driving NMOS transistor; The gate of the first driving NMOS transistor is connected to the gate of the driving PMOS transistor, serving as the first input terminal; The source of the driving PMOS transistor serves as the second input terminal; The source of the first driving NMOS transistor serves as the third input terminal; The drain of the driving PMOS transistor and the drain of the first driving NMOS transistor serve as the output terminal.

3. The word line driving circuit according to claim 2, characterized in that, It also includes: a control inverter and a second driving NMOS transistor; The input terminal of the control inverter is used to receive the second control signal, and the output terminal is used to output the second drive signal. The source of the second driving NMOS transistor is connected to the source of the first driving NMOS transistor; The gate of the second driving NMOS transistor is used to receive the second driving signal; The drain of the second driving NMOS transistor is used to connect to the word line.

4. The word line driving circuit according to claim 1, characterized in that, The first control module includes a first MOSFET, and the second control module includes a second MOSFET. The drain of the first MOSFET is connected to the drain of the second MOSFET and is connected to the second input terminal. The gate of the first MOSFET is connected to the gate of the second MOSFET and is used to receive the first control signal. The source of the first MOSFET is used to receive the word line turn-on voltage, and the source of the second MOSFET is grounded. When the second MOSFET is turned on, the voltage pull-down rate of the first drive signal is less than 5V / ns.

5. The word line driving circuit according to claim 1, characterized in that, The first control module includes a first MOSFET, and the second control module includes a second MOSFET and a third MOSFET. The drain of the first MOS transistor is connected to the drain of the third MOS transistor and connected to the second input terminal. The source of the third MOS transistor is connected to the drain of the second MOS transistor. The gate of the first MOS transistor is connected to the gate of the second MOS transistor and is used to receive the first control signal. The source of the first MOS transistor is used to receive the word line turn-on voltage. The source of the second MOS transistor is grounded. The gate of the third MOS transistor is used to receive the floating control signal. Under the same overdrive voltage, the signal conduction capability of the third MOSFET is less than that of the second MOSFET, and when the second MOSFET and the third MOSFET are both turned on, the voltage pull-down rate of the first drive signal is less than 5V / ns.

6. The word line driving circuit according to claim 4 or 5, characterized in that, The first MOSFET is a PMOS, and the second MOSFET is an NMOS.

7. The word line driving circuit according to claim 5, characterized in that, The third MOS transistor is an NMOS.

8. The word line driving circuit according to claim 1, characterized in that, The driving inverter includes: a sub-driving PMOS transistor and a sub-driving NMOS transistor; The source of the sub-driving PMOS transistor is used to receive a first power supply voltage, the source of the sub-driving NMOS transistor is used to receive a second power supply voltage, the drain of the sub-driving PMOS transistor and the drain of the sub-driving NMOS transistor are connected to output the word line driving signal, and the gate of the sub-driving PMOS transistor and the gate of the sub-driving NMOS transistor are connected to receive the word line control signal. Of the first power supply voltage and the second power supply voltage, one is a high-level voltage and the other is a low-level voltage.

9. The word line driving circuit according to claim 3, characterized in that, The control inverter includes: a control PMOS transistor and a control NMOS transistor; The source of the control PMOS transistor is used to receive a third power supply voltage, the source of the control NMOS transistor is used to receive a fourth power supply voltage, the drain of the control PMOS transistor and the drain of the control NMOS transistor are connected to output the second drive signal, and the gate of the control PMOS transistor and the gate of the control NMOS transistor are connected to receive the second control signal. Of the third power supply voltage and the fourth power supply voltage, one is a high-level voltage and the other is a low-level voltage.

10. The word line driving circuit according to claim 8 or 9, characterized in that, The high-level voltage is the internal power supply voltage of the memory to which the word line driving circuit belongs or the word line enable voltage, and the low-level voltage is 0 or the word line disable voltage.

11. The word line driving circuit according to claim 8 or 9, characterized in that, The low-level voltage and the high-level voltage are provided by an external voltage.

12. A word line driving method, characterized in that, Applied to any one of the word line driving circuits of claims 1 to 11, comprising: During the driving phase, a word line control signal is provided to synchronize the data input from the second input terminal to the output terminal. At the same time, a first control signal is provided to enable the first control module to pull up the first driving signal, and a second control signal is provided to turn off the second driving MOS transistor. During the transition from the driving phase to the waiting phase, the word line control signal is stopped, the data input from the third input terminal is synchronized to the output terminal, and the first control signal is provided to enable the second control module to pull down the first driving signal. The voltage pull-down rate of the second control module for the first driving signal is less than 5V / ns.

13. The word line driving method according to claim 12, characterized in that, Also includes: During the driving phase, a second control signal is provided to turn off the second driving MOSFET; During the waiting phase, a second control signal is provided to turn on the second driving MOS transistor and simultaneously pull down the word line potential.

14. A memory, characterized in that, The word line driving circuit of any one of claims 1 to 11 is used to control the word lines in the memory.

Images