Memory device, operating method thereof, and memory system

Abstract

A memory device, an operating method thereof, and a memory system are disclosed. In one aspect, a memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is to transfer charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit to discharge stored charge in the first programmable bit line.

Description

Technical Field

[0001] One embodiment of this disclosure relates to a memory device, and more particularly to a memory device comprising a bit line, a first programmable bit line, a charge-sharing circuit, and a discharge circuit. Background Technology

[0002] Static random access memory (SRAM) devices are volatile semiconductor memories that store data bits using a bistable circuit system that does not require updating. SRAM devices typically include one or more memory arrays, each containing multiple SRAM cells. An SRAM cell is often called a bit cell because it stores one bit of information, represented by the logic state of two cross-coupled inverters. Each memory array includes multiple bit cells configured in rows and columns. Each bit cell in a memory array typically includes connections to a power supply voltage and a reference voltage. Logic signals on the bit lines control reading from and writing to the bit cells, while word lines control the connection between the bit lines and the inverters; otherwise, the inverters would float. Word lines can be coupled along a row of the memory array to multiple bit cells, providing different word lines for different rows. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory device including bit lines, a first programmable bit line, a charge-sharing circuit, and a discharge circuit. The bit lines are connected to a plurality of memory cells in a memory array, and each bit line has a first length. The first programmable bit line has a second length, determined based on the size of the memory array. The charge-sharing circuit is connected to the bit lines and the first programmable bit line, and is used to transfer charge from the bit lines to the first programmable bit line. The discharge circuit is connected to the first programmable bit line, and is used to discharge the stored charge in the first programmable bit line.

[0004] Another embodiment of this disclosure provides a memory system including a memory array, a controller, and a programmable charge-sharing circuit. The memory array includes bit lines having a first length. The controller provides control signals to the memory array. The programmable charge-sharing circuit is connected to the controller and the bit lines. The programmable charge-sharing circuit includes a first programmable bit line having a second length determined based on the size of the memory array, a charge-sharing circuit connected to the bit lines and the first programmable bit line, and a discharge circuit connected to the first programmable bit line. The charge-sharing circuit transfers charge from the bit lines to the first programmable bit line. The discharge circuit discharges stored charge in the first programmable bit line.

[0005] Another embodiment of this disclosure provides a method for operating a memory device, the method comprising the steps of: during a read operation of a memory cell, providing a first voltage to a control signal line connected to a discharge circuit and a charge-sharing circuit; discharging a programmable bit line using the discharge circuit based on the first voltage on the control signal line; providing a second voltage different from the first voltage to the control signal line; and connecting the bit line to the programmable bit line based on the second voltage on the control signal line. Attached Figure Description

[0006] The features disclosed herein are best understood when read in conjunction with the accompanying drawings from the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A The figure shows a schematic block diagram of a memory device according to some embodiments;

[0008] Figure 1B The illustration shows an example circuit diagram of a memory cell according to some embodiments;

[0009] Figure 2A The diagram illustrates an example of a programmable charge-sharing circuit according to some embodiments;

[0010] Figure 2B The illustrations depict the use of reading operations during some embodiments. Figure 2A Example waveforms illustrating the effect of a programmable charge-sharing circuit;

[0011] Figure 3 The diagram illustrates an example charge-sharing tile matrix based on some embodiments of the charge-sharing ratio;

[0012] Figure 4A The figure shows an example block diagram of a memory device according to some embodiments;

[0013] Figure 4B The illustrations are based on some embodiments. Figure 4A Timing diagram of instance operations of the memory device;

[0014] Figure 5 The diagram illustrates an example of a programmable charge-sharing circuit according to some embodiments;

[0015] Figure 6 The diagram illustrates an example of a programmable charge-sharing circuit according to some embodiments;

[0016] Figure 7 The diagram illustrates an example of a programmable charge-sharing circuit according to some embodiments;

[0017] Figure 8The illustration shows a flowchart of an example method for operating a memory device according to some embodiments.

[0018] [Symbol Explanation]

[0019] 100: Memory Device

[0020] 101: First reference voltage

[0021] 102: Controller

[0022] 103: Memory Unit

[0023] 104: Memory Array

[0024] 105:WL

[0025] 107:BL

[0026] 109:BLB

[0027] 110: Node

[0028] 112: Character line driver

[0029] 114: Clock Generator

[0030] 116: Bit line driver

[0031] 118:SA

[0032] 122-126: Nodes

[0033] 128: Second reference voltage

[0034] 200: Programmable CS circuit

[0035] 202: Parasitic Capacitor

[0036] 204:PBLC

[0037] 206: CS transistor

[0038] 208: Discharge transistor

[0039] 210: Control signal line

[0040] 250: Graphics

[0041] 252~258: Waveform

[0042] 260: Graphics

[0043] 300:CS tile matrix

[0044] 310~340: Tiles

[0045] 400: Memory Device

[0046] 402: Memory Array

[0047] 404: Memory Array

[0048] 410: Main Controller

[0049] 412:WL Driver

[0050] 422a~422d: CS transistor

[0051] 432a~432d: Discharge transistors

[0052] 440: Tracking Array

[0053] 450: Timing Diagram

[0054] 452:I / O circuit

[0055] 454:I / O circuit

[0056] 500: Programmable CS circuit

[0057] 502: Parasitic Capacitor

[0058] 504:PBLC

[0059] 506: CS transistor

[0060] 508: Discharge transistor

[0061] 510: Control signal

[0062] 512: Delay Chain

[0063] 512a~512b: Inverters

[0064] 600: Programmable CS circuit

[0065] 602: Parasitic Capacitor

[0066] 604:PBLC

[0067] 606a: NMOS transistor

[0068] 606b: PMOS transistor

[0069] 608: Discharge transistor

[0070] 610a~610b: Complementary control signals

[0071] 700: Programmable CS circuit

[0072] 702: Parasitic Capacitor

[0073] 704:PBLC

[0074] 706a: NMOS transistor

[0075] 706b: PMOS transistor

[0076] 708: Discharge transistor

[0077] 710: Control Signal

[0078] 712: Delay Chain

[0079] 712a~712b: Inverters

[0080] 800: Method

[0081] 802~808: Operation Detailed Implementation

[0082] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0083] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0084] With advancements in integrated circuit (IC) technology, IC characteristics (e.g., transistor gate length) are continuously decreasing, allowing for the implementation of more circuitry within ICs. A challenge of this continuous progress is the inconsistency in memory cell manufacturing at the silicon process variation, operating voltage, and temperature (PVT) angles, which can affect memory chip quality and yield. A standard static random access memory (SRAM) cell includes two cross-coupled inverters connected to a bit line (BL) and a bit line bar (BLB) via two access transistors. The memory cell (e.g., the access memory cell) is activated by turning on the access transistors via a word line (WL) signal. However, if the pull-down n-type metal-oxide-semiconductor (NMOS) or pull-up p-type metal-oxide-semiconductor (PMOS) is unbalanced (e.g., improper granularity or unbalanced resistance), the stored data in the memory cell can be disturbed during a read operation. This phenomenon is called a read static noise margin (RSNM) violation. When this occurs, current can flow from the BL / BLB through the pull-down transistor to ground, which can interfere with the voltage level on the BL / BLB and cause the data in the memory cell to flip unintentionally, thereby damaging the memory cell.

[0085] Typical approaches to this problem include several methods. The first method is to change the metal scheme of the WL from bimetallic to monometallic, which degrades the WL's slew rate at high voltages, thus reducing the strength of the access transistor. However, this can lead to signal integrity issues at high voltages. The second method involves reducing the size of the WL driver, which also degrades the WL's slew rate and thus the strength of the access transistor. However, this allows for further fine-tuning of read / write tolerances and the addition of clipped columns to support a wider voltage range. The third method involves suppressing the WL voltage, which reduces the WL voltage and thus the strength of the access transistor. However, similar to the second method, this allows for further fine-tuning of read / write tolerances and the addition of clipped columns to support a wider voltage range. The fourth method involves a head socket for the WL driver, which degrades the WL's slew rate. However, voltage drops in the word lines can cause timing and power delivery problems. Therefore, it is desirable to reliably maintain a high RSNM.

[0086] In this disclosure, a programmable charge-sharing (CS) capacitor can be formed to provide more advantages than the prior art. For example, a charge-sharing circuit can be used to connect bit lines and bit bars to programmable bit lines and programmable bit bars. The programmable bit lines and programmable bit bars can receive charge from the corresponding bit lines or bit bars to reduce the voltage on the bit lines and / or bit bars. This can significantly reduce the sudden inflow of current to the pull-down transistor when the access transistor starts up. The programmable lines can be formed as metal structures parallel to the corresponding bit lines / bit bars, and the programmable lines can also have different lengths. Depending on how much charge sharing is required for the bit lines and / or bit bars, the length of the corresponding programmable bit lines or bit bars can sufficiently facilitate charge sharing, so that the corresponding bit lines and / or bit bars can have a voltage lower than the supply voltage VDD. This can advantageously result in a reduced voltage bounce at the drain of the pull-down resistor, thereby increasing RSNM and reducing the probability of unintentional bit flips in the memory cell.

[0087] Figure 1A The figure shows a schematic block diagram of a memory device 100 according to some embodiments. A memory device is a type of IC device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuitry for other functionalities besides the memory device.

[0088] The memory device 100 includes at least one memory cell 103 and a controller (also referred to as "control circuitry") 102, coupled to control the operation of the memory cell 103. Figure 1A In the instance configuration, memory device 100 includes multiple memory cells 103 arranged in multiple columns and rows in memory array 104. Memory device 100 further includes multiple word lines WL[0] to WL[m] extending along the rows and multiple bit lines (also referred to as "data lines") BL[0] to BL[k] extending along the columns of memory cells 103. Although Figure 1ANot shown, but complementary bit lines BLB[0] to BLB[k] may exist, substantially extending parallel to the plurality of bit lines BL[0] to BL[k]. Each of the memory cells 103 is coupled to the controller 102 via at least one of the word lines and / or bit lines and / or bit lines. Examples of word lines include, but are not limited to, read word lines for transmitting the address of the memory cell 103 to be read, write word lines for transmitting the address of the memory cell 103 to be written, or the like. In at least one embodiment, a set of word lines is used to perform both read word lines and write word lines. Examples of bit lines include read bit lines for transmitting data read from the memory cell 103 indicated by the corresponding word line, write bit lines for transmitting data to be written to the memory cell 103 indicated by the corresponding word line, or the like. In at least one embodiment, a set of bit lines is used to perform both read bit lines and write bit lines. In one or more embodiments, each memory cell 103 is coupled to a pair of bit lines, referred to herein as a word line and a bit line bar. A word line is generally referred to herein as a WL, while a bit line is generally referred to herein as a BL. Various numbers of word lines and / or bit lines in the memory device 100 are within the scope of various embodiments.

[0089] exist Figure 1A In the example configuration, controller 102 includes word line driver 112, clock generator 114, bit line driver 116, and sense amplifier (SA) 118 for performing at least one of a read operation or a write operation. In at least one embodiment, controller 102 further includes one or more clock generators for providing clock signals to various components of memory device 100; one or more input / output (I / O) circuits for exchanging data with external devices; and / or one or more controllers for controlling various operations in memory device 100. In at least one embodiment, clock generator 114 is omitted. In some embodiments, the inputs of SA 118 may include a multiplexer (mux) that can receive multiple inputs, for example, multiple bit lines (and bit line bars). The controller can provide control signals to the mux so that the mux can provide signals to SA 118 on sensed bit lines, and SA 118 can provide output signals to I / O circuitry including I / O pads. Furthermore, a memory device may have multiple SA 118s. For example, in a memory device with 1064 columns, there may be 256 SA 118s, each SA 118 having 4 bit lines connected to a mux that provides the selected bit line signal to the SA 118.

[0090] Word line driver 112 is coupled to memory array 104 via word line WL. Word line driver 112 is used to decode the row address of selected memory cell 103 for access in read or write operations. Word line driver 112 is used to supply voltage to the selected word line WL corresponding to the decoded row address and to supply different voltages to other, unselected word lines WL. In some embodiments, word line driver 112 may include multiple word line drivers connected to a group of word lines and providing a word line signal to these word lines. For example, the number of rows in the memory device may correspond to the number of word line drivers divided by the number of multiplexers.

[0091] Bit line driver 116 (also referred to as a "write driver") is coupled to memory array 104 via bit line BL. Bit line driver 116 decodes the column address of selected memory cell 103 for access during read or write operations. Bit line driver 116 supplies voltage to the selected bit line BL corresponding to the decoded row address and supplies different voltages to other unselected bit lines BL. During a write operation, bit line driver 116 supplies a write voltage (also referred to as a "programmed voltage") to the selected bit line BL. During a read operation, bit line driver 116 supplies a read voltage to the selected bit line BL.

[0092] SA 11 is coupled to memory array 104 via bit line BL. During a read operation, SA 118 is used to sense data read from the accessed memory cell 103 and retrieved via the corresponding bit line BL. The described memory device configuration is an example; other memory device configurations are within the scope of various embodiments. In at least one embodiment, memory device 100 is volatile memory, and memory cell 103 is an SRAM memory cell. Other types of memory are within the scope of various embodiments. Instance memory types of memory device 100 include, but are not limited to, SRAM, dynamic random access memory (DRAM), or similar.

[0093] The transistors in this disclosure are shown to have a specific type (n-type or p-type), but the embodiments are not limited thereto. A transistor can be any suitable type of transistor, including but not limited to metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), fin field-effect transistors (FinFETs), planar MOS transistors with raised source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0094] In some embodiments, the controller 102 includes a word line driver 112, a clock generator 114, a bit line driver 116, and a sense amplifier 118, as well as a plurality of other circuits, such as one or more multiplexers, one or more gate-gate transistors (or pass transistors), and / or one or more level shifters, wherein each of these other circuits may include p-type or n-type transistors. The multiplexer, gate-gate transistor, sense amplifier 118, and level shifter may typically be disposed on opposite sides of the word line driver 112, clock generator 114, and / or bit line driver 116. The controller 102 may be disposed on a substrate and connected to the memory array 104 via one or more bit lines BL and / or one or more word lines WL disposed in one or more metallization layers and / or one or more via structures.

[0095] In some embodiments, rows may be defined as the number of character line drivers divided by the number of inputs to the sense amplifier 118, and columns may be defined as the number of I / O pads multiplied by the number of mux inputs. However, embodiments are not limited thereto.

[0096] Figure 1BThe illustration shows an example circuit diagram of a memory cell 103 according to some embodiments. The memory cell 103 includes six transistors forming a six-transistor (6T) SRAM memory cell. In some embodiments, the memory cell 103 may be implemented as any of a variety of other SRAM cells, such as, for example, a two-transistor-two-resistor (2T-2R) SRAM cell, a four-transistor (4T) SRAM cell, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, etc. Although the discussion in this disclosure is directed to SRAM cells, it should be understood that other embodiments of this disclosure may also be used in any other memory cell, such as, for example, a dynamic random access memory (DRAM) cell.

[0097] like Figure 1B As shown, memory cell 103 includes six transistors: transistors M1, M2, M3, M4, M5, and M6. Transistors M1 and M2 form a first inverter, while transistors M3 and M4 form a second inverter, wherein the first and second inverters are cross-coupled to each other. Specifically, each of the first and second inverters is coupled between a first reference voltage 101 and a second reference voltage 128. In some embodiments, the first reference voltage 101 is a voltage level of the supply voltage applied to memory cell 100, which is generally referred to as "VDD". The second reference voltage 128 is generally referred to as "ground". The first inverter (formed by transistors M1 and M2) is coupled to transistor M5, while the second inverter (formed by transistors M3 and M4) is coupled to transistor M6. In addition to being coupled to the first inverter and the second inverter, transistors M5 and M6 are each coupled to word line (WL) 105, and to bit line (BL) 107 and bit line bar (BLB) 109, respectively.

[0098] In some embodiments, transistors M1 and M3 are referred to as pull-up transistors of memory cell 103 (hereinafter referred to as "pull-up transistor M1" and "pull-up transistor M3", respectively); transistors M2 and M4 are referred to as pull-down transistors of memory cell 103 (hereinafter referred to as "pull-down transistor M2" and "pull-down transistor M4", respectively); and transistors M5 and M6 are referred to as access transistors of memory cell 103 (hereinafter referred to as "access transistor M5" and "access transistor M6", respectively). In some embodiments, transistors M2, M4, M5, and M6 each include an n-type metal-oxide-semiconductor (NMOS) transistor, while transistors M1 and M3 each include a p-type metal-oxide-semiconductor (PMOS) transistor. Although illustrated Figure 1B The embodiments show that transistors M1 to M6 are NMOS or PMOS transistors, but any of a variety of transistors or devices suitable for use in memory devices can be implemented as at least one of transistors M1 to M6, such as, for example, bipolar junction transistors (BJTs), high-electron-mobility transistors (HEMTs), etc.

[0099] Access transistors M5 and M6 each have a gate coupled to WL 105. The gates of transistors M5 and M6 are used to receive pulse signals via WL 105 to accordingly enable or block access to memory cell 103, which will be discussed in more detail below. Transistors M2 and M5 are coupled to each other at node 110 by the drain of transistor M2 and the source of transistor M5. Node 110 is further coupled to the drain of transistor M1 and node 122. Transistors M4 and M6 are coupled to each other at node 124 by the drain of transistor M4 and the source of transistor M6. Node 124 is further coupled to the drain of transistor M3 and node 126.

[0100] When a memory cell (e.g., memory cell 103) stores data bits, the first node of the bit cell is configured to be in a first logical state (logic 1 or logic 0), and the second node of the bit cell is configured to be in a second logical state (logic 0 or logic 1). The first and second logical states are complementary to each other. In some embodiments, the first logical state at the first node may represent the logical state of the data bits stored in the memory cell. For example, in Figure 1BIn the embodiment shown, when memory unit 103 stores data bits in a logic 1 state, node 110 is configured to be in a logic 1 state, while node 124 is configured to be in a logic 0 state.

[0101] To read the logic state of data bits stored in memory cell 103, BL 107 and BLB 109 are precharged to VDD (e.g., logic high). WL 105 then confirms or activates to logic high via a confirmation signal, thereby turning on access transistors M5 and M6. Specifically, rising edges of the confirmation signal are received at the gates of access transistors M5 and M6, respectively, to turn them on. Once access transistors M5 and M6 are turned on, the precharged BL 107 or BLB 109 can begin to discharge based on the logic state of the data bits. For example, when memory cell 103 stores logic 0, node 110 can present a voltage corresponding to logic 0, while node 124 can present a voltage corresponding to complementary logic 1. In response to the turn-on of access transistors M5 and M6, a discharge path can be provided, starting from the precharged BL 107, passing through access transistor M5 and pull-down transistor M2, and ending at ground 128. Along the discharge path, access transistor M5 and pull-down transistor M2 can conduct currents I5 and I2, respectively. When the voltage level on BL 107 is pulled down by this discharge path, pull-down transistor M4 can remain off. Therefore, BL 107 and BLB 109 can each present a voltage level to generate a sufficiently large voltage difference between BL 107 and BLB 109. Thus, the sense amplifier 118 coupled to BL 107 and BLB 109 can use the polarity of the voltage difference to determine whether the logic state of the data bit is logic 1 or logic 0.

[0102] RSNM is an SNM present when WL and BL / BLB are connected to VDD during a read operation. When WL is on (or enabled), the node storing logic 0 may be located in the middle of a voltage divider (e.g., between transistors M5 and M2 or between transistors M6 and M4). Therefore, this "read interference" defect can draw current from BL through transistors M5 and M2 to reference 128 or from BLB through transistors M6 and M4 to reference 128. During a read or write operation, the half-select memory cell 103 along the selected WL 105 undergoes a virtual read operation. And due to read interference, if the voltage variation along BL and BLB caused by read interference is higher than RSNM, the stored data in the half-select memory cell 103 is at risk of experiencing unintentional bit flips. In preprocessing, the bit cell (or memory cell 103) mismatch becomes larger, which contributes to the noise voltage at nodes 110 or 124. When subjected to high temperatures and high voltages in fast NMOS with slow PMOS or fast NMOS with fast PMOS (FS / FF), read interference can cause cells with strong pull-down transistors M2 or M4 to flip. For example, at high temperatures and higher mismatch conditions, RSNM decreases, which increases the risk of unintentional bit flips.

[0103] For example, at the start of a read operation on memory cell 103, node 110 may have logic 0 (e.g., 0V), while node 124 may have logic 1 (e.g., VDD). BL and BLB may be pre-charged, for example, to VDD. When transistor M5 is turned on, the charge stored in BL flows through transistor M5 and to node 110. This influx of charge causes the voltage at node 110 to bounce from 0V to a voltage greater than 0V. If the bounce at node 110 is high enough, it can cause the inverters, including transistors M3 and M4, to transition the output at node 124 from VDD to 0V, resulting in unintentional bit flipping. Therefore, it is necessary to keep the voltage bounce at node 110 low.

[0104] Existing methods for addressing this problem are insufficient. For example, increasing the supply voltage of an SRAM cell by adding a boost cap is inadequate because it also strengthens the pull-up PMOS transistor, which can affect the ability to write data into the SRAM cell during write operations. Another example is that reducing the size of the WL driver to decrease the rising edge of the voltage level on the WL can lead to performance degradation and reduced ability to write memory cells at low voltages and temperatures. Furthermore, cells at the end of the WL can suffer additional performance degradation and read margin effects. Moreover, designing different sizes for the WL driver results in greater design effort and higher performance, power, and / or area (PPA) degradation. Therefore, it is necessary to mitigate the risk of unintentional bit flips due to RSNM violations without affecting PPA.

[0105] Figure 2A The illustration shows an example programmable CS circuit 200 according to some embodiments. The programmable CS circuit 200 includes a programmable bit line (PBL) (or charge-shared bit line or CSBL), a CS transistor (or CS sub-circuit) 206, and a discharge transistor (or discharge circuit) 208. The PBL can be schematically represented as a PBL capacitor (PBLC) 204, which may include parasitic capacitors. Both the CS transistor 206 and the discharge transistor 208 can be controlled by a control signal provided on control signal line 210, although embodiments are not limited thereto. The programmable CS circuit 200 is connected to the bit line BL having a parasitic capacitor 202. Although some circuit components such as Figure 2A As shown, but not limited to, the programmable CS circuit 200 may be provided with more, fewer, or different components. It should be understood that various modifications can be made to the programmable CS circuit 200 within the spirit and scope of this disclosure. Furthermore, although not separately illustrated or described, the disclosed techniques can be applied to BLBs, not just BLBs. For example, the programmable CS circuit 200 may also be positioned adjacent to the BLB to reduce or eliminate unintentional bit flipping caused by BLB voltage bounce. Therefore, for simplicity and clarity, similar descriptions are omitted.

[0106] Typically, in an integrated circuit chip including a memory device, the metal structures within metal layers ML0, ML2, ML4, and ML6 (and potentially other layers) (even-numbered metal layers) can be substantially parallel to each other, and the metal structures within metal layers ML1, ML3, ML5, and ML7 (and potentially other layers) (odd-numbered metal layers) can be substantially parallel to each other. Metal structures formed in even-numbered metal layers can be formed substantially perpendicular to metal structures formed in odd-numbered metal layers. Therefore, by forming vias filled with conductive material at the overlap locations of even-numbered and odd-numbered metal layers, electronic components can be electrically connected to each other, even if they are disposed separately.

[0107] PBL (and PBLC 204) can be formed as a metal structure in a metal layer of a memory device. If the bit line BL of the memory device is formed as a metal structure in metal layer ML0, then PBL can be formed as a metal structure in an even-numbered metal layer (e.g., metal layers ML2, ML4, or ML6). If the bit line BL is formed as a metal structure in metal layer ML1, then PBL can be formed as a metal structure in an odd-numbered metal layer (e.g., metal layers ML3, ML5, or ML7).

[0108] When manufacturing a memory device (e.g., memory device 100), the memory device may include a set of partitioned memory blocks (PBLs) of the same length and arranged parallel to the blue line (BL). However, different memory device sizes can result in different PBL lengths. For example, for a first memory device with a large number of white space drivers (WLs) and a small number of I / O pads, there may be a PBL of the same or substantially the same length as the BL. If a second memory device has fewer WLs than the first memory device but the same number of I / O pads, the second memory device may have a PBL of approximately half the length of the BL. Furthermore, for a third memory device with the same number of WLs as the first memory device and more I / O pads than both the first and second memory devices, the length of the PBL may be smaller (e.g., 1 / 8 of the BL length). Still further, for a fourth memory device with fewer WLs than the first and third memory devices but more I / O pads than the second memory device, the length of the PBL may be smaller (e.g., 1 / 32 of the BL length). Therefore, as the number of WL drivers decreases and the number of I / O pads increases, the length of the PBL can be reduced. Similarly, PBLs of approximately 1 / 4, 1 / 8, 1 / 16, or 1 / 32 of the BL length can exist. The capacitance of the PBLC 204 can vary depending on the length of the PBL relative to the BL. For example, the longer the PBL, the larger the capacitance of the PBLC 204 can be. Although certain lengths and ratios of the PBL relative to the BL are described, the embodiments are not limited thereto, and the length of the PBL can be less than, equal to, or greater than any length of the BL.

[0109] The CS transistor 206 has source and drain (S / D) terminals that can be connected to the BL and PBLC. When the CS transistor 206 is turned on, the charge stored in the BL (and parasitic capacitor 202) can be shared with the PBL and charge the PBLC 204. The CS transistor 206 can be controlled by a control signal on control signal line 210. The CS transistor 206 can be programmed based on the on-time of the CS transistor 206. For example, if the CS transistor 206 is turned on for a shorter charge-sharing period, less CS can occur between the BL and PBLC 204, and if the CS transistor 206 is turned on for a longer CS period, more CS can occur between the BL and PBLC 204, making the charge stored in the BL and PBLC 204 similar. Therefore, by taking into account the charge rate of the PBL, the CS transistor 206 can provide the required amount of charge from the BL.

[0110] Discharge transistor 208 can be turned on to discharge the charge on PBLC 204 to ground. For example, the discharge can be performed before PBL receives charge from BL through CS transistor 206.

[0111] In some embodiments, CS transistor 206 includes a PMOS transistor, while the discharge transistor includes an NMOS transistor. Therefore, when discharge transistor 208 is turned on, CS transistor 206 can be turned off, and when discharge transistor 208 is turned off, CS transistor 206 can be turned on. However, embodiments are not limited thereto, and CS transistor 206 may include an NMOS transistor or any combination of circuit components that can share the charge from BL to PBLC 204. Similarly, discharge transistor 208 may include a PMOS transistor or any combination of circuit components that can collectively discharge the charge on PBLC 204 to ground.

[0112] A controller (e.g., controller 102) may provide control signals to control signal line 210. The controller may calculate the charge sharing period, including the duration of turning CS transistor 206 on / off and discharge transistor 208 off. The amount of charge sharing may depend on, for example, the number of WL drivers and / or the number of input / output (I / O) pads on the memory device. The amount of CS may depend on the number of WL drivers and I / O pads because memory devices of different granularities (e.g., memory device 100) may be more prone to stronger and / or higher voltage bounces than other devices.

[0113] For example, if a memory device has 1024 WL drivers and 8 I / O pads, it is more prone to voltage bounce. Therefore, the PBL length can be set to be similar to the BL length of the memory device. On the other hand, if a memory device has 240 WL drivers and 72 I / O pads, it is less prone to voltage bounce compared to a memory device with 1024 WL drivers and 8 I / O pads. Therefore, a 240×72 memory device can include a PBL with a smaller ratio (e.g., the PBL length is 1 / 4 of the BL length). Another example is that if a memory device has 1024 WL drivers and 144 I / O pads, this memory device is less prone to voltage bounce than a 240×72 memory device. This memory device can have a PBL with a smaller ratio (e.g., the PBL length may be 1 / 8 of the BL length). As a further example, if a memory device has 240 WL drivers and 144 I / O pads, the PBL length can be 1 / 32 of the BL length because this memory device is less prone to voltage bounce. Therefore, the controller can allow the BL and PBL to share charge, and the PBL length depends on which WL driver and I / O pad the controller reads the memory cell from. Thus, the memory device can be designed with a PBL length that depends on the size of the memory device, maximizing the performance of the memory device during read operations. Therefore, the charge stored on the BL can be reduced, making ( Figure 1BThe voltage bounce occurring at node 110 can be reduced, which can increase RSNM and eliminate unintentional bit flips.

[0114] Figure 2B The diagram illustrates example waveforms according to some embodiments, which help to demonstrate the use during a read operation. Figure 2A The effect of a programmable charge-sharing circuit is described. Graph 250 includes several waveforms 252, 254, 256, and 258 at different nodes of a memory cell (e.g., memory cell 103), while graph 260 is a detailed view of a portion of graph 250. The x-axis of graphs 250 and 260 corresponds to time, and the y-axis corresponds to voltage. Waveforms 252 and 254 are interpolated to show differences. Similarly, waveforms 256 and 258 are interpolated to show differences. Furthermore, waveforms 252 and 254 are placed over waveforms 256 and 258 to show the voltage at different nodes occurring at the same point in time during a read operation (e.g., after pre-charge is complete). Those skilled in the art will recognize that the waveforms are shown as examples, and the embodiments are not limited thereto.

[0115] Waveform 252 is measured at BL (e.g., BL of memory cell 103) without a programmable charge-sharing circuit. Waveform 254 is measured at BL (e.g., BL of memory cell 103) using, for example, a programmable charge-sharing circuit 200. Waveform 256 is measured at a voltage divider node (e.g., node 110) between an access transistor (e.g., transistor M5) and a pull-down transistor (e.g., transistor M2) without a programmable charge-sharing circuit. And waveform 258 is measured at a voltage divider node (e.g., node 110) between an access transistor (e.g., transistor M5) and a pull-down transistor (e.g., transistor M2) using a programmable charge-sharing circuit 200.

[0116] At the same point in time during the read operation, the voltage measurement of waveform 252 is greater than the voltage measurement of waveform 254. Therefore, as shown in waveform 256, the voltage measurement at the voltage divider node is greater than the voltage measurement at the voltage divider node in waveform 258.

[0117] As shown in detailed figure 260, the voltage measurement of a memory device including a programmable charge-sharing circuit (shown in waveform 258) is approximately 37 mV lower than the voltage measurement of a memory device without a programmable charge-sharing circuit (shown in waveform 256). Due to the reduced voltage at the voltage divider node, the memory cell has an increased RSNM, which reduces and / or eliminates the possibility of unintentional bit flipping.

[0118] Figure 3The illustration shows an example CS tile matrix 300 according to some embodiments of the CS ratio. The x-axis corresponds to the number of I / O pads on the memory device (e.g., memory device 100), while the y-axis corresponds to the number of WL drivers on the memory device. As mentioned above, the length of the PBL (which determines how much charge sharing occurs) can depend on the number of WL drivers and I / O pads of the memory device. In this disclosure, the terms "memory array" and "memory device" are used interchangeably to refer to a matrix of memory cells arranged in WL drivers and I / O pads.

[0119] The CS tile matrix 300 may include multiple tiles with different boundaries, depending on the number of WL drivers and the number of I / O pads. For example, tile 310 may indicate that for all memory arrays with Y2 to Y3 WL drivers and X0 to X1 I / O pads, the CS ratio may be 1:1, meaning that the PBL may be the same length as the BL. Tile 320 may indicate that for all memory arrays with Y2 to Y3 WL drivers and X2 to X3 I / O pads, the CS ratio may be 1:8, meaning that the PBL length may be 1 / 8 of the BL length. Tile 330 may indicate that for all memory arrays with Y0 to Y1 WL drivers and X0 to X1 I / O pads, the CS ratio may be 1:4, meaning that the PBL length may be 1 / 4 of the BL length. Tile 340 can indicate that for all memory arrays with WL drives of number Y0 to Y1 and I / O pads of number X2 to X3, the CS ratio can be 1:32, which means that the PBL length can be 1 / 32 of the BL length.

[0120] Although the CS tile matrix 300 includes four tiles, the embodiments are not limited to this, and any number of tiles and configurations can be considered. For example, there may be more or fewer tiles in the x-direction or y-direction. Furthermore, the tiles may have non-quadrilateral shapes. For example, a chip designer may decide that a tile may include various shapes, such as rectangles, hexagons, circles, etc., depending on how the chip designer chooses to design the memory array and how much charge sharing occurs within that memory array.

[0121] Figure 4A The illustration shows an example block diagram of a memory device 400 according to some embodiments. The memory device 400 includes memory arrays 402 and 404, a WL driver 412 (e.g., WL driver 112), a tracking array 440, a main controller 410, and input / output (I / O) circuitry 452 and 454. The WL driver 412, the main controller 410, and / or the tracking array 440 may be collectively referred to as a controller (e.g., controller 102) in this disclosure. Those skilled in the art will recognize that... Figure 4AThe example block diagram does not include certain signal lines and / or circuits that may be implemented as part of memory device 400, and for clarity and simplicity, these signal lines and / or circuits are omitted.

[0122] Memory arrays 402 and 404 may include arrays of SRAM memory cells (e.g., memory cell 103) disposed in WL drivers and I / O pads. Memory arrays 402 and 404 may be located on opposite sides of word line driver 412.

[0123] Various circuits and signal lines can be used to mold and / or track memory arrays so that the main controller 410 can accurately and timely generate signals for the operation of memory device 400. For example, the tracking array 440 may include an array of SRAM memory cells (or I / O pads) used to time-track memory device 400 via a TRKBL signal output to the main controller 410, so that the main controller 410 knows when to trigger certain clock and / or control signal edges. For example, the TRKBL signal line may simulate bit lines in SRAM memory arrays 402 and 404, such that the TRKBL signal can rise and fall based on conditions of SRAM memory arrays 402 and 404. For example, the TRKBL signal may be triggered when the CKPB signal can rise and fall, as will be described in further detail below.

[0124] The main controller 410 can be connected to the WL driver 412. The main controller 410 can receive a TRKBL signal delayed to the TRKBLD signal to generate a charge-sharing enable CSENB signal, which can be used for, for example... Figure 2A The control signal line 210 provides control signals. For example, the charge-sharing enable signal CSENB can be delayed by an inverter buffer to generate the GLB_CSENB_L signal for SRAM array 402 and the GLB_CSENB_R signal for SRAM array 404. The CSENB signal can be generated using a NAND gate that receives the TRKBLD signal and the BLEQB signal as inputs; it is the signal that controls / enables BL / BLB precharge. The BLEQB signal can be input to an inverter, which can be used to generate global BLEQB signals (e.g., GLB_BLEQ_L for SRAM array 402 and GLB_BLEQ_R for SRAM array 404), which are routed to all I / O circuits. Within each I / O circuit, a local BLEQB signal LOC_BLEQB can be generated for precharge circuitry within the I / O circuit. Figure 4AAs shown, a buffer (e.g., multiple inverters connected in series) can be used to delay the CSENB signal. Although some circuit components are shown for generating certain signals, the embodiments are not limited thereto, and a variety of other circuit components or combinations of circuit components can be used to generate the same or similar signals. For example, two or more inverters (e.g., four, six, etc.) can be used as buffers to delay the CSENB signal.

[0125] Among other things, each of the I / O circuits 452 and 454 may include a sense amplifier (e.g., sense amplifier 118). I / O circuits 452 and 454 may receive inputs including, for example, input data and write enable signals, and read data from memory cells in SRAM arrays 402 and 404 as outputs. Although not shown, those skilled in the art will recognize that multiple I / O circuits may be arranged adjacent to SRAM arrays 402 and 404 to write data to or read data from memory cells. Furthermore, the location number of the I / O pads relative to the main controller 410 may be increased and correspond to... Figure 3 The x-axis of matrix 300. For example, the I / O circuit 452 closest to the main controller 410 can be X0 on the x-axis of matrix 300, while the I / O circuit (not shown) located on the far left can represent X3 on the x-axis. Similarly, the I / O circuit 454 closest to the main controller 410 can be X0 on the x-axis of matrix 300, while the I / O circuit (not shown) located on the far right can represent X3 on the x-axis.

[0126] I / O circuit 452 may include CS transistors 422a and 422b (e.g., CS transistor 206) and discharge transistors 432a and 432b (e.g., discharge transistor 208). CS transistor 422a may be connected to bit line BL0 (e.g., ...). Figure 2A BL) and programmable bit line PBL0 (e.g., Figure 2A The PBL), and the CS transistor 422b can be connected to the bit line bar BLB0 (e.g., with Figure 2A The BL (relative to BLB) and programmable bit bar PBLB0 (e.g., with Figure 2A The PBL is the programmable BLB. I / O circuitry 454 may include CS transistors 422c and 422d (e.g., CS transistor 206) and discharge transistors 432c and 432d (e.g., discharge transistor 208). CS transistor 422c may be connected to bit line BL1 (e.g., ...). Figure 2A BL) and programmable bit line PBL1 (e.g., Figure 2A The PBL), while the CS transistor 422d can be connected to the bit line bar BLB1 (e.g., with the PBL), and the CS transistor 422d can be connected to the bit line bar BLB1 (e.g., with the PBL). Figure 2AThe BL (relative to BLB) and the programmable bit bar PBLB1 (e.g., with Figure 2A (This is the PBL as opposed to a programmable BLB). For the sake of simplicity, similar descriptions will not be repeated.

[0127] Figure 4B The illustration shows a timing diagram 450 illustrating an example operation of a memory device 400 according to some embodiments. The clock signal CKPB may include a clock signal used by an SRAM array for storing, retrieving, and retaining data. The BLEQB signal may be similar to... Figure 4A The BLEQB signal and TRKBL signal are similar. Figure 4A The TRKBL signal and TRKBLD signal can be similar to Figure 4A The TRKBLD signal, and the CSENB signal can be similar to Figure 4A The CSENB signal. The GLB_CSENB_L and GLB_CSENB_R signals can be similar to the GLB_CSENB_L and GLB_CSENB_R signals that provide control signals to the discharge transistor and charge-sharing transistor, respectively.

[0128] Timing diagram 450 shows the positive and negative edges of various signals, which also demonstrates how to determine the charge sharing period. For example... Figure 4A As shown, the precharge enable signal BLEQB and the delayed BL tracking signal TRKBLD can be input into the inverting circuit to generate the charge sharing enable signal CSENB. CSENB can be delayed by a buffer to generate the GLB_CSENB_L and GLB_CSENB_R signals.

[0129] Therefore, charge sharing can begin (e.g., CSENB rises) when pre-charging of BL stops (e.g., BLEQB rises), and charge sharing can stop when the BL tracking signal TRKBL is low enough that voltage bounce does not cause unintentional bit flipping. In some embodiments, the rise of LOC_BLEQB may precede the fall of GLB_CSENB_L / R. In some embodiments, the rise of GLB_CSENB_L / R may precede the fall of LOC_BLEQB. In some embodiments, the fall of BLEQB may precede the rise of TRKBLD. Therefore, the charge sharing period can be determined by the timing of the pre-charging stop and the voltage drop of the TRKBL signal.

[0130] In some embodiments, charge sharing can be made lower for higher voltages. For example, if VDD is 1.5V, the amount of charge sharing can increase compared to if VDD is 1.1V. Furthermore, the pre-charge circuit may include p-type transistors cross-coupled to the BL and BLB to be pre-charged by the p-type transistor. If the BLB drops excessively due to charge sharing when reading logic 0 from the memory cell, the voltage drop in the BLB can cause the cross-coupled p-type transistor to turn on, thereby increasing the voltage in the BL to logic 0 because the voltage drop in the BLB exceeds the threshold voltage of the p-type transistor (e.g., for a 3nm node, the threshold voltage of the cross-coupled p-type MOS transistor is approximately 350mV to approximately 400mV). Therefore, charge sharing in the BLB and PBLB can be less during the reading of logic 0 from the memory cell.

[0131] Figure 5 The illustration shows an example programmable CS circuit 500 according to some embodiments. The programmable CS circuit 500 is similar to the programmable CS circuit 200, except that it includes a delay chain 512 (including inverters 512a and 512b). For example, parasitic capacitor 502 is similar to parasitic capacitor 202, PBLC 504 is similar to PBLC 204, CS transistor 506 is similar to CS transistor 206, discharge transistor 508 is similar to discharge transistor 208, and the control signal is similar to control signal 510. Therefore, similar descriptions are omitted.

[0132] Delay chain 512 can add a delay to the control signal sent to charge-sharing transistor 506. This allows discharge transistor 508 to discharge the PBL (and PBLC 504) for a longer period. This can be beneficial for balancing the gate delay between the signal path of CS transistor 506 and the signal path of discharge transistor 508. Although delay chain 512 shows two inverters 512a and 512b, the embodiment is not limited to this, and more than two inverters may be considered, depending on how much delay needs to be added to match the gate delay between the two signal paths. Similarly, delay chains can be added to other signal paths (e.g., the signal path of discharge transistor 508).

[0133] Figure 6The illustration shows an example programmable CS circuit 600 according to some embodiments. Programmable CS circuit 600 is similar to programmable CS circuit 200, except that programmable CS circuit 600 includes CMOS transistors to perform charge sharing between BL and PBL (instead of only one PMOS transistor in programmable CS circuit 200) using complementary control signals 610a and 610b (instead of only one control signal 210 in programmable CS circuit 200). For example, parasitic capacitor 602 is similar to parasitic capacitor 202, PBLC 604 is similar to PBLC 204, and discharge transistor 608 is similar to discharge transistor 208. Therefore, similar descriptions are omitted.

[0134] When NMOS transistor 606a and PMOS transistor 606b are used for charge sharing between BL and PBL, charge sharing can occur more quickly. Control signal 610a can be complementary to control signal 610b. For example, an inverter can be added so that the two signals are opposite to each other to control NMOS transistor 606a and PMOS transistor 606b.

[0135] Figure 7 The illustration shows an example programmable CS circuit 700 according to some embodiments. Programmable CS circuit 700 is similar to programmable CS circuit 200, except that programmable CS circuit 700 includes a delay chain 712 (including inverters 712a and 712b), and programmable CS circuit 700 includes NMOS transistor 706a and PMOS transistor 706b as charge-sharing transistors (instead of a PMOS charge-sharing transistor 206 in programmable CS circuit 200). For example, parasitic capacitor 702 is similar to parasitic capacitor 202, PBLC 704 is similar to PBLC 204, CS transistor 706 is similar to CS transistor 206, discharge transistor 708 is similar to discharge transistor 208, and control signal is similar to control signal 710. Therefore, similar descriptions are omitted.

[0136] Delay chain 712 can add a delay to the control signal sent to charge-sharing transistor 706. This allows discharge transistor 708 to discharge the PBL (and PBLC 704) for a longer period. This can be beneficial for balancing the gate delay between the signal path of CS transistor 706 and the signal path of discharge transistor 708. Although delay chain 712 shows two inverters 712a and 712b, the embodiment is not limited to this, and more than two inverters may be considered, depending on how much delay needs to be added to match the gate delay between the two signal paths. Similarly, delay chains can be added to other signal paths (e.g., the signal path of discharge transistor 708).

[0137] When NMOS transistor 706a and PMOS transistor 706b are used for charge sharing between BL and PBL, charge sharing can occur more quickly. Control signal 710a can be complementary to control signal 710b. For example, an inverter can be added so that the two signals are opposite to each other to control NMOS transistor 706a and PMOS transistor 706b. Furthermore, NMOS transistor 706a can be gated by control signal 710a output from inverter 712a. Therefore, by combining delay chain 712 and the CMOS charge-sharing transistor with control signal 710a, the area of ​​the memory device can be reduced.

[0138] refer to Figure 2A and Figures 5 to 7 Each of the embodiments described in this disclosure may include one or more PBLs, which may be formed as a metal structure in any of the metal layers M0 to M7. Similarly, the PBL to which the programmable CS circuits 200, 500, 600, or 700 are connected may depend on the CS ratio selected by the user, which may depend on which WL driver and I / O pad the memory cell is located on.

[0139] Figure 8 The illustration shows a flowchart of an example method 800 for operating a memory device according to some embodiments. Method 800 can be used to reduce voltage bounce within a memory cell to increase RSNM and reduce the probability of unintentional bit flips within the memory cell. Note that method 800 is merely an example and is not intended to limit this disclosure. Therefore, it can be understood that... Figure 8 Method 800 provides additional operations before, during, and after, and some other operations can only be briefly described in this document.

[0140] In summary, method 800 begins at operation 802, during a read operation of a memory cell, by providing a first voltage to a control signal line connected to a discharge circuit and a charge-sharing circuit. Method 800 proceeds to operation 804, where, based on the first voltage on the control signal line, the programmable bit line is discharged using the discharge circuit. Method 800 proceeds to operation 806, where a second voltage, different from the first voltage, is provided to the control signal line. Method 800 proceeds to operation 808, where the bit line is connected to the programmable bit line based on the second voltage on the control signal line.

[0141] Referring to operation 802, during a read operation of a memory cell (e.g., memory cell 103), a controller (e.g., controller 102) may provide a first voltage (e.g., an on-state voltage, such as logic high or power supply voltage VDD) to control signal lines (e.g., control signal line 210) connected to a discharge circuit (e.g., discharge transistor 208) and a charge-sharing circuit (e.g., charge-sharing transistor 206). Before providing the first voltage to the control signal lines, the bit lines may be pre-charged to a specific pre-charge voltage (e.g., VDD, VDD / 2, etc.).

[0142] Referring to operation 804, based on providing a first voltage to the control signal line, the discharge circuit can discharge charge on a programmable bit line (e.g., PBL). The PBL may have a length similar to or different from the bit line.

[0143] Referring to operation 806, the controller may provide a second voltage (e.g., shutdown voltage, 0V, etc.) different from the first voltage to the control signal line.

[0144] Referring to operation 808, based on the second voltage on the control signal line, the charge-sharing circuit can be turned on, electrically connecting the bit line to the PBL. When the bit line is connected to the PBL, a portion of the charge on the BL can be transferred to the PBL during the pre-charging period. Once the charge-sharing period is complete, the charge-sharing circuit can be turned off, so that no more charge is transferred from the bit line to the PBL.

[0145] Therefore, at the end of the charge-sharing period, the bit line can have less charge (and voltage) than the pre-charged amount. Because the charge on the bit line is reduced, the charge surge from the bit line to the pull-down transistor is reduced when the memory cell's access transistor is turned on, and the voltage bounce is also reduced. This prevents unintentional bit flipping in the memory cell.

[0146] In one embodiment of this disclosure, a memory device is disclosed. The memory device includes bit lines connected to a plurality of memory cells of a memory array, the bit lines having a first length. The memory device includes a first programmable bit line having a second length determined based on the size of the memory array, and a charge-sharing circuit connected to the bit lines and the first programmable bit line. The charge-sharing circuit is used to transfer charge from the bit lines to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit being used to discharge stored charge in the first programmable bit line.

[0147] In some embodiments, the charge-sharing circuit includes a p-type transistor, which includes a gate terminal connected to a control line.

[0148] In some embodiments, the discharge circuit includes an n-type transistor, which includes a gate terminal connected to a control line.

[0149] In some embodiments, the bit lines are formed as a first metal structure, and wherein the first programmable bit lines are formed as a second metal structure substantially parallel to the first metal structure.

[0150] In some embodiments, the first length is the same as the second length.

[0151] In some embodiments, the first length is different from the second length.

[0152] In some embodiments, the second length is longer for a memory array having a first row number greater than the second row number, and the second length is longer for a memory array having a first column number greater than the second column number.

[0153] In some embodiments, the charge-sharing circuit includes a p-type transistor and an n-type transistor connected in parallel, wherein a first control signal is connected to the p-type transistor, and wherein a second control signal, which is the reverse of the first control signal, is connected to the n-type transistor.

[0154] In some embodiments, the memory device further includes a plurality of inverters connected to the gate terminal of a charge-sharing circuit, wherein control signals are connected to the gate terminals of the input and discharge circuits of the inverters.

[0155] In some embodiments, the charge-sharing circuit includes a p-type transistor and an n-type transistor connected in parallel, wherein the gate terminal of the n-type transistor is connected to the output of the first inverter and the input of the second inverter.

[0156] In another embodiment of this disclosure, a memory system is disclosed. The memory system includes a memory array, which includes bit lines having a first length, a controller for providing control signals to the memory array, and a programmable charge-sharing circuit connected to the controller and the bit lines. The programmable charge-sharing circuit includes a first programmable bit line having a second length determined based on the size of the memory array, and charge-sharing circuitry connected to the bit lines and the first programmable bit line. The charge-sharing circuitry is used to transfer charge from the bit lines to the first programmable bit lines. The programmable charge-sharing circuitry also includes a discharge circuit connected to the first programmable bit line, the discharge circuitry being used to discharge the stored charge in the first programmable bit line.

[0157] In some embodiments, the memory system further includes tracking circuitry for tracking the behavior of bit lines and providing tracking signals to a controller, wherein the controller generates control signals based on the tracking signals.

[0158] In some embodiments, the memory system further includes a precharge circuit for precharging bit lines based on a precharge control signal from a controller, wherein the controller includes a NAND gate for receiving a tracking signal and the precharge control signal as inputs and outputting a control signal.

[0159] In some embodiments, programmable bit lines are arranged parallel to bit lines.

[0160] In some embodiments, the bit lines are formed as a first metal structure, and wherein the first programmable bit lines are formed as a second metal structure substantially parallel to the first metal structure.

[0161] In some embodiments, a first programmable bit line is disposed in a first region of the memory array, wherein the memory system further includes a second programmable bit line, and wherein the first programmable bit line is longer than the second programmable bit line.

[0162] In some embodiments, the memory array includes a plurality of static random access memory cells.

[0163] In another aspect of this disclosure, a method for operating a memory device is disclosed. The method includes, during a read operation of a memory cell, providing a first voltage to a control signal line connected to a discharge circuit and a charge-sharing circuit, discharging a programmable bit line using the discharge circuit based on the first voltage on the control signal line, providing a second voltage different from the first voltage to the control signal line, and connecting the bit line to the programmable bit line based on the second voltage on the control signal line.

[0164] In some embodiments, the method further includes the step of pre-charging the bit line before activating the charge sharing control signal line.

[0165] In some embodiments, the method further includes the steps of: tracking bit lines to output a tracking signal, wherein precharging of the bit lines is initiated based on a precharge control signal, and wherein a charge sharing control signal is generated based on the tracking signal and the precharge control signal.

[0166] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0167] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, It includes: A bit line, which is connected to a plurality of memory cells of a memory array, wherein the bit line has a first length; A first programmable bit line having a second length determined based on the number of multiple word line drivers coupled to the memory array and the number of multiple input / output pads; A charge-sharing circuit connected to the bit line and the first programmable bit line, wherein the charge-sharing circuit is used to transfer a charge from the bit line to the first programmable bit line; and A discharge circuit is connected to the first programmable bit line, wherein the discharge circuit is used to discharge a stored charge in the first programmable bit line.

2. The memory device as claimed in claim 1, characterized in that, The charge-sharing circuit includes a p-type transistor, which has a gate terminal connected to a control line.

3. The memory device as claimed in claim 2, characterized in that, The discharge circuit includes an n-type transistor, which includes a gate terminal connected to the control line.

4. The memory device as claimed in claim 1, characterized in that, The bit line is formed as a first metal structure, and the first programmable bit line is formed as a second metal structure substantially parallel to the first metal structure.

5. The memory device as claimed in claim 4, characterized in that, The first length is the same as the second length.

6. The memory device as claimed in claim 4, characterized in that, The first length is different from the second length.

7. The memory device as claimed in claim 6, characterized in that, The second length is longer for a memory array having a first row number greater than a second row number, and the second length is longer for a memory array having a first column number greater than a second column number.

8. The memory device as claimed in claim 1, characterized in that, The charge-sharing circuit includes a p-type transistor and an n-type transistor connected in parallel, wherein a first control signal is connected to the p-type transistor, and a second control signal, which is the reverse of the first control signal, is connected to the n-type transistor.

9. The memory device as claimed in claim 1, characterized in that, It further includes a plurality of inverters connected to a gate terminal of the charge-sharing circuit, wherein a control signal is connected to the input of the plurality of inverters and a gate terminal of the discharge circuit.

10. The memory device as claimed in claim 9, characterized in that, The charge-sharing circuit includes a p-type transistor and an n-type transistor connected in parallel, wherein a gate terminal of the n-type transistor is connected to an output of a first inverter and an input of a second inverter.

11. A memory system, characterized in that, It includes: A memory array, the memory array including a bit line having a first length; A controller for providing a control signal to the memory array; and A programmable charge-sharing circuit is connected to the controller and the bit line, the programmable charge-sharing circuit comprising: A first programmable bit line having a second length determined by a number of multiple word line drivers coupled to the memory array and a number of multiple input / output pads; A charge-sharing circuit connected to the bit line and the first programmable bit line, wherein the charge-sharing circuit is used to transfer a charge from the bit line to the first programmable bit line; and A discharge circuit is connected to the first programmable bit line, wherein the discharge circuit is used to discharge a stored charge in the first programmable bit line.

12. The memory system as claimed in claim 11, characterized in that, It further includes a tracking circuit for tracking a behavior of the bit line and providing a tracking signal to the controller, wherein the controller generates the control signal based on the tracking signal.

13. The memory system as claimed in claim 12, characterized in that, It further includes a pre-charge circuit for pre-charging the bit line based on a pre-charge control signal from the controller, wherein the controller includes a NAND gate for receiving the tracking signal and the pre-charge control signal as inputs and outputting the control signal.

14. The memory system as claimed in claim 11, characterized in that, The programmable bit line is set parallel to the bit line.

15. The memory system as claimed in claim 14, characterized in that, The bit line is formed as a first metal structure, and the first programmable bit line is formed as a second metal structure substantially parallel to the first metal structure.

16. The memory system as claimed in claim 15, characterized in that, The first programmable bit line is disposed in a first region of the memory array, and the memory system further includes a second programmable bit line, wherein the first programmable bit line is longer than the second programmable bit line.

17. The memory system as claimed in claim 11, characterized in that, The memory array includes multiple static random access memory units.

18. A method for operating a memory device, characterized in that, The method includes the following steps: During a read operation of a memory cell in a memory array, a first voltage is provided to a control signal line connected to a discharge circuit and a charge-sharing circuit; Based on the first voltage on the control signal line, the discharge circuit discharges a programmable bit line. A second voltage, different from the first voltage, is provided to the control signal line; and Based on the second voltage on the control signal line, a bit line is connected to the programmable bit line. The programmable bit line has a length, and The length is determined based on the number of word line drivers coupled to the memory array and the number of input / output pads.

19. The method as described in claim 18, characterized in that, It further includes the following step: pre-charging the bit line before activating the control signal line of the charge-sharing circuit.

20. The method as described in claim 19, characterized in that, It further includes the following steps: tracking the bit line to output a tracking signal, wherein the pre-charging of the bit line is initiated based on a pre-charge control signal, and wherein a control signal for the charge-sharing circuit is generated based on the tracking signal and the pre-charge control signal.

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