Power-on read circuit

Abstract

A power-on read circuit is provided. The power-on read circuit includes a power voltage detector, a first voltage booster, a voltage selector, a reference voltage generator, and a read voltage generator. The power voltage detector detects a power voltage to generate a control signal. The first voltage booster generates a first boosted voltage according to the control signal. The voltage selector selects the power voltage or the first boosted voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power, and generates a reference voltage according to the control signal based on the selected voltage. The read voltage generator generates a second boosted voltage according to the reference voltage and a frequency signal, and generates a read voltage according to the control signal based on the second boosted voltage. The read voltage is provided to a memory cell array to perform a data read operation.

Description

Technical Field

[0001] This invention relates to a power-on readout circuit, and more particularly to a power-on readout circuit that can operate normally under low power supply voltage. Background Technology

[0002] In flash memory products, some storage cells are used to store specific data. This specific data must be read during power-on. Typically, applying an appropriate read voltage during the power-on read operation ensures that the correct data is read.

[0003] The aforementioned read voltage is typically generated based on a reference voltage. However, during the power supply startup process, the value of this reference voltage cannot be accurately controlled, resulting in the read voltage not being generated correctly. Therefore, the data read during the power supply startup read operation is often suspected of being erroneous. Summary of the Invention

[0004] This invention relates to a power-on readout circuit that can operate normally under low power supply voltage conditions.

[0005] According to an embodiment of the present invention, a power-on read circuit includes a power supply voltage detector, a first boost converter, a voltage selector, a reference voltage generator, and a read voltage generator. The power supply voltage detector detects the voltage value of the power supply voltage to generate a control signal. The first boost converter generates a first boost voltage according to the control signal. The voltage selector selects either the power supply voltage or the first boost voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power supply and generates a reference voltage based on the selected voltage according to the control signal. The read voltage generator generates a second boost voltage based on the reference voltage and a clock signal, and generates a read voltage based on the second boost voltage according to the control signal. The read voltage is provided to the memory cell array to perform a data read operation.

[0006] Based on the above, the power-on read circuit of the present invention can provide a boost voltage via a boost converter during the power supply voltage startup process, which serves as the basis for generating a reference voltage. Based on the reference voltage, the read voltage generator can generate another boost voltage, and based on this boost voltage, generate the read voltage. In this way, data read operations of the memory cell array can be effectively performed. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1This is a block diagram of a power-on read circuit according to an embodiment of the present invention;

[0009] Figure 2 and 4 These are partial circuit diagrams of the power-on readout circuits in different embodiments of the present invention;

[0010] Figure 3 This is a schematic diagram illustrating an implementation of the voltage selector in the power-on readout circuit of this invention.

[0011] Figure 5 This is a schematic diagram of an embodiment of the read voltage generator of the power-on read circuit according to an embodiment of the present invention;

[0012] Figure 6 This is a waveform diagram of the operation of the power-on readout circuit according to an embodiment of the present invention.

[0013] Explanation of icon numbers

[0014] 100, 400, 500: Power-on readout circuit;

[0015] 101: Memory cell array;

[0016] 110: Power supply voltage detector;

[0017] 120, 510: Boost converter;

[0018] 130, 300: Voltage selector;

[0019] 140: Reference voltage generator;

[0020] 150: Read voltage generator;

[0021] 210: Data detector;

[0022] 410: Delay unit;

[0023] 420: Clock signal generator;

[0024] 511: Logic unit;

[0025] 512: Charge pump;

[0026] 513: Voltage divider;

[0027] 520: Read timing controller;

[0028] CMP1: Comparator;

[0029] dt: Delay time;

[0030] EN: Enable signal;

[0031] OSC: Clock signal;

[0032] PORead, PORead': Read voltage;

[0033] PORoff: Reading end signal;

[0034] PU: Control signal;

[0035] R1, R2: Resistors;

[0036] RDATA: Data;

[0037] SW1, SW2: Switches;

[0038] t1~t3: Time points;

[0039] VCC: Power supply voltage;

[0040] Vdiv: Voltage divider voltage;

[0041] VPP: Boost voltage;

[0042] VPPBGR: Boost voltage;

[0043] VREF: Reference voltage;

[0044] VSEL: Select voltage. Detailed Implementation

[0045] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0046] Please refer to Figure 1 , Figure 1This is a block diagram of a power-on read circuit according to an embodiment of the present invention. The power-on read circuit 100 is used to perform data reading operations on the memory cell array 101 during the power-on process of the power supply voltage VCC. The power-on read circuit 100 includes a power voltage detector 110, a boost converter 120, a voltage selector 130, a reference voltage generator 140, and a read voltage generator 150. The power voltage detector 110 is used to detect the voltage value of the power supply voltage VCC to generate a control signal PU. Specifically, the power voltage detector 110 generates the control signal PU by detecting the rising state of the power supply voltage VCC during the power-on process. For example, when the power supply voltage VCC rises above a threshold value, the power voltage detector 110 sets the control signal PU to an enabled logic value and enters a power-on read period. Here, the enabled logic value can be set by the designer, for example, a logic value of 1 or a logic value of 0.

[0047] During power-on read, the power-on read circuit 100 performs a data read operation on the memory cell array 101.

[0048] Boost converter 120 is coupled to power supply voltage detector 110. Boost converter 120 receives a control signal PU and is activated when the control signal PU is an enabled logic value, and is used to generate a boost voltage VPPBGR. In this embodiment, boost converter 120 can be a charge pump, and when activated, it performs voltage boosting based on a reference voltage to generate the boost voltage VPPBGR. In this embodiment, the boost voltage VPPBGR is always higher than the power supply voltage VCC.

[0049] The boost voltage VPPBGR and the power supply voltage VCC are provided to the voltage selector 130. In this embodiment, the voltage selector 130 selects one of the boost voltage VPPBGR and the power supply voltage VCC to generate the selected voltage VSEL, and provides the selected voltage VSEL to the reference voltage generator 140 as the operating power supply for the reference voltage generator 140. Specifically, the voltage selector 130 selects the boost voltage VPPBGR as the selected voltage VSEL during power-on readout, and selects the power supply voltage VCC as the selected voltage VSEL after power-on readout.

[0050] The reference voltage generator 140 receives a control signal PU and generates a reference voltage VREF based on the selected voltage VSEL according to the control signal PU. During the power supply voltage VCC startup process, the voltage selector 130 can select a boost voltage VPPBGR with a relatively high voltage as the selected voltage VSEL. At this time, the reference voltage generator 140 can effectively generate the reference voltage VREF based on the selected voltage VSEL with a sufficiently high voltage value. In this embodiment, the reference voltage generator 140 can be a bandgap voltage generator.

[0051] On the other hand, the read voltage generator 150 generates a read voltage PORead based on a reference voltage VREF, a control signal PU, and a clock signal OSC. Specifically, the read voltage generator 150 can perform a boost operation based on the reference voltage VREF and the clock signal OSC to generate a boost voltage. The read voltage generator 150 generates the read voltage PORead based on the boost voltage and the control signal PU. The read voltage generator 150 can generate the aforementioned boost voltage through a charge pump operation. Additionally, the read voltage generator 150 can further boost the read voltage PORead to generate a voltage-shifted read voltage PORead'. The voltage-shifted read voltage PORead' is provided to the memory cell array 101 for data read operations on the memory cell array 101.

[0052] After the power-on reading action is completed, the voltage selector 130 changes the selected power supply voltage VCC to be the selected voltage VSEL.

[0053] In this embodiment, the power-on read circuit 100 can effectively perform power-on read operations based on a boost voltage VPPBGR (e.g., equal to 2.1 volts) in applications with low power supply voltage VCC (e.g., equal to 1.4 volts). In other words, the power-on read circuit 100 of this embodiment can support electronic devices to effectively perform power-on read operations in applications operating at low power supply voltages.

[0054] Please refer to the following: Figure 2 , Figure 2 This is a partial circuit diagram of the power-on readout circuit according to an embodiment of the present invention. Figure 2In the power-on read circuit 100, a data detector 210 is further included. The data detector 210 is coupled to the memory cell array 101 and is used to detect the data RDATA read by the memory cell array 101 during the power-on read operation. The memory cell array 101 contains a label indicating whether the data RDATA provided during the power-on read operation is the last data record. The data detector 210 checks whether each piece of read data RDATA contains a label indicating that it is the last data record. When the read data RDATA has a label indicating that it is the last data record, it indicates that the power-on read operation has been completed, and the data detector 210 can generate a read end signal PORoff.

[0055] exist Figure 1 In this embodiment, a read end signal PORoff can be provided to the boost converter 120, causing the boost converter 120 to stop operating. Alternatively, the voltage selector 130 can also select either the power supply voltage VCC or the boost voltage VPPBGR to generate the selected voltage VSEL based on the read end signal PORoff. Specifically, when the read end signal PORoff indicates that the power-on read operation is not complete (during the power-on read period), the voltage selector 130 selects the boost voltage VPPBGR to generate the selected voltage VSEL. Conversely, when the read end signal PORoff indicates that the power-on read operation is complete (after the power-on read period), the voltage selector 130 selects the power supply voltage VCC to generate the selected voltage VSEL.

[0056] The data detector 210 can be constructed using digital circuitry and used to compare the label in each piece of data RDATA that is read with the label representing the last piece of data, and generate a read end signal PORoff based on the comparison result.

[0057] Please refer to Figure 3 , Figure 3 This is a schematic diagram illustrating an embodiment of the voltage selector in the power-on readout circuit of the present invention. The voltage selector 300 includes switches SW1 and SW2. One end of switch SW1 receives a boost voltage VPPGBR, and the other end of switch SW1 is coupled to switch SW2, providing a selection voltage VSEL. Switch SW2, not coupled to the terminal of switch SW1, receives the power supply voltage VCC. Switches SW1 and SW2 are controlled by the readout voltage PORead or the readout end signal PORoff.

[0058] When both switches SW1 and SW2 are controlled by the read voltage PORead, if PORead is the enabled logic value, switch SW1 is turned on and switch SW2 is turned off. In this case, switch SW1 selects the boost voltage VPPGBR as the selected voltage VSEL. Conversely, if PORead is the disabled logic value, switch SW2 is turned on and switch SW1 is turned off. In this case, switch SW2 selects the power supply voltage VCC as the selected voltage VSEL.

[0059] Both switches SW1 and SW2 are controlled by the read completion signal PORoff. When PORoff is disabled (indicating the power-on read operation is not yet complete), switch SW1 is turned on and switch SW2 is turned off. In this case, switch SW1 selects the boost voltage VPPGBR as the selected voltage VSEL. Conversely, when PORoff is enabled (indicating the power-on read operation is complete), switch SW2 is turned on and switch SW1 is turned off. In this case, switch SW2 selects the power supply voltage VCC as the selected voltage VSEL.

[0060] Please refer to the same time. Figure 1 as well as Figure 4 ,in Figure 4 This is a schematic diagram of a portion of the power-on readout circuit according to another embodiment of the present invention. Figure 4 In the power-on readout circuit 400, a delay unit 410 and a clock signal generator 420 are further included. The delay unit 410 can be coupled to, for example, Figure 1 In this embodiment, the power supply voltage detector 110 and delay unit 410 are coupled to a clock signal generator 420. The clock signal generator 420 generates a clock signal OSC. The clock signal OSC is provided to the read voltage generator 150. The delay unit 410 receives a control signal PU and uses it to delay the control signal PU. The activation time of the clock signal generator 420 is determined based on the output signal of the delay unit 410. The delay unit 410 generates its output signal by delaying the control signal PU; that is, the delay unit 410 causes the clock signal generator 420 to be activated to generate the clock signal OSC only after a certain delay time following the activation of the control signal PU.

[0061] The aforementioned delay time is used to ensure that the reference voltage generator 140 has effectively generated the reference voltage VREF. The clock signal generator 420 can also generate the clock signal OSC only after the reference voltage VREF has been effectively generated, which can avoid the probability of the read voltage generator 150 malfunctioning.

[0062] Please refer to the following: Figure 5 , Figure 5This is a schematic diagram illustrating an embodiment of the read voltage generator in the power-on read circuit of the present invention. The read voltage generator 500 includes a boost converter 510 and a read timing controller 520. The boost converter 510 generates a boost voltage VPP based on a reference voltage VREF and a clock signal OSC. The read timing controller 520 generates a read voltage PORead based on the boost voltage VPP and a control signal PU.

[0063] In this embodiment, the boost converter 510 includes a comparator CMP1, a logic unit 511, a charge pump 512, and a voltage divider 513. The comparator CMP1 compares the reference voltage VREF and the divided voltage Vdiv to generate an enable signal EN. The comparator CMP1 can be implemented using an operational amplifier. The positive input of the operational amplifier receives the reference voltage VREF, the negative input receives the divided voltage Vdiv, and the output generates the enable signal EN. The logic unit 511 is coupled to the comparator CMP1. The logic unit 511 determines whether to output a clock signal OSC based on the enable signal EN. Specifically, when the enable signal EN indicates that the divided voltage Vdiv is less than the reference voltage VREF, the logic unit 511 can output the clock signal OSC to the charge pump 512. Conversely, when the enable signal EN indicates that the divided voltage Vdiv is not less than the reference voltage VREF, the logic unit 511 only outputs the clock signal OSC to the charge pump 512. Figure 5 In this invention, the logic unit 511 can be implemented using AND gates. In other embodiments of the invention, the logic unit 511 can also be implemented using other types of logic gates, without any particular limitation.

[0064] When the charge pump 512 receives the clock signal OSC, it can perform voltage boosting according to the clock signal OSC, generating a gradually increasing boost voltage VPP. When the charge pump 512 does not receive the clock signal OSC, the voltage value of the boost voltage VPP remains unchanged. The voltage divider circuit 513 can be composed of resistors R1 and R2. The voltage divider circuit 513 generates a divided voltage Vdiv by dividing the boost voltage VPP. Figure 5 It is not difficult to see that the comparator CMP1, logic unit 511, charge pump 512 and voltage divider 513 control the generated boost voltage VPP to a preset voltage value through a feedback mechanism.

[0065] On the other hand, the read timing controller 520 includes a latch 521 and a voltage offsetter 522. The latch 521 receives a control signal PU and an enable signal EN. The latch 521 generates a read voltage PORead by latching the control signal PU according to the enable signal EN. The voltage offsetter 522 increases the value of the read voltage PORead based on the boost voltage VPP and generates a voltage-offset read voltage PORead'.

[0066] In this embodiment, the enable signal EN indicates whether the voltage divider voltage Vdiv is greater than the reference voltage VREF. When the voltage divider voltage Vdiv is greater than the reference voltage VREF (indicating that the boost voltage VPP is sufficiently high), the latch 521 can latch the control signal PU according to the enable signal EN, and thereby generate the read voltage PORead. Furthermore, based on the fact that the boost voltage VPP is sufficiently high at this time, the voltage offset read voltage PORead' generated by the voltage offsetter 522 can have a sufficiently high voltage value to perform data reading operations on the memory cell array.

[0067] Incidentally, latch 521 can be implemented using any form of latching circuit for logic signals well known to those skilled in the art. Voltage shifter 522 can be implemented using a low-to-high voltage level shifter well known to those skilled in the art, without any particular limitation.

[0068] Please refer to the following at the same time Figure 1 as well as Figure 6 ,in, Figure 6 This is a waveform diagram illustrating the operation of the power-on readout circuit according to an embodiment of the present invention. When the power supply voltage VCC is activated, it rises from the reference ground voltage VSS. At time t1, the power supply voltage detector 110 pulls the control signal PU to a logic value of 1 based on the power supply voltage VCC, thus initiating the power-on readout operation. At this time, since the power supply voltage VCC has not yet reached a stable state, the voltage value of the control signal PU rises along with the power supply voltage VCC.

[0069] Simultaneously, based on the enabled control signal PU, boost converter 120 can generate a boost voltage VPPBGR and provide the boost voltage VPPBGR to reference voltage generator 140. Reference voltage generator 140 then generates a reference voltage VREF based on the boost voltage VPPBGR.

[0070] After a delay time dt from time point t1, the reference voltage generator 140 can stably provide the reference voltage VREF, and the read voltage generator 150 can begin generating the boost voltage VPP. When the boost voltage VPP reaches a default target, the enable signal EN is pulled low to logic value 0, and the control signal PU is latched to generate the read voltage PORead.

[0071] Subsequently, at time t3, the data detector in the power-on reading circuit 100 can determine that the last piece of data has been read, and generate a reading end signal PORoff accordingly, and end the power-on reading action.

[0072] In summary, the power-on read circuit of the present invention utilizes a boost converter to provide a boosted voltage during the power supply voltage startup process. This boosted voltage serves as the operating power supply for the reference voltage generator, enabling the reference voltage generator to effectively generate a reference voltage even when the power supply voltage is insufficient. In this way, the read voltage generator can generate another boosted voltage based on the reference voltage, and use this boosted voltage to generate the read voltage. This allows for efficient data read operations from the memory cell array even under low power supply voltage conditions.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power-on readout circuit, characterized in that, include: A power supply voltage detector detects the voltage value of the power supply to generate a control signal; A first boost converter generates a first boost voltage according to the control signal; A voltage selector selects either the power supply voltage or the first boost voltage to generate the selected voltage; A reference voltage generator receives the selected voltage as an operating power supply and generates a reference voltage based on the selected voltage according to the control signal. as well as A read voltage generator generates a second boost voltage based on the reference voltage and a clock signal, and then generates a read voltage based on the second boost voltage according to the control signal. The read voltage is provided to the memory cell array to perform a data read operation.

2. The power-on readout circuit according to claim 1, characterized in that, The first booster is a charge pump.

3. The power-on readout circuit according to claim 1, characterized in that, The voltage selector selects the first boost voltage as the selected voltage during the power-on readout period, and the voltage selector selects the power supply voltage as the selected voltage after the power-on readout period.

4. The power-on readout circuit according to claim 1, characterized in that, The reference voltage generator is a bandgap voltage generator.

5. The power-on readout circuit according to claim 3, characterized in that, The first boost voltage is higher than the power supply voltage.

6. The power-on readout circuit according to claim 1, characterized in that, Also includes: A clock signal generator, which generates the clock signal according to the control signal; A delay unit, coupled between the power supply voltage detector and the clock signal generator, delays the control signal to generate a delayed control signal. The clock signal generator adjusts the time for generating the clock signal according to the delay control signal.

7. The power-on readout circuit according to claim 1, characterized in that, The read voltage generator includes: A second boost converter generates the second boost voltage based on the reference voltage and the clock signal; and The timing controller is read to generate the read voltage based on the second boost voltage and according to the control signal.

8. The power-on readout circuit according to claim 7, characterized in that, The second booster includes: A comparator compares the reference voltage with the divided voltage to generate an enable signal; The logic unit determines whether to output the clock signal based on the enable signal; A charge pump, according to the clock signal, generates the second boost voltage; and A voltage divider divides the second boost voltage to generate the divided voltage.

9. The power-on readout circuit according to claim 8, characterized in that, The read timing controller includes: A latch, which generates the read voltage by latching the control signal according to the enable signal; and A voltage offset device that boosts the value of the read voltage based on the second boost voltage.

10. The power-on readout circuit according to claim 1, characterized in that, Also includes: A data detector is used to detect whether the last data has been read. When the last data is read, the data detector generates a read end signal, wherein the first boost converter stops providing the first boost voltage according to the read end signal.

11. The power-on readout circuit according to claim 10, characterized in that, The voltage selector selects the power supply voltage or the first boost voltage based on the read voltage or the read end signal to generate the selected voltage.

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