Memory function verification and data collection system, test method and electronic device

Abstract

The application provides a memory function verification and data acquisition system, a test method and electronic equipment. The system comprises a test motherboard, a test daughterboard, a host computer, external instruments and a power supply system; the test motherboard is in electrical connection with the host computer, the test daughterboard and the external instruments; the test motherboard comprises a core control circuit, a relay control interface circuit, an arbitrary wave generation circuit and other auxiliary circuits which are connected with each other; the test daughterboard is used for high and low temperature test on a measured chip; the host computer is used for sending and receiving instructions to the test motherboard, inquiring and processing data; and the external instruments are used for function test on the measured device and AC / DC parameter acquisition. The application can cover application verification and data acquisition work of most types of memories, and the logic function judgment is accurate, the data acquisition is efficient and accurate, the test system designed is simple to operate, the test effect is good, the test stability and reliability are high, and the application value in engineering is very high.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit chip functional verification and data acquisition technology, and in particular to a memory functional verification and data acquisition system, testing method and electronic device. Background Technology

[0002] There are several drawbacks to using traditional ATE (Automatic Test Equipment) systems for memory functional verification. For example, the test development process is complex, requiring the creation of pin configuration files, level files, timing files, pattern files, and testflow files. This is especially true for large-capacity FLASH test vectors. For NorFlash memories of 256Mbit and above, manually copying tens of millions of row vectors can cause significant lag in the industrial control computer. Completing a single vector typically takes tens of hours, resulting in extremely low development efficiency. Furthermore, traditional ATE systems have limited accuracy in AC / DC parameter testing, failing to meet the high-precision parameter testing requirements of some chips. External source tables are usually needed to compensate for the insufficient accuracy of ATE tests, and configuring these external source tables requires writing low-level algorithms, making the process quite complex. Furthermore, traditional ATE (Automatic Test Equipment) systems have long chip testing times, especially sector erasure and die erasure. For a 1Gbit NorFlash memory, die erasure can take up to 8 minutes, and single-chip testing takes approximately 30-40 minutes. In addition, some ATE systems, due to their configuration limitations, cannot support multi-site testing, and can only complete the testing of one memory chip at a time. Therefore, when the testing demand is high, the memory testing efficiency is very low. Although there is a dedicated testing system for memory chips (T5833) that supports multi-site testing, this system suffers from complex operation procedures, high equipment purchase costs, and complex programming. Therefore, the inventors aim to address the related problems in the existing technology and conduct research and development to improve it. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is to provide a memory function verification and data acquisition system, test method and electronic device that is simple to operate, provides accurate logic function verification and test data, has good test results, and has high test stability and reliability.

[0004] Based on the above objectives, this disclosure provides a memory function verification and data acquisition system in a first aspect, including a test motherboard, a test daughterboard, a host computer, external instruments, and a power supply system.

[0005] The host computer can be electrically connected to the test motherboard, and the test motherboard can also be electrically connected to the test daughterboard and external instruments.

[0006] The test motherboard includes interconnected core control circuits, relay control interface circuits, memory control circuits, ADC sampling circuits, arbitrary wave generation circuits, power conversion circuits, storage circuits, crystal oscillator circuits, filter circuits, communication circuits, reset circuits, and power conversion circuits.

[0007] The test sub-board includes the device under test and peripheral power supply and signal circuits, and is used to perform high and low temperature tests on the chip under test;

[0008] The host computer is used to send control commands to the test motherboard, receive test data, process test data, query the information under test, and set parameters.

[0009] The external instruments are used to perform functional tests on the device under test and to acquire AC / DC parameters.

[0010] The power supply system is used to provide electrical energy to the test motherboard and the test daughterboard.

[0011] In some optional embodiments, the core control circuit of the test motherboard includes: a main control chip, which includes a variable static memory controller and a high-density instruction set;

[0012] The variable static storage controller is used to issue corresponding data / address / control signal types according to different external memory types to match the signal speed;

[0013] The core control circuit is also used to complete data acquisition and processing, protocol conversion, single or multiple sets of high and low level toggling output, and manage and control peripherals.

[0014] In some optional embodiments, the relay control interface circuit of the test motherboard includes: an input signal relay control circuit and an output signal relay control circuit;

[0015] The input signal relay control circuit is used to control the selection of the input excitation signal, which includes an external high-precision power supply, an IO drive signal, and an arbitrary wave generation signal.

[0016] The IO drive signal is used to provide high-level and low-level drive signals and serves as a backup drive source.

[0017] The arbitrary wave generation signal provides excitation signals for square waves, triangular waves, sine waves, cosine waves, and sawtooth waves.

[0018] The output signal relay control circuit is used to select the test source for the output signal of the test chip. The output signal test source includes a high-precision PPMU, a high-precision AD sampling circuit, and an external high-performance oscilloscope.

[0019] The DC parameters of the high-precision PPMU are set via the host computer.

[0020] The high-precision AD sampling circuit is used to acquire multiple signal data and communicate with the main control chip;

[0021] The external high-performance oscilloscope is used to capture and test AC parameters, including chip select enable to data output validity time, output enable to data output validity time, and address setup time.

[0022] In some optional embodiments, the arbitrary wave generation circuit of the test motherboard can simultaneously generate multiple signals of different frequencies to generate high-precision signals.

[0023] The communication circuit of the test motherboard is used to connect with the host computer and communicate with the host computer for data.

[0024] The storage circuit of the test motherboard is used to save data that is not lost when power is off; wherein, the data that is not lost when power is off includes motherboard address information data, key threshold parameters, and extracted data;

[0025] One end of the reset circuit of the test motherboard is connected to the ground button and the main control pin, which can be used to restore the initial state;

[0026] The power conversion circuit of the test motherboard is used to convert electrical energy to power the test motherboard and the control daughterboard.

[0027] In some optional embodiments, the test subboard has an interface for high and low temperature testing, through which the power supply lines and signal lines of the chip under test are led out to enable high and low temperature testing in a high and low temperature chamber.

[0028] In some optional embodiments, the host computer communicates with the test motherboard via a connection cable, and the host computer is used for:

[0029] Send control commands to the test motherboard, the control commands including automatic test commands and single-step test commands;

[0030] Receive test data from the test equipment collected by the test motherboard, the test equipment test data including functional and AC / DC test data;

[0031] Process the received test data, make judgments, output the logical judgment results, and display them;

[0032] Query the test motherboard address number and the ID information of the memory chip under test;

[0033] Enables parameter settings, including AC / DC parameter card limit settings and external source meter range settings;

[0034] It can also be used for single-time acquisition of test sub-board data, timed acquisition of test sub-board data, polling acquisition of test sub-board data, and export of test data.

[0035] In some optional embodiments, the power supply system provides DC power to the test motherboard via a switching power supply, and the test motherboard then provides DC power to the core CPU, internal module circuits and external test daughterboards via a power conversion circuit.

[0036] In some optional embodiments, the external instrument is used to connect with the test equipment when performing AC / DC parameter testing and functional verification, and to receive control signals from the test motherboard to realize functional testing of the device under test and capture AC / DC parameters.

[0037] In a second aspect, based on the same inventive concept, a method for verifying memory function and testing data acquisition is also disclosed, comprising:

[0038] The test operation instructions in the host computer are sent to the core CPU of the test motherboard.

[0039] In response to the core CPU, test operation commands from the host computer are sent to the optimization controller, high-precision PPMU, and high-performance oscilloscope;

[0040] Read the memory ID in response to receiving the output signal from the optimization controller;

[0041] Upon receiving the output signal from the high-precision PPMU, a DC parameter test is performed.

[0042] Upon receiving the output signal from the high-performance oscilloscope, an AC parameter test is performed.

[0043] The test results data are uploaded to the host computer.

[0044] In a second aspect, based on the same inventive concept, an electronic device is also disclosed, which is capable of operating the memory function verification and data acquisition system described in any of the above solutions;

[0045] The electronic device includes a memory, a processor, and a computer program stored in the memory and executable by the processor. When the processor executes the program, it implements a method for memory function verification and data acquisition testing.

[0046] As described above, this disclosure provides a memory function verification and data acquisition system, testing method, and electronic equipment. Addressing the insufficient testing accuracy of ATE (Automatic Test Equipment) systems, the accuracy of AC / DC parameter testing of memory chips can be enhanced by using an external source table. Addressing the limited storage depth and complex test program writing requirements of ATE systems, the dedicated FSMC memory controller can efficiently manage NORFLASH, NAND FLASH, SRAM, serial EEPROM, and SPI serial FLASH memories, eliminating the need for writing level files, timing files, and pattern files required by ATE test equipment, thus greatly improving the development efficiency of test personnel. The combination of a motherboard and daughterboard allows for the matching of memory chips of different models and interface types. This application can cover the application verification and data acquisition work of most types of memory, with accurate logical function judgment, efficient and precise data acquisition, and a simple-to-operate, effective, stable, and reliable testing system, possessing significant engineering application value. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a topology diagram of the system according to an embodiment of the present disclosure;

[0049] Figure 2 This is a topology diagram of the test motherboard of the system according to an embodiment of the present disclosure;

[0050] Figure 3 This is a schematic diagram of the interface of the host computer of the system according to an embodiment of this disclosure;

[0051] Figure 4 This is a flowchart of the testing method according to an embodiment of the present disclosure;

[0052] Figure 5 This is a flowchart of the testing method according to an embodiment of the present disclosure;

[0053] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0055] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0056] Before describing in detail the memory function verification and data acquisition system, testing method and electronic device provided in this application, the application scenario and inventive concept of this application will be described first.

[0057] This invention relates to a memory function verification and data acquisition system, belonging to the field of integrated circuit chip function verification and data acquisition. As an auxiliary testing tool for memory chips using ATE testing and functional verification, this invention can perform logic function verification and AC / DC parameter testing on the memory. Addressing the insufficient accuracy of ATE testing equipment, the accuracy of AC / DC parameter testing of memory chips can be enhanced by using an external source table. Addressing the limited storage depth and complex test program writing requirements of ATE equipment, the FSMC dedicated memory controller can efficiently manage NORFLASH, NAND FLASH, SRAM, serial EEPROM, SPI serial FLASH, and other types of memory, thus eliminating the need for writing level files, timing files, and pattern files required by ATE testing equipment, greatly improving the development efficiency of testers. The combination of a motherboard and daughterboard allows for compatibility with memory chips of different models and interface types. The test system designed in this invention is simple to operate, provides accurate logic function verification and test data, exhibits good test results, and demonstrates high stability and reliability.

[0058] There are several drawbacks to using traditional ATE (Automatic Test Equipment) systems for memory functional verification. For example, the test development process is complex, requiring the creation of pin configuration files, level files, timing files, pattern files, and testflow files. This is especially true for large-capacity FLASH test vectors. For NorFlash memories of 256Mbit and above, manually copying tens of millions of row vectors can cause significant lag in the industrial control computer. Completing a single vector typically takes tens of hours, resulting in extremely low development efficiency. Furthermore, traditional ATE systems have limited accuracy in AC / DC parameter testing, failing to meet the high-precision parameter testing requirements of some chips. External source tables are usually needed to compensate for the insufficient accuracy of ATE tests, and configuring these external source tables requires writing low-level algorithms, making the process quite complex. Furthermore, chip testing on traditional ATE (Automatic Test Equipment) machines is time-consuming, especially sector erasure and die erasure. For 1Gbit NorFlash memory, die erasure can take up to 8 minutes, and single-chip testing takes approximately 30-40 minutes. In addition, some ATE machines, due to their configuration limitations, cannot support multi-site testing and can only test one memory chip at a time. Therefore, when testing demand is high, memory testing efficiency is very low. Although there is a dedicated testing system for memory chips (T5833) that supports multi-site testing, this system suffers from complex operation procedures, high equipment purchase costs, complex programming, and is sourced from overseas, making the supply chain extremely unreliable.

[0059] Therefore, considering the functional and structural characteristics of memory chips, it is essential to develop a domestically produced and user-friendly memory testing system / device. The designed application verification system and data acquisition system must be: compatible with memory chips from different manufacturers, models, and package types; efficiently manage NORFLASH, NANDFLASH, SRAM, serial EEPROM, SPI serial FLASH, and other memory types using a dedicated FSMC memory controller; accurately verify the logic functions of memory chips; and precisely and efficiently acquire the electrical performance output of the device under given stimulus conditions. It can generate excitation signals of common waveforms (square wave, triangle wave, sine wave, cosine wave) with frequencies from 0 to 200 MHz, and can perform data acquisition with high sampling accuracy (the ADC used in the test system must be at least 12-bit). It can also achieve simultaneous acquisition of multiple output data (at least 4 to 8 ADCs are required) and meet the requirements of multi-site test mode.

[0060] Therefore, only a test system that meets the above-mentioned functional characteristics can basically realize the functional verification and data acquisition of various types of memory chips, and only in this way can the test data and logical function judgment results be convincing.

[0061] The technical problem to be solved by this invention is: to design a memory chip that is compatible with different types, models, and package types, and can accurately verify the logic function of the memory chip. Through the FSMC dedicated memory controller, it can efficiently manage memory such as NORFLASH, NANDFLASH, SRAM, serial EEPROM, and SPI serial FLASH. It can generate excitation signals of common waveforms (square wave, triangle wave, sine wave, cosine wave) with a frequency of 0-200MHz. It can accurately and efficiently acquire the electrical performance parameters (including VOH, VOL, IOH, IOL, VIH, VIL, IIH, IIL, tPLH, tCE, tOE, tACC, etc.) output by the device under given excitation conditions. Furthermore, it can match memory chips with different test conditions and test accuracies by connecting an external source table. It can acquire data with high sampling accuracy (the ADC used in this system has a sampling accuracy of 16 bits). It can realize the simultaneous acquisition of multiple output data (this system uses 8 ADCs to acquire 8 data simultaneously). It can meet the multi-site test mode and support the simultaneous testing of 4 memory chips.

[0062] Combination Figure 1 As shown in the figure, a memory function verification and data acquisition system disclosed in an embodiment of the present invention includes a test motherboard, a test daughterboard, a host computer, external instruments, and a power supply system. The test motherboard is the motherboard of the memory function verification and data acquisition system. The test daughterboard includes the chip under test and its associated peripheral circuits. The power supply system can be a power adapter, DC power supply, etc. The external instruments can be a signal generator, oscilloscope, spectrum analyzer, network vector analyzer, digital multimeter, etc.

[0063] The host computer is electrically connected to the test motherboard, and the test motherboard is also electrically connected to the test daughterboard and external instruments. The test motherboard includes interconnected core control circuits, relay control interface circuits, memory control circuits, ADC sampling circuits, arbitrary wave generation circuits, power conversion circuits, storage circuits, crystal oscillator circuits, filtering circuits, communication circuits, reset circuits, and power conversion circuits. The test daughterboard includes the device under test (DUT) and peripheral power supply and signal circuits for performing high and low temperature tests on the DUT. The host computer is used to send control commands to the test motherboard, receive test data, process test data, query DUT information, and set parameters. The external instruments are used to perform functional tests on the DUT and capture AC / DC parameters. The power supply system is used to provide power to the test motherboard and the test daughterboard.

[0064] In some alternative embodiments, combined with Figure 2 The following describes the test motherboard, a core component of the system:

[0065] The test motherboard includes: core control circuit, FSMC memory control circuit, relay control circuit, arbitrary wave generation circuit, ADC sampling circuit, power conversion circuit, crystal oscillator circuit, filter circuit, storage circuit, RS485 communication circuit, reset circuit, etc.

[0066] For the core control circuit, the STM32F407IGT6 is used as the main control chip. This chip integrates a variable static memory controller (FSMC) and a Thumb-2 high-density instruction set. By setting special function registers, the FSMC can issue corresponding data / address / control signal types to match the signal speed according to different external memory types. This allows the system to not only utilize various types and speeds of external static memory, but also to simultaneously expand with multiple different types of static memory without adding external components, greatly enhancing the system's compatibility and flexibility. In addition, the core control circuit also performs data acquisition and processing, protocol conversion, single or multiple sets of I / O port high / low level toggling output (toggling frequency not exceeding 10Hz), and management and control of various peripherals.

[0067] This system optimizes the scheduling of memory chips through the FSMC controller. By reading the chip ID, it can automatically match test algorithms for different memory chip models, eliminating the workload of writing level, timing, pattern, and testflow code required in traditional ATE-based chip test development, thus greatly improving the system's development efficiency. Furthermore, addressing the issue of long sector erase and chip erase test times in traditional ATE-based systems, this system's internal test algorithm integrates a MATCH function. By real-time monitoring of the chip's BUSY output signal, it promptly controls the erase operation, thereby saving additional chip erase time and significantly enhancing the system's testing efficiency.

[0068] The relay control interface circuit is divided into two parts: an input signal relay control circuit and an output signal relay control circuit. The input relay control circuit is mainly used to control the selection of input excitation signals, which include three types: PPMU (external high-precision power supply), IO drive signals, and arbitrary wave generation signals. The core control algorithm can flexibly select these three excitation signals according to the different frequency and precision excitation requirements of the devices. The high-precision PPMU can provide excitation signals from -15V to 15V and 0 to 5A. This system can program the external high-precision PPMU via the VISA protocol, setting parameters such as the range and current limit of the excitation signal. The IO drive signal can provide high-level and low-level drive signals, and can be used as a backup drive source when an external PPMU excitation is unavailable. The arbitrary wave generation signal can provide common excitation signals such as square waves, triangle waves, sine waves, cosine waves, and sawtooth waves to meet the driving requirements of different device models, with an output voltage coverage of 0 to 5V and a current coverage of 0 to 1A.

[0069] The output signal relay control circuit is mainly used to select the test source for the output signal of the test chip. The output signal test sources include a high-precision PPMU, a high-precision AD sampling circuit, and an external high-performance oscilloscope. The high-precision PPMU can test DC parameters such as VIL, VIH, VOH, and VOL of the chip under test. Parameters of the high-precision PPMU can also be set via the VISA protocol on the host computer interface. The high-precision AD sampling circuit uses a 16-bit precision AD7606 chip, which can simultaneously acquire data from 8 channels, greatly improving sampling efficiency. It communicates with the main control chip via the SPI protocol. The external high-performance oscilloscope mainly complements the first two test sources, primarily targeting AC parameter testing. It can capture AC parameters such as the chip select enable to data output validity time tCE, the output enable valid to data output validity time tOE, and the address setup time tACC. This system integrates a high-precision external source meter, which can meet the testing accuracy requirements of various memory chips. It solves the problem that traditional ATE test equipment cannot test high-precision AC and DC parameters, greatly enhancing the system's flexibility. According to the different capacities of the memory chips under test, the corresponding excitation signals and the number of test resource channels can be flexibly expanded, greatly enhancing the system's scalability.

[0070] For arbitrary wave generation circuits, since the input excitation requirements of DUTs vary, conventional memory input excitation includes: drive high, drive low, etc., and there are high requirements for the test frequency of the excitation signal. Typically, the input excitation frequency of high-speed memory can reach about 150MHz. Therefore, a signal generation circuit needs to be designed to meet the excitation requirements of different frequencies. This circuit can generate 4 signals of different frequencies simultaneously, and the maximum generated signal frequency can reach about 200MHz, which is sufficient to cover the input excitation requirements of most devices. This arbitrary wave generation circuit is controlled by FPGA, and the generated signal has high accuracy.

[0071] In some optional embodiments, the storage circuit, which uses an EEPROM chip, is used to store data that is not lost when power is off, such as motherboard address information, key threshold parameters, and important extracted data.

[0072] The communication circuit is selected as an RS485 communication circuit. This part of the circuit is used to provide a hardware interface for communication with the host computer software. It uses the half-duplex mode of RS485, and only two communication lines (A, B) are needed to complete data communication.

[0073] A reset circuit is essential to ensure stable and reliable system operation. Therefore, a button with one end connected to ground and the main controller's BOOTO pin are designed to restore the system to its initial, predetermined state when a bug occurs, thereby enhancing the system's fault tolerance.

[0074] The power conversion circuit, as the power source of the entire system, directly affects the stability of the system operation due to the reliability of its power supply. Since the main control chip of the core control circuit operates at a voltage of 3.3V, and the power supply voltage required by different types of DUTs ranges from 3.3V to 12V, a 12V-5V and 5V-3.3V power conversion circuit is designed to supply power to the motherboard and daughterboard.

[0075] Further integration Figure 2 The test board topology diagram shown illustrates the connection relationships of various circuits within the test board. In the diagram, the connections in the output relay control circuit indicate the flow direction of the input signal, and the connections in the output relay control circuit indicate the flow direction of the output signal. The flow trajectory of the input signal, i.e., the excitation signal of the chip under test, is as follows: Input excitation signal (IO drive signal, PPMU excitation signal, FPGA arbitrary wave signal) -> Input signal selection circuit -> Input interface -> Chip under test. The flow trajectory of the output signal, i.e., the output signal of the chip under test, is as follows: Chip under test output signal -> Output interface -> Output test source selection circuit -> Test source (AD sampling circuit, PPMU, external high-performance oscilloscope). The I / O signal mainly includes two parts: the excitation signal used to drive the chip under test and the control signal used to control the relay's on / off state. The excitation signal driving the chip under test is mainly used to drive high and low level signals to the memory chip. For the control signal used to control the relay's on / off state, due to the limited driving capability of the I / O, it cannot directly drive the relay. Therefore, a relay driver chip ULN2803A is needed, with each driver chip capable of driving eight relays. The motherboard is equipped with multiple USB interfaces for data communication with external source meters (high-precision PPMU, high-performance oscilloscope). The core CPU, based on the VISA protocol, can perform real-time control of external source meters. The motherboard also features a TTL interface for data communication with an arbitrary wave generator. The core CPU can use this interface to issue control commands to the arbitrary wave generator to generate different types and frequencies of excitation signals, including high and low level signals, sine waves, cosine waves, sawtooth waves, etc., with a maximum frequency of up to 200MHz. Furthermore, the core CPU can adjust the phase and amplitude of the input signal according to the requirements of different devices under test.

[0076] In some optional embodiments, the test sub-board is configured to be designed according to the package and model of the device under test (DUT). Devices from the same manufacturer, series, and package but with different capacities can use the same test sub-board. Overall, the circuit design of the memory chip test sub-board is relatively simple, specifically including: the DUT and the peripheral power supply and signal circuits for its normal operation. Furthermore, addressing the issue of traditional ATE test equipment being inconvenient for high and low temperature testing, the test sub-board also reserves a dedicated interface for high and low temperature testing to meet the high and low temperature testing requirements of memory chips. The power supply and signal lines of the DUT can be led out using dedicated custom connecting wires (with extremely strong tensile strength, high and low temperature resistance, and an operating temperature range of -65℃ to 150℃) to facilitate high and low temperature testing in a high and low temperature chamber.

[0077] In some alternative embodiments, combined with Figure 3 The diagram shows the interface of the host computer. The host computer is configured such that its software, deployed on an industrial control computer, communicates with the test motherboard via an RS485 line. The host computer software includes:

[0078] 1) Send control commands (automatic test commands, single-step test commands) to the test motherboard;

[0079] 2) Receive DUT test data (including functional and AC / DC test data) collected by the test motherboard;

[0080] 3) Process, judge, output and display the logical judgment results of the received test data;

[0081] 4) Query the test motherboard address number and the ID information of the memory chip under test;

[0082] 5) Enable parameter settings, such as AC / DC parameter card limit settings and external source meter range settings;

[0083] 6) In addition, it should also have functions such as single-time acquisition of test sub-board data, timed acquisition of test sub-board data, polling acquisition of test sub-board data, and export of test data.

[0084] In some optional embodiments, the power supply system is configured such that the external power supply of this system adopts 220V AC mains power. Since the power supply voltage requirements of the test motherboard and test daughterboard are in the range of DC 3.3V-12V, this system adopts a high-performance, high-reliability switching power supply (AC220V~DC12V) to provide 12V DC power to the test motherboard. The test motherboard then provides 5V and 3.3V DC power to the core CPU, internal module circuits and external test daughterboard through a power conversion circuit.

[0085] In some optional embodiments, the external instruments are configured to be used for auxiliary testing of the DUT during AC / DC parameter testing and partial functional verification. These instruments may include high-precision DC power supplies (PPMUs), high-performance oscilloscopes, 7.5-digit multimeters, logic analyzers, and network vector analyzers. Therefore, this system specifically reserves a data interface for communication with external instruments. The core CPU of the test motherboard can achieve precise control of these external instruments based on the VISA protocol to realize functional testing and AC / DC parameter acquisition of the device under test.

[0086] The overall operating principle of the memory function verification and data acquisition system provided in the embodiments of the present invention is as follows:

[0087] Before running the entire testing system, firstly, connect the memory chip test daughterboard to the test motherboard and turn on the system switch, waiting for the device self-test to complete. Next, configure the serial port information of the host computer software: select the corresponding serial port number COMX ("X" represents the serial port number), baud rate = 9600, stop bits = 1, data bits = 8, and click Connect to establish a communication connection between the host computer system and the testing system. Then, in the host computer interface, set the limit range of AC and DC parameters according to the device manual (including DC parameters such as VIL, VIH, VOL, VOH, and AC parameters such as tCE, tOE, tACC). For DC parameter testing, there are two main methods: voltage-current measurement and current-voltage measurement. The voltage value, current value, and acquisition time can be set in the host computer interface. For functional test items, if full address testing is not required, the sector address to be tested can also be set to meet personalized testing needs. Furthermore, select the automatic test items according to the test requirements. By default, it is a full-process test, namely Continuity connectivity test -> Read memory ID -> Functional test -> DC parameter test -> AC parameter test -> Memory erase -> End. This system can be adjusted according to different test requirements. That is, if only functional testing is required, select connectivity test, read memory ID, and functional test in the test process settings on the host computer interface. Next, set the input stimulus form of the chip under test. By default, the functional test uses the internal FSMC interface and can be completed without any additional external input stimulus. When special external stimulus is required, for example, most memory chips now have a high-voltage erase function. To verify this function, a 12V'VHH needs to be applied to the Vpp / WP# pin. In this case, an external PPMU can be set as the input stimulus source for this pin. After setting the parameters, click the automatic test button, and the system will start automatically executing the test process.

[0088] Once the test begins, data uploaded to the host computer software is processed and decoded according to the specified data decoding protocol (MODBUS protocol). The test data is then displayed. Due to the setting of thresholds for key parameters, a "PASS" flag appears if the collected data is within the threshold range, and a "FAIL" flag appears if the test data does not reach the threshold. This completes the judgment of the device's logic function. For example, for the write all-zero test of a NORFLASH memory chip, if the read low-level signal is within the VOL threshold range, a "PASS" flag will be output; otherwise, a "FAIL" flag will appear. Similarly, the same judgment mechanism and processing mode are used for testing other parameters. Therefore, this system can effectively complete the functional verification of the device under test and AC / DC parameter testing, with a test accuracy of up to four decimal places. Furthermore, all test data can be displayed in real time as waveforms to analyze data fluctuations throughout the entire test cycle, which is more conducive to device performance analysis. All test data can be exported in a professional format as an Excel spreadsheet.

[0089] The memory function verification and data acquisition system provided in this invention can cover the application verification and data acquisition work of most types of memory. Moreover, it has accurate logic function judgment, efficient and accurate data acquisition, and the designed test system is simple to operate, has good test results, high test stability and reliability, and has very high engineering application value.

[0090] Combination Figure 4 As shown, based on the same inventive concept, corresponding to the memory function verification and data acquisition system of any of the above embodiments, the present invention also provides a memory function verification and data acquisition test method, including:

[0091] S1: Send the test operation instructions from the host computer to the core CPU of the test motherboard;

[0092] S2: In response to the core CPU, the test operation instructions in the host computer are sent to the optimization controller, high-precision PPMU and high-performance oscilloscope;

[0093] S3: Read the memory ID in response to receiving the output signal of the optimization controller;

[0094] S4: Perform DC parameter testing in response to receiving the output signal of the high-precision PPMU;

[0095] S5: Performs AC parameter tests in response to receiving the output signal from the high-performance oscilloscope;

[0096] S6: Upload the test result data to the host computer.

[0097] Further integration Figure 5 As shown, the detailed workflow is as follows: The host computer sends test commands to the core CPU of the test motherboard via the RS485 bus. After receiving the test commands, the motherboard starts the test process. The core CPU calls the FSMC optimization controller to perform a series of automatic test operations on the memory, including reading the memory ID, reading all 1s (if reading all 1s fails, the chip will be erased and read again), writing all 0s, reading all 0s, chip erasure, writing to the chessboard, reading the chessboard, and sector erasure. When the test process reaches the DC parameter test, the CPU will start the external high-precision PPMU control to achieve DC parameter testing such as VIL, VIH, VOH, and VOL. When it reaches the AC parameter test, the CPU will start the external high-performance oscilloscope control to achieve AC parameter capture such as tCE, tOE, and tACC. After the entire automatic test is completed, the core CPU uploads the test result data to the host computer interface. During the entire automatic test process, when a certain test fails, the test algorithm will immediately jump out of the test process and promptly feed back the failure data to the host computer interface. The above is the automatic testing process. The host computer can also perform single-step testing on the chip under test according to different testing requirements.

[0098] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides an electronic device capable of operating a memory function verification and data acquisition system including any of the above embodiments.

[0099] The electronic device further includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the test method described in any of the above embodiments.

[0100] Figure 6 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0101] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0102] The memory 1020 can be implemented in the form of ROM (Read-Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0103] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0104] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0105] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0106] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0107] The electronic devices described above are used to implement the corresponding charging pile fault prediction methods in any of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0108] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0109] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result.

[0110] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0111] Furthermore, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the apparatus may be shown in block diagram form. This is to prevent the embodiments of this disclosure from being difficult to understand, and it also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully within the understanding of those skilled in the art). While specific details (e.g., circuitry) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0112] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0113] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory function verification and data acquisition system, characterized in that, include: Test motherboard, test daughterboard, host computer, external instruments and power supply system; The host computer is electrically connected to the test motherboard, and the test motherboard is also electrically connected to the test daughterboard and external instruments. The test motherboard includes interconnected core control circuits, relay control interface circuits, memory control circuits, ADC sampling circuits, arbitrary wave generation circuits, power conversion circuits, storage circuits, crystal oscillator circuits, filter circuits, communication circuits, and reset circuits. The test sub-board includes the device under test and peripheral power supply and signal circuits, and is used to perform high and low temperature tests on the chip under test; The host computer is used to send control commands to the test motherboard, receive test data, process test data, query the information under test, and set parameters. The external instruments are used to perform functional tests on the device under test and to acquire AC / DC parameters. The power supply system is used to provide electrical energy to the test motherboard and the test daughterboard; The core control circuit of the test motherboard includes a main control chip, which includes a variable static memory controller. The variable static storage controller is used to issue corresponding data / address / control signal types according to different external memory types to match the signal speed.

2. The memory function verification and data acquisition system according to claim 1, characterized in that, The main control chip also includes a high-density instruction set; The core control circuit is also used to complete data acquisition and processing, protocol conversion, single or multiple sets of high and low level toggling output, and manage and control peripherals.

3. The memory function verification and data acquisition system according to claim 1, characterized in that, The relay control interface circuit of the test motherboard includes: an input signal relay control circuit and an output signal relay control circuit; The input signal relay control circuit is used to control the selection of the input excitation signal, which includes an external high-precision power supply, an IO drive signal, and an arbitrary wave generation signal. The IO drive signal is used to provide high-level and low-level drive signals and serves as a backup drive source. The arbitrary wave generation signal provides excitation signals for square waves, triangular waves, sine waves, cosine waves, and sawtooth waves. The output signal relay control circuit is used to select the test source for the output signal of the test chip. The output signal test source includes a high-precision PPMU, a high-precision AD sampling circuit, and an external high-performance oscilloscope. The DC parameters of the high-precision PPMU are set via the host computer. The high-precision AD sampling circuit is used to acquire multiple signal data and communicate with the main control chip; The external high-performance oscilloscope is used to capture and test AC parameters, including chip select enable to data output validity time, output enable to data output validity time, and address setup time.

4. The memory function verification and data acquisition system according to claim 1, characterized in that, The arbitrary wave generation circuit of the test motherboard can simultaneously generate multiple signals of different frequencies, generating high-precision signals. The communication circuit of the test motherboard is used to connect with the host computer and communicate with the host computer for data. The storage circuit of the test motherboard is used to save data that is not lost when power is off; wherein, the data that is not lost when power is off includes motherboard address information data, key threshold parameters, and extracted data; One end of the reset circuit of the test motherboard is connected to the ground button and the main control pin, which can be used to restore the initial state; The power conversion circuit of the test motherboard is used to convert electrical energy to power the test motherboard and the control daughterboard.

5. The memory function verification and data acquisition system according to claim 1, characterized in that, The test subboard has an interface for high and low temperature testing. The power supply and signal lines of the chip under test are led out through wires so that high and low temperature tests can be carried out in the high and low temperature chamber.

6. The memory function verification and data acquisition system according to claim 1, characterized in that, The host computer communicates with the test motherboard via a connection cable, and the host computer is used for: Send control commands to the test motherboard, the control commands including automatic test commands and single-step test commands; Receive test data from the test equipment collected by the test motherboard, the test equipment test data including functional and AC / DC test data; Process the received test data, make judgments, output the logical judgment results, and display them; Query the test motherboard address number and the ID information of the memory chip under test; Enables parameter settings, including AC / DC parameter card limit settings and external source meter range settings; It can also be used for single-time acquisition of test sub-board data, timed acquisition of test sub-board data, polling acquisition of test sub-board data, and export of test data.

7. The memory function verification and data acquisition system according to claim 1, characterized in that, The power supply system provides DC power to the test motherboard through a switching power supply, and the test motherboard then provides DC power to the core CPU, internal module circuits and external test daughterboards through a power conversion circuit.

8. The memory function verification and data acquisition system according to claim 1, characterized in that, The external instrument is used to connect with the test equipment when performing AC / DC parameter testing and functional verification, and to receive control signals from the test motherboard to realize functional testing of the device under test and capture AC / DC parameters.

9. A method for verifying memory function and testing data acquisition, characterized in that, Applied to the system according to any one of claims 1-8, the method comprises: The test operation instructions in the host computer are sent to the core CPU of the test motherboard. In response to the core CPU, test operation commands from the host computer are sent to the optimization controller, high-precision PPMU, and high-performance oscilloscope; Read the memory ID in response to receiving the output signal from the optimization controller; Upon receiving the output signal from the high-precision PPMU, a DC parameter test is performed. Upon receiving the output signal from the high-performance oscilloscope, an AC parameter test is performed. The test results data are uploaded to the host computer.

10. An electronic device, characterized in that, It is capable of operating the memory function verification and data acquisition system described in any one of claims 1-8; The electronic device includes a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor executes the program to implement the test method as described in claim 9.

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