A silicon carbide diode and a method of manufacturing the same

Abstract

The application discloses a manufacturing method of a silicon carbide diode, which comprises the following steps: removing a fourth oxide layer in a third set area by adopting a photoetching and etching process, taking the fourth oxide layer as a mask layer, and forming a second groove in a silicon carbide epitaxial layer by adopting a dry etching process; the third set area is located in a cell area of the device and does not coincide with the first set area, that is, the second groove is formed outside the first set area in the cell area; removing the fourth oxide layer by adopting a wet etching process; growing a fifth oxide layer, removing the fifth oxide layer in the cell area by adopting a photoetching and etching process; growing metal titanium by adopting a physical vapor deposition process, and forming a Schottky barrier between the metal titanium and a surface of the silicon carbide epitaxial layer in the cell area by adopting an alloying process. The silicon carbide diode and the manufacturing method thereof have the advantages of improving a reverse withstand voltage of the device and reducing a forward voltage drop.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip manufacturing processes, and more particularly to a silicon carbide diode and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC), a typical representative of third-generation semiconductors, possesses a wide bandgap, high breakdown voltage, high thermal conductivity, and high electron saturation velocity. Therefore, power electronic devices fabricated from SiC exhibit higher withstand voltage, current density, and operating frequency. They can operate in high-frequency and high-temperature environments, demonstrating high reliability and suitability for harsh working conditions. As a third-generation power electronic device, SiC devices have become a crucial development direction in power electronics technology, with significant application prospects in both military and civilian fields.

[0003] A junction barrier Schottky diode is a special type of semiconductor device whose structure differs from that of a regular diode. Its name contains three key terms: junction barrier Schottky, diode, and we will explain them one by one below.

[0004] First, there's the junction barrier, which refers to the potential barrier formed at the interface between two semiconductor materials due to their different band structures. This barrier hinders the flow of electrons. Therefore, under forward bias, electrons need to overcome this barrier to pass through the diode, while under reverse bias, the barrier becomes even stronger, further preventing the flow of electrons.

[0005] Next is the Schottky junction, which refers to a metal-semiconductor junction formed by directly contacting a metal with a semiconductor material. This junction is characterized by extremely low reverse leakage current, making it suitable for fabricating high-speed, high-frequency devices.

[0006] Finally, there's the diode, a device composed of two semiconductor materials that exhibits unidirectional conductivity. When forward biased, electrons can pass through the diode, while when reverse biased, electrons cannot.

[0007] A junction barrier Schottky diode is a device that combines these three concepts. Its structure consists of a metal, an n-type semiconductor, and a p-type semiconductor. Under forward bias, electrons enter the metal from the n-type semiconductor, then enter the p-type semiconductor, and finally flow out. Under reverse bias, due to the presence of the metal-semiconductor junction, the reverse leakage current is very small, so it can be used to make high-speed, high-frequency devices.

[0008] Junction barrier Schottky diodes have many advantages, such as low reverse leakage current, fast response speed, and low noise. Therefore, they are widely used in radio frequency, microwave, and optoelectronic fields. However, they also have some disadvantages, such as poor temperature stability and leakage current increasing with temperature. Therefore, the selection should be based on specific circumstances in practical applications.

[0009] Silicon carbide diodes are a type of silicon carbide device. Among silicon carbide diodes, Schottky barrier diodes have the significant advantage of fast switching speed, are majority carrier devices, and have no reverse recovery time. However, under high voltage, the Schottky barrier degrades, resulting in large reverse leakage current and an inability to achieve high-voltage withstand characteristics. Compared to Schottky barrier diodes, PiN devices have higher voltage withstand capability, but longer reverse recovery time and larger forward voltage drop. Junction barrier Schottky diodes (JBS) combine the Schottky barrier and PiN structures, integrating the advantages of both, including high voltage withstand capability, low leakage current, low forward voltage drop, and fast reverse recovery time.

[0010] Typically, hybrid silicon carbide diodes (MPS) are made by adding a photolithography layer to the traditional jB diode, thereby separating the ohmic and Schottky metals for fabrication, reducing ohmic contact resistance, and improving forward surge capability. Further improvements are needed to enhance the forward surge and reverse withstand voltage capabilities of these devices. Summary of the Invention

[0011] This invention provides a silicon carbide diode and its manufacturing method, which solves the problems existing in the prior art and has the advantages of improving the reverse withstand voltage, reducing the forward voltage drop, and increasing the power density of the device.

[0012] A method for manufacturing a silicon carbide diode according to an embodiment of this application includes the following steps:

[0013] Substrate preparation: N-type silicon carbide substrate, 350 μm thick, doping concentration >1e19 / cm² 3 ;

[0014] Epitaxial growth: An N-type silicon carbide epitaxial layer was grown on an N-type silicon carbide substrate to a thickness of 10 ± 2 μm and a doping concentration of 1e15–1e16 / cm². 3 ;

[0015] A composite layer consisting of a first oxide layer, polycrystalline silicon, and a second oxide layer is grown on the surface of an N-type silicon carbide epitaxial layer.

[0016] The first oxide layer is a thermal oxide layer with a thickness of 30±5nm, and the thickness of the polycrystalline silicon is 100±20nm.

[0017] The second oxide layer is an oxide layer grown by chemical vapor deposition process, with a thickness of 2000±200nm;

[0018] The second oxide layer is densified by a high-temperature annealing process, with a process temperature of 850-1000 degrees Celsius and a process time of 30-60 minutes;

[0019] The second oxide layer and polysilicon in the first designated area are removed by photolithography and etching processes, and then the photoresist is removed. Using the second oxide layer and polysilicon as a masking layer, the first P+ doped region is formed by multiple ion implantations under high temperature environment. The multiple implantations are 3 to 5 times, and the implanted dopant is aluminum.

[0020] A first P+ doped region with a depth of 1.5±0.2 μm is formed in the silicon carbide epitaxial layer;

[0021] The first P+ doped region formed in the first defined region includes several first P+ doped regions in the cell region and several first P+ doped regions in the guard ring region;

[0022] The first oxide layer, polysilicon, and second oxide layer are removed by wet etching, and a composite layer consisting of a third oxide layer and nickel is grown by deposition.

[0023] Photolithography and etching processes are used to remove the nickel and third oxide layer in the second designated area, and to remove the photoresist.

[0024] Using the nickel and third oxide layer as masking layers, a first trench is formed in the silicon carbide epitaxial layer in the second defined region using a dry etching process; the second defined region is located only in the cell region and corresponds one-to-one with the first defined region in the cell region, and its size is smaller than the first defined region; in the cell region of the device, the first trenches formed are all located in the first P+ doped region and their size is smaller than the first P+ doped region.

[0025] The nickel is removed using a wet etching process, leaving the third oxide layer intact.

[0026] Using an ion implantation process, a second P+ doped region with greater depth and wider lateral dimensions is formed below the first P+ doped region at the bottom of the first trench.

[0027] The third oxide layer is removed, a carbon film is grown on the surface, and high-temperature annealing is performed to activate the dopants in the first P+ doped region and the second P+ doped region, and then the carbon film is removed.

[0028] Metallic nickel is grown to fill the first trench;

[0029] The nickel metal outside the first trench is removed by CMP process, while the nickel metal inside the first trench is retained; an alloying process is used to make the nickel metal in the first trench form an ohmic contact with the first P+ doped region.

[0030] Preferably, the above steps are followed by the following steps:

[0031] A fourth oxide layer is deposited, and the fourth oxide layer in the third defined region is removed by photolithography and etching processes. Using the fourth oxide layer as a masking layer, a second trench is formed in the silicon carbide epitaxial layer by dry etching process. The third defined region is located in the cell region of the device and does not overlap with the first defined region mentioned above. That is, the second trench is formed outside the first defined region of the cell region.

[0032] The fourth oxide layer is removed using a wet etching process;

[0033] A fifth oxide layer is grown, and the fifth oxide layer in the cell region is removed using photolithography and etching processes.

[0034] Physical vapor deposition is used to grow metallic titanium, and an alloying process is used to form a Schottky barrier between the metallic titanium and the surface of the silicon carbide epitaxial layer in the cell region.

[0035] Fabricate the front metal layer, specifically an aluminum layer of 3.0±0.3um;

[0036] The passivation layer can be a composite layer consisting of an oxide layer, silicon nitride, and polyimide.

[0037] Backside grinding and backside metallization.

[0038] Preferably, the above steps include:

[0039] The high-temperature environment is 500±30 degrees Celsius. The thickness of the third oxide layer is 500±100nm, the thickness of the nickel is 100±10nm, the width of the first trench is 1±0.1um, the depth of the first trench is 1±0.1um, the width of the second trench is 2±0.2um, and the depth of the first trench is 0.5±0.1um.

[0040] A silicon carbide diode manufactured using the method described above includes a silicon carbide epitaxial layer and a Schottky barrier, wherein the Schottky barrier is formed on the surface of the silicon carbide epitaxial layer.

[0041] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0042] This invention proposes a silicon carbide diode and its manufacturing method. Based on the traditional silicon carbide hybrid diode (MPS), this invention innovates and improves the structure and process to enhance the reverse breakdown voltage, reduce the forward voltage drop, and increase the power density of the device.

[0043] The differences and advantages of this invention compared to the traditional silicon carbide hybrid diode MPS are as follows:

[0044] In traditional MPS structures, the P+ ohmic contact is only present on the upper surface. However, the P+ ohmic contact of this invention is a groove-shaped structure, with ohmic contact between the metal and P+ on three sides, resulting in a larger contact area. This enhances the device's forward surge capability, and the ohmic metal can act as a field plate to improve the device's reverse withstand voltage when the device is subjected to reverse voltage.

[0045] 2. In the traditional MPS structure, the N-Schottky contact only has a Schottky barrier on the upper surface (Schottky contact), while the N-Schottky contact of the present invention is a groove structure, with Schottky barriers on three sides of the metal and N-. The area of ​​the Schottky barrier is larger, so the forward voltage drop of the device is smaller, the reverse recovery time is shorter, or the chip area required to achieve the same forward voltage drop as the traditional MPS is smaller.

[0046] Third, the present invention injects P+ at the bottom of the trench of the ohmic contact to form a potential barrier, which can effectively avoid the premature breakdown of the device caused by the concentration of electric field at the bottom of the trench.

[0047] This invention employs a double-trench structure (both the ohmic contact region and the Schottky contact region are located within the trench), and injects P+ at the bottom of the ohmic contact trench to form a potential barrier, thus forming a hybrid diode with a double-trench and double-barrier structure. Compared with hybrid diodes with traditional structures, it has a higher reverse breakdown voltage, a lower forward voltage drop, and a higher current density. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figures 1-11 This is a schematic flowchart of a silicon carbide diode manufacturing method according to the present invention;

[0050] Figures 12-14 This is a schematic diagram comparing the present invention with the prior art. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0053] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0054] The first embodiment of the present invention provides a method for manufacturing a silicon carbide diode, comprising the following steps:

[0055] 1. Substrate preparation: N-type silicon carbide substrate, 350 μm thick, doping concentration >1e19 / cm² 3 .

[0056] 2. Epitaxial Growth: An N-type silicon carbide epitaxial layer is grown on an N-type silicon carbide substrate to a thickness of 10±2 μm and a doping concentration of 1e15~1e16 / cm. 3 .

[0057] 3. A composite layer consisting of a first oxide layer (Pad OX), polysilicon (Poly), and a second oxide layer (LPTEOS) is grown on the surface of an N-type silicon carbide epitaxial layer.

[0058] The first oxide layer is a thermal oxide layer with a thickness of 30±5nm.

[0059] The thickness of the polycrystalline silicon is 100±20nm.

[0060] The second oxide layer is an oxide layer grown by chemical vapor deposition, with a thickness of 2000±200nm.

[0061] Then, the second oxide layer is densified by a high-temperature annealing process at a temperature of 850–1000 degrees Celsius for 30–60 minutes. After densification, the second oxide layer has a more stable etching rate.

[0062] 4. Use photolithography and etching processes to remove the second oxide layer and polysilicon in the first designated area, and then remove the photoresist.

[0063] 5. Using the second oxide layer and polysilicon as masking layers, the first P+ doped region is formed by multiple ion implantations under high temperature conditions.

[0064] Outside the first designated region, the area will not be implanted in this step due to the obstruction of the second oxide layer and polysilicon. In the first designated region, ions penetrate the first oxide layer (which is relatively thin and can penetrate) and enter the silicon carbide epitaxial layer to form the first P+ doped region.

[0065] The high-temperature environment is 500±30 degrees Celsius.

[0066] The multiple implantations refer to 3 to 5 implantations, with aluminum as the implanted dopant. For example:

[0067] The initial injection energy was 30 kiloelectron volts, and the dose was 5e¹⁵ / cm². 2 .

[0068] The second injection energy was 100 kiloelectron volts, and the dose was 5e¹³ / cm². 2 .

[0069] The third injection energy was 250 kiloelectron volts, and the dose was 5e13 / cm. 2 .

[0070] The fourth injection energy was 350 keV, and the dose was 5e14 / cm. 2 .

[0071] The fifth injection energy was 500 keV, and the dose was 5e15 / cm. 2 .

[0072] A first P+ doped region with a depth of 1.5±0.2um is formed in the silicon carbide epitaxial layer.

[0073] Please see Figure 1 The first P+ doped region formed in the first designated region includes several first P+ doped regions in the cell region (marked with "P+" in the schematic diagram) and several first P+ doped regions in the guard ring region (marked with r1, r2...rn in the schematic diagram, a total of n P+ rings; only three P+ rings are shown in the schematic diagram, which does not mean that there are only three rings).

[0074] 6. Remove the first oxide layer, polysilicon, and second oxide layer, specifically by using a wet etching process.

[0075] 7. A composite layer consisting of a third oxide layer (LPTEOS) and nickel is grown using a deposition process.

[0076] The thickness of the third oxide layer is 500±100nm, and the thickness of the nickel is 100±10nm.

[0077] 8. Use photolithography and etching processes to remove the nickel and third oxide layer in the second designated area, and then remove the photoresist.

[0078] 9. Using the nickel and the third oxide layer as masking layers, a first trench is formed in the silicon carbide epitaxial layer in the second designated region using a dry etching process.

[0079] The second designated region is located only in the cell region and corresponds one-to-one with the first designated region in the cell region. Its size is smaller than the first designated region. That is, in the cell region of the device, the first trenches formed in this step are all located in the first P+ doped region and their size is smaller than the first P+ doped region.

[0080] Please see Figure 2 The width of the first trench is 1±0.1um and the depth of the first trench is 1±0.1um.

[0081] Nickel, as a masking layer, has a higher etching selectivity in this dry etching process (i.e., the etching rate of nickel is very low when etching silicon carbide).

[0082] 10. Remove the nickel, specifically by wet etching; retain the third oxide layer.

[0083] 11. Using ion implantation technology, a second P+ doped region with greater depth and wider lateral dimensions is formed below the first P+ doped region at the bottom of the first trench.

[0084] To achieve the desired lateral dimensions, this injection step employs an angled injection method with an angle of 30±5°.

[0085] The dopant in the ion implantation process is aluminum, the implantation energy is 40 ± 10 kEV, and the implantation dose is 5e¹⁵ to 8e¹⁵ / cm². 2 The depth of the second P+ doped region formed below the first P+ doped region is approximately 0.5 ± 0.1 μm.

[0086] Please see Figure 3 The second P+ doped region can prevent premature breakdown caused by the electric field concentration at the bottom of the first trench when the device is subjected to reverse voltage.

[0087] 12. Remove the third oxide layer; grow a carbon film on the surface, then anneal at high temperature to activate the dopants in the first and second P+ doped regions (process temperature: 1650±50 degrees Celsius, process time: 30±10 min), then remove the carbon film (see [link to documentation]). Figure 4 ).

[0088] 13. Grow metallic nickel to fill the first trench (see [link]). Figure 5 ).

[0089] 14. The nickel metal outside the first trench is removed using a CMP process, retaining the nickel metal within the first trench; then, an alloying process is used to form an ohmic contact between the nickel metal in the first trench and the first P+ doped region. The alloying process is performed at a temperature of 650±50 degrees Celsius for a time of 20±10 minutes (see [link to relevant documentation]). Figure 6 ).

[0090] 15. Deposit a fourth oxide layer (LPTEOS), then remove the fourth oxide layer in the third designated area using photolithography and etching processes. Then, using the fourth oxide layer as a masking layer, form a second trench in the silicon carbide epitaxial layer using a dry etching process. The width of the second trench is 2±0.2um, and the depth of the first trench is 0.5±0.1um.

[0091] The third defined region is located within the cell region of the device and does not overlap with the first defined region, meaning that the second trench is formed outside the first defined region of the cell region (see [link]). Figure 7 ).

[0092] 16. Remove the fourth oxide layer, specifically by using a wet etching process.

[0093] 17. Grow the fifth oxide layer, and then remove the fifth oxide layer in the cell region using photolithography and etching processes.

[0094] 18. A physical vapor deposition process is used to grow metallic titanium. Then, an alloying process is employed to form a Schottky barrier (Schottky contact) between the titanium and the surface of the silicon carbide epitaxial layer in the cell region (including the bottom and sides of the second trench). Please refer to [link to relevant documentation]. Figure 8 .

[0095] 19. The subsequent processes are relatively conventional and will not be described in detail.

[0096] Specifically, this includes: fabricating a front-side metal layer, which can be an aluminum layer of 3.0 ± 0.3 μm. Please refer to [link / reference]. Figure 9 .

[0097] To fabricate a passivation layer, it can specifically be a composite layer consisting of an oxide layer, silicon nitride, and polyimide. Please refer to [link / reference needed]. Figure 10 .

[0098] For backside grinding and backside metallization, please refer to [link / reference]. Figure 11 .

[0099] Please see Figure 11 The second embodiment of the present invention provides a silicon carbide diode, which is manufactured by the above-described method for manufacturing a silicon carbide diode, and includes a silicon carbide epitaxial layer and a Schottky barrier, wherein the Schottky barrier is formed on the surface of the silicon carbide epitaxial layer.

[0100] The differences and advantages of this invention compared to the traditional silicon carbide hybrid diode MPS are as follows:

[0101] I. In traditional MPS structures, the P+ ohmic contact is only present on the upper surface. However, the P+ ohmic contact of this invention is a groove-shaped structure, with ohmic contact between the metal and P+ on three sides, resulting in a larger contact area. This improves the device's forward surge capability, and when the device withstands reverse voltage, the ohmic metal acts as a field plate to enhance the device's reverse withstand voltage (see [link to relevant documentation]). Figure 12 ).

[0102] II. In traditional MPS structures, the N-Schottky contact only has a Schottky barrier on its upper surface (Schottky contact). However, the N-Schottky contact of this invention has a groove-shaped structure, with Schottky barriers on three sides for both the metal and N-. The area of ​​the Schottky barrier is larger, resulting in a smaller forward voltage drop, shorter reverse recovery time, or a smaller chip area required to achieve the same forward voltage drop as a traditional MPS. (See also...) Figure 13 In the schematic diagram, MO represents the ohmic contact metal, and MS represents the Schottky contact metal.

[0103] Third, this invention injects P+ ions at the bottom of the trench in the ohmic contact to form a potential barrier, which can effectively avoid premature device breakdown caused by electric field concentration at the bottom of the trench (see [link]). Figure 14 ).

[0104] In summary, this invention employs a double-trench structure (both the ohmic contact region and the Schottky contact region are located within the trench), and injects P+ at the bottom of the ohmic contact trench to form a potential barrier, thus forming a hybrid diode with a double-trench and double-barrier structure. Compared with hybrid diodes with traditional structures, it has a higher reverse breakdown voltage, a lower forward voltage drop, and a higher current density.

[0105] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0106] This invention proposes a silicon carbide diode and its manufacturing method. Based on the traditional silicon carbide hybrid diode (MPS), this invention innovates and improves the structure and process to enhance the reverse breakdown voltage, reduce the forward voltage drop, and increase the power density of the device.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a silicon carbide diode, characterized in that, Includes the following steps: Substrate preparation: N-type silicon carbide substrate, 350 μm thick, doping concentration >1e19 / cm² 3 ; Epitaxial growth: An N-type silicon carbide epitaxial layer was grown on an N-type silicon carbide substrate to a thickness of 10 ± 2 μm and a doping concentration of 1e15–1e16 / cm². 3 ; A composite layer consisting of a first oxide layer, polycrystalline silicon, and a second oxide layer is grown on the surface of an N-type silicon carbide epitaxial layer. The first oxide layer is a thermal oxide layer with a thickness of 30±5nm, and the thickness of the polycrystalline silicon is 100±20nm. The second oxide layer is an oxide layer grown by chemical vapor deposition process, with a thickness of 2000±200nm; The second oxide layer is densified by a high-temperature annealing process, with a process temperature of 850-1000 degrees Celsius and a process time of 30-60 minutes; The second oxide layer and polysilicon in the first designated area are removed by photolithography and etching processes, and then the photoresist is removed. Using the second oxide layer and polysilicon as a masking layer, the first P+ doped region is formed by multiple ion implantations under high temperature environment. The multiple implantations are 3 to 5 times, and the implanted dopant is aluminum. A first P+ doped region with a depth of 1.5±0.2 μm is formed in the silicon carbide epitaxial layer; The first P+ doped region formed in the first defined region includes several first P+ doped regions in the cell region and several first P+ doped regions in the guard ring region; The first oxide layer, polysilicon, and second oxide layer are removed by wet etching, and a composite layer consisting of a third oxide layer and nickel is grown by deposition. Photolithography and etching processes are used to remove the nickel and third oxide layer in the second designated area, and to remove the photoresist. Using the nickel and third oxide layer as masking layers, a first trench is formed in the silicon carbide epitaxial layer in the second defined region using a dry etching process; the second defined region is located only in the cell region and corresponds one-to-one with the first defined region in the cell region, and its size is smaller than the first defined region; in the cell region of the device, the first trenches formed are all located in the first P+ doped region and their size is smaller than the first P+ doped region. The nickel is removed using a wet etching process, leaving the third oxide layer intact. Using an ion implantation process, a second P+ doped region with greater depth and wider lateral dimensions is formed below the first P+ doped region at the bottom of the first trench. The third oxide layer is removed, a carbon film is grown on the surface, and high-temperature annealing is performed to activate the dopants in the first P+ doped region and the second P+ doped region, and then the carbon film is removed. Metallic nickel is grown to fill the first trench; The nickel metal outside the first trench is removed by CMP process, while the nickel metal inside the first trench is retained; an alloying process is used to make the nickel metal in the first trench form an ohmic contact with the first P+ doped region.

2. The method for manufacturing a silicon carbide diode according to claim 1, characterized in that, The above steps are followed by the following steps: A fourth oxide layer is deposited, and the fourth oxide layer in the third defined region is removed by photolithography and etching processes. Using the fourth oxide layer as a masking layer, a second trench is formed in the silicon carbide epitaxial layer by dry etching process. The third defined region is located in the cell region of the device and does not overlap with the first defined region mentioned above. That is, the second trench is formed outside the first defined region of the cell region. The fourth oxide layer is removed using a wet etching process; A fifth oxide layer is grown, and the fifth oxide layer in the cell region is removed using photolithography and etching processes. Physical vapor deposition is used to grow metallic titanium, and an alloying process is used to form a Schottky barrier between the metallic titanium and the surface of the silicon carbide epitaxial layer in the cell region. Fabricate the front metal layer, specifically an aluminum layer of 3.0±0.3um; The passivation layer can be a composite layer consisting of an oxide layer, silicon nitride, and polyimide. Backside grinding and backside metallization.

3. The method for manufacturing a silicon carbide diode according to claim 2, characterized in that, include: The high-temperature environment is 500±30 degrees Celsius. The thickness of the third oxide layer is 500±100nm, the thickness of the nickel is 100±10nm, the width of the first trench is 1±0.1um, the depth of the first trench is 1±0.1um, the width of the second trench is 2±0.2um, and the depth of the first trench is 0.5±0.1um.

4. A silicon carbide diode manufactured using the method for manufacturing a silicon carbide diode as described in claim 2, characterized in that, It includes a silicon carbide epitaxial layer and a Schottky barrier, wherein the Schottky barrier is formed on the surface of the silicon carbide epitaxial layer.

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