Wafer-based semiconductor structure board-level manufacturing method

Abstract

This application provides a board-level manufacturing method for a wafer-based semiconductor structure. The manufacturing method includes: providing multiple wafers and a first carrier board, wherein each wafer includes multiple interconnected first chips, and the front side of each first chip has a first bonding pad; cutting the wafer near the first bonding pad to form a gap between adjacent first chips with a depth less than the thickness of the wafer; forming a protective layer on the wafer, the material of which enters the gap; mounting the multiple wafers onto the first carrier board, with the protective layer facing the first carrier board; the first carrier board is a panel-level carrier board; forming a first molding compound layer covering at least the sidewalls of the wafers; peeling off the first carrier board and mounting the resulting first molding compound structure onto a second carrier board, with the protective layer facing away from the second carrier board; forming a first redistribution structure on the protective layer to lead out the first bonding pads; peeling off the second carrier board to obtain a semiconductor intermediate structure; and cutting the semiconductor intermediate structure to obtain multiple semiconductor structures including at least one of the first chips.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a board-level manufacturing method for a wafer-based semiconductor structure. Background Technology

[0002] In existing packaging technologies, in order to improve processing accuracy, wafer-level packaging equipment is required to first perform rewiring on the wafer to increase the spacing between adjacent pads of the chip, then cut the wafer into multiple chips, and finally mount the chips onto a panel-level carrier board and perform fan-out packaging using panel-level packaging equipment.

[0003] In other words, existing packaging technologies require both panel-level and wafer-level equipment, resulting in higher packaging costs. Summary of the Invention

[0004] This application provides a method for board-level manufacturing of a wafer-based semiconductor structure. The method includes: A plurality of wafers and a first substrate are provided, wherein the wafers include a plurality of interconnected first chips and a plurality of first pads are provided on the front side of the first chips; The wafer is cut on the side closest to the first bonding pad to create a gap between adjacent first chips, the depth of which is less than the thickness of the wafer. A protective layer is formed on the side of the wafer near the first bonding pad, and the material of the protective layer enters into the gap; The plurality of wafers are mounted on the first carrier board, with the front side of the first chip facing the first carrier board; the first carrier board is a panel-level carrier board; A first molding compound is formed, wherein the first molding compound covers at least one side of the wafer; Peel off the first substrate to obtain the first molding compound structure, and attach the first molding compound structure to the second substrate, with the front side of the first chip facing away from the second substrate; A first rewiring structure is formed on the front side of the first chip to bring out the first solder pad; The second substrate is peeled off to obtain the semiconductor intermediate structure; The semiconductor intermediate structure is cut to obtain multiple semiconductor structures, each semiconductor structure including at least one of the first chips.

[0005] In one embodiment, the first rewiring structure includes a first rewiring layer electrically connected to the first pad and a first conductive post located on the side of the first rewiring layer away from the first chip; the first rewiring layer includes a plurality of first conductive traces, each of the first pads is electrically connected to one of the first conductive traces, and each of the first conductive traces is provided with a first conductive post on the side away from the first chip; the minimum spacing between adjacent first pads is less than the minimum spacing between two first conductive posts electrically connected to them.

[0006] In one embodiment, the first redistribution structure includes a first redistribution layer electrically connected to the first pad, and a first conductive pillar located on the side of the first redistribution layer facing away from the first chip; after cutting the semiconductor intermediate structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes: The plurality of semiconductor structures are mounted on a third carrier board, with the first conductive post facing away from the third carrier board; the third carrier board is a panel-level carrier board. A second molding compound is formed, which covers the side surface of the semiconductor structure and the surface facing away from the third substrate, and the first conductive pillar is exposed in the second molding compound. A second rewiring structure is formed on the surface of the second molding layer opposite to the first chip, and the second rewiring structure is electrically connected to the first conductive pillar. The third substrate is peeled off to obtain a semiconductor packaging structure; The semiconductor package structure is cut to obtain multiple substructures, each of which includes at least one of the first chips.

[0007] In one embodiment, the second redistribution structure includes a second redistribution layer and a second conductive post located on the side of the second redistribution layer opposite to the first chip; the orthographic projection of the second conductive post on the surface of the first chip opposite to the second conductive post is located outside the first chip; and / or, the minimum spacing between adjacent second conductive posts is greater than the minimum spacing between adjacent first conductive posts; and / or, the number of second conductive posts is greater than the number of first conductive posts.

[0008] In one embodiment, the first redistribution structure includes a first redistribution layer electrically connected to the first pad, the first redistribution layer including a plurality of first conductive traces, each of the first pads being electrically connected to one of the first conductive traces; before stripping the second carrier board, the wafer-based semiconductor structure board-level manufacturing method further includes: An insulating layer is formed covering the first redistribution layer; A plurality of first openings are formed on the insulating layer, each first opening exposing a portion of a first conductive trace; the minimum spacing between adjacent first pads is less than the minimum spacing between the first openings corresponding to two first conductive traces connected to them. After cutting the semiconductor intermediate structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes: The plurality of semiconductor structures are mounted on a fourth substrate, with the first opening facing the fourth substrate; the fourth substrate is a panel-level substrate. A third molding compound is formed, the third molding compound covering at least the side surface of the semiconductor structure; Peel off the fourth carrier plate to obtain the second encapsulated structure; A second rewiring structure is formed on the surface of the third molding layer near the first opening, and the second rewiring structure is electrically connected to the first rewiring structure through the first opening.

[0009] In one embodiment, prior to forming the first molding compound, the wafer-based semiconductor structure board-level manufacturing method further includes: using the gap as an alignment marker, mounting a plurality of second chips on the side of the plurality of wafers away from the first bonding pad, with a second chip respectively disposed on the back side of each first chip; and the surface of the second chip away from the first chip having a second bonding pad. The semiconductor structure includes the first chip and the second chip; after cutting the intermediate semiconductor structure to obtain multiple semiconductor structures, the wafer-based board-level manufacturing method for the semiconductor structure further includes: The plurality of semiconductor structures are mounted on a fifth substrate, with the first redistribution structure facing away from the fifth substrate; the fifth substrate is a panel-level substrate. A fourth molding compound is formed, the fourth molding compound covering at least the side surface of the semiconductor structure; A third rewiring structure is formed on the side of the fourth molding layer away from the fifth substrate. The third rewiring structure is electrically connected to the first rewiring structure. The orthographic projection of the third rewiring structure on the fifth substrate is located outside the orthographic projection of the first chip on the fifth substrate. Peel off the fifth substrate and form a second opening on the fourth molding layer to expose a portion of the third redistribution structure; A first connecting post is formed within the second opening, and a fourth rewiring structure is formed on the surface of the first molding layer opposite to the first chip. The fourth rewiring structure is electrically connected to the third rewiring structure through the first connecting post, and the fourth rewiring structure is electrically connected to the second pad.

[0010] In one embodiment, prior to forming the first molding compound layer, the wafer-based semiconductor structure board-level manufacturing method further includes: The side of the plurality of wafers facing away from the first bonding pad is thinned to expose the gap.

[0011] In one embodiment, after thinning the side of the plurality of wafers away from the first bonding pad to expose the gap, the wafer-based semiconductor structure board-level manufacturing method further includes: A metal layer is formed on the side of the plurality of wafers opposite to the protective layer; the second chip is mounted on the metal layer; After the fifth substrate is stripped, the wafer-based semiconductor structure board-level manufacturing method further includes: A third opening is formed on the first molding layer to expose a portion of the metal layer; A second connecting post is formed within the third opening, and a heat sink is formed on the second connecting post away from the first chip. The heat sink is electrically connected to the metal layer through the second connecting post.

[0012] In one embodiment, the metal layer does not cover the gap; or, The metal layer covers the gap, and the metal layer forms a recess at the gap; the mounting of multiple second chips on the side of the plurality of wafers opposite to the first bonding pad, using the gap as an alignment marker, includes: Using the recess formed by the metal layer at the gap as an alignment mark, a plurality of second chips are mounted on the side of the plurality of wafers away from the first bonding pad.

[0013] In one embodiment, the metal layer is made of silver paste or copper paste; after mounting multiple second chips on the side of the plurality of wafers away from the first bonding pad, the wafer-based semiconductor structure board-level manufacturing method further includes: The silver paste or copper paste is cured, and the second chip is mounted on the plurality of wafers using the silver paste or copper paste.

[0014] The main technical effects achieved by the embodiments of this application are: The wafer-based semiconductor structure board-level manufacturing method provided in this application embodiment involves mounting multiple wafers onto a first substrate at the panel level to obtain a first molding compound structure, and then mounting the first molding compound structure onto a second substrate at the panel level. Using the wafer's positioning structure as an alignment marker, a first redistribution structure is formed on the front side of the first chip. The semiconductor structure manufacturing process can utilize panel-level equipment. Compared to a scheme using wafer-level equipment to form the first redistribution structure on a wafer, the wafer-based semiconductor structure board-level manufacturing method provided in this application embodiment can reduce manufacturing costs while ensuring product accuracy. The wafer-based semiconductor structure board-level manufacturing method provided in this application embodiment can simultaneously package chips from multiple wafers, significantly improving packaging efficiency. Furthermore, compared to a scheme that first cuts the wafer into multiple chips and then performs molding compounding, it simplifies the semiconductor structure manufacturing steps and improves efficiency. Since the chips in the same wafer do not undergo relative position changes due to cutting, forming the first molding compound layer, or filling the protective layer before forming the first redistribution structure, and no chip mounting is performed, the fabrication accuracy of the first redistribution layer is well guaranteed. Meanwhile, in this embodiment, the wafer is cut on the side closest to the first solder pad to form a gap smaller than the wafer thickness between adjacent first chips, and a protective layer is formed on the side of the wafer closest to the first solder pad, allowing the material of the protective layer to enter the gap. This not only keeps the relative positions of the chips in the wafer unchanged, but also provides a buffer between the wafer material and the material of the first molding compound, preventing the wafer from cracking due to the difference in the coefficient of thermal expansion between the molding compound and the wafer. Attached Figure Description

[0015] Figure 1 This is a flowchart of a wafer-based semiconductor structure board-level manufacturing method provided in an exemplary embodiment of this application; Figure 2 This is a schematic diagram of the three-dimensional structure of a wafer provided in an exemplary embodiment of this application; Figure 3 This is a three-dimensional structural diagram of the first intermediate structure provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram of the structure of the first intermediate structure provided in an exemplary embodiment of this application; Figure 5 This is a schematic diagram of the second intermediate structure provided in an exemplary embodiment of this application; Figure 6 This is a three-dimensional structural diagram of the third intermediate structure provided in an exemplary embodiment of this application; Figure 7 This is a schematic diagram of the third intermediate structure provided in an exemplary embodiment of this application; Figure 8This is a schematic diagram of the fourth intermediate structure provided in an exemplary embodiment of this application; Figure 9 This is a schematic diagram of the fifth intermediate structure provided in an exemplary embodiment of this application; Figure 10 This is a partial structural diagram of the sixth intermediate structure provided in an exemplary embodiment of this application; Figure 11 This is a partial structural diagram of the sixth intermediate structure provided in an exemplary embodiment of this application; Figure 12 This is a partial structural diagram of the seventh intermediate structure provided in an exemplary embodiment of this application; Figure 13 This is a partial structural diagram of the seventh intermediate structure provided in an exemplary embodiment of this application from another perspective; Figure 14 This is a partial structural diagram of the eighth intermediate structure provided in an exemplary embodiment of this application; Figure 15 This is a partial structural diagram of the ninth intermediate structure provided in an exemplary embodiment of this application; Figure 16 This is a partial structural diagram of the tenth intermediate structure provided in an exemplary embodiment of this application; Figure 17 This is a partial structural diagram of the eleventh intermediate structure provided in an exemplary embodiment of this application; Figure 18 This is a schematic diagram of the semiconductor intermediate structure provided in an exemplary embodiment of this application; Figure 19 This is a schematic diagram of a semiconductor structure provided in an exemplary embodiment of this application; Figure 20 This is a schematic diagram of a semiconductor structure provided in another exemplary embodiment of this application; Figure 21 This is a partial structural diagram of the eleventh intermediate structure provided in an exemplary embodiment of this application from one perspective; Figure 22 This is a schematic diagram of the eleventh intermediate structure provided in an exemplary embodiment of this application from another perspective; Figure 23 This is a partial structural schematic diagram of a semiconductor structure provided in another exemplary embodiment of this application; Figure 24 This is a schematic diagram of the thirteenth intermediate structure provided in an exemplary embodiment of this application; Figure 25 This is a schematic diagram of the fourteenth intermediate structure provided in an exemplary embodiment of this application; Figure 26This is a schematic diagram of the fifteenth intermediate structure provided in an exemplary embodiment of this application; Figure 27 This is a schematic diagram of the sixteenth intermediate structure provided in an exemplary embodiment of this application; Figure 28 This is a schematic diagram of the seventeenth intermediate structure provided in an exemplary embodiment of this application; Figure 29 This is a schematic diagram of the substructure provided in an exemplary embodiment of this application; Figure 30 This is a partial structural diagram of the eighteenth intermediate structure provided in an exemplary embodiment of this application; Figure 31 This is a schematic diagram of the nineteenth intermediate structure provided in an exemplary embodiment of this application; Figure 32 This is a schematic diagram of the twentieth intermediate structure provided in an exemplary embodiment of this application; Figure 33 This is a schematic diagram of the twenty-first intermediate structure provided in an exemplary embodiment of this application; Figure 34 This is a schematic diagram of the twenty-second intermediate structure provided in an exemplary embodiment of this application; Figure 35 This is a schematic diagram of the substructure provided in an exemplary embodiment of this application; Figure 36 This is a schematic diagram of the twenty-third intermediate structure provided in an exemplary embodiment of this application; Figure 37 This is a schematic diagram of the twenty-fourth intermediate structure provided in an exemplary embodiment of this application; Figure 38 This is a schematic diagram of the twenty-fifth intermediate structure provided in an exemplary embodiment of this application; Figure 39 This is a schematic diagram of the twenty-sixth intermediate structure provided in an exemplary embodiment of this application; Figure 40 This is a schematic diagram of the twenty-seventh intermediate structure provided in an exemplary embodiment of this application; Figure 41 This is a schematic diagram of the twenty-eighth intermediate structure provided in an exemplary embodiment of this application; Figure 42 This is a schematic diagram of the twenty-ninth intermediate structure provided in an exemplary embodiment of this application; Figure 43 This is a partial structural diagram of the twenty-ninth intermediate structure provided in an exemplary embodiment of this application; Figure 44This is a schematic diagram of the thirtieth intermediate structure provided in an exemplary embodiment of this application; Figure 45 This is a schematic diagram of a semiconductor structure provided in another exemplary embodiment of this application; Figure 46 This is a schematic diagram of the thirty-first intermediate structure provided in an exemplary embodiment of this application; Figure 47 This is a schematic diagram of the thirty-second intermediate structure provided in an exemplary embodiment of this application; Figure 48 This is a schematic diagram of the thirty-third intermediate structure provided in an exemplary embodiment of this application; Figure 49 This is a schematic diagram of the thirty-fourth intermediate structure provided in an exemplary embodiment of this application; Figure 50 This is a schematic diagram of the thirty-fifth intermediate structure provided in an exemplary embodiment of this application; Figure 51 This is a schematic diagram of the thirty-sixth intermediate structure provided in an exemplary embodiment of this application; Figure 52 This is a schematic diagram of the thirty-seventh intermediate structure provided in an exemplary embodiment of this application; Figure 53 This is a schematic diagram of the thirty-eighth intermediate structure provided in an exemplary embodiment of this application; Figure 54 This is a schematic diagram of the substructure provided in another exemplary embodiment of this application. Specific Implementation

[0016] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0017] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0018] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0019] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0020] This application provides a wafer-level semiconductor structure fabrication method at the board level. The board-level fabrication method refers to a method for manufacturing semiconductor structures using panel-level equipment. See also... Figure 1 The wafer-based semiconductor structure board-level manufacturing method includes the following steps 110 to 190.

[0021] In step 110, a plurality of wafers and a first substrate are provided. The wafers include a plurality of interconnected first chips, and the front side of the first chips is provided with a plurality of first pads.

[0022] In step 120, the side of the wafer closest to the first bonding pad is cut to form a gap between adjacent first chips, the depth of which is less than the thickness of the wafer.

[0023] In step 130, a protective layer is formed on the side of the wafer near the first bonding pad, and the material of the protective layer enters the gap.

[0024] In step 140, the plurality of wafers are mounted on the first carrier board, with the protective layer facing the first carrier board; the first carrier board is a panel-level carrier board.

[0025] In step 150, a first molding compound is formed, which at least covers the side surface of the wafer.

[0026] In step 160, the first carrier plate is peeled off to obtain the first encapsulated structure, and the first encapsulated structure is attached to the second carrier plate, with the protective layer facing away from the second carrier plate.

[0027] In step 170, a first rewiring structure is formed on the protective layer to bring out the first solder pad.

[0028] In step 180, the second carrier plate is peeled off to obtain a semiconductor intermediate structure.

[0029] In step 190, the semiconductor intermediate structure is cut to obtain multiple semiconductor structures, each semiconductor structure including at least one of the first chips.

[0030] The wafer-based semiconductor structure board-level manufacturing method provided in this application embodiment involves mounting multiple wafers onto a first substrate at the panel level to obtain a first molding compound structure, and then mounting the first molding compound structure onto a second substrate at the panel level. Using the wafer's positioning structure as an alignment marker, a first redistribution structure is formed on the front side of the first chip. The semiconductor structure manufacturing process can utilize panel-level equipment. Compared to a scheme using wafer-level equipment to form the first redistribution structure on a wafer, the wafer-based semiconductor structure board-level manufacturing method provided in this application embodiment can reduce manufacturing costs while ensuring product accuracy. The wafer-based semiconductor structure board-level manufacturing method provided in this application embodiment can simultaneously package chips from multiple wafers, significantly improving packaging efficiency. Furthermore, compared to a scheme that first cuts the wafer into multiple chips and then performs molding compounding, it simplifies the semiconductor structure manufacturing steps and improves efficiency. Since the chips in the same wafer do not undergo relative position changes due to cutting, forming the first molding compound layer, or filling the protective layer before forming the first redistribution structure, and no chip mounting is performed, the fabrication accuracy of the first redistribution layer is well guaranteed. Meanwhile, in this embodiment, the wafer is cut on the side closest to the first solder pad to form a gap smaller than the wafer thickness between adjacent first chips, and a protective layer is formed on the side of the wafer closest to the first solder pad, allowing the material of the protective layer to enter the gap. This not only keeps the relative positions of the chips in the wafer unchanged, but also provides a buffer between the wafer material and the material of the first molding compound, preventing the wafer from cracking due to the difference in the coefficient of thermal expansion between the molding compound and the wafer.

[0031] The steps of the wafer-based semiconductor structure board-level manufacturing method provided in the embodiments of this application will be described in detail below.

[0032] Example 1: In step 110, a plurality of wafers and a first substrate are provided. The wafers include a plurality of interconnected first chips, and the front side of the first chips is provided with a plurality of first pads.

[0033] In one embodiment, such as Figure 2 As shown, wafer 10 has a circular structure. The wafer includes multiple chips, which are interconnected. Interconnection of multiple chips means that at least a portion of the film layers of the multiple chips are integrally formed.

[0034] In step 120, the side of the wafer closest to the first bonding pad is cut to form a gap between adjacent first chips, the depth of which is less than the thickness of the wafer.

[0035] This step yields the following result: Figure 3 and Figure 4 The first intermediate structure shown. (As shown) Figure 2 and Figure 3 As shown, gaps 12 are formed between adjacent first chips 11. Since the depth of the gaps 12 is less than the thickness of the wafer 10, the multiple first chips 11 of the wafer 10 are still connected together after the wafer 10 is cut to form the gaps 12.

[0036] In step 130, a protective layer is formed on the side of the wafer near the first bonding pad, and the material of the protective layer enters the gap.

[0037] Here, the side of wafer 10 closest to the first bonding pad refers to the side of wafer 10 where the first bonding pad is located, that is, the side of wafer 10 located on the front side of the first chip 11. This step yields the second intermediate structure. A protective layer covers the side of wafer 10 where the first bonding pad is located, and the protective layer covers the bonding pad.

[0038] When the first molding layer is formed in step 150, the process temperature is high, the expansion coefficient of the first molding layer is high, and the expansion coefficient of the wafer is low. Since the material of the protective layer enters the gap 12, the material of the protective layer entering the gap 12 can play a buffering role to prevent the wafer 10 from cracking due to the difference in expansion coefficients between the first molding layer and the wafer 10.

[0039] In one embodiment, the protective layer is one or more layers of insulating material. The material of the protective layer can be a molding compound, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties. The protective layer can be formed on the wafer 10 by lamination, spin coating, printing, molding, or other suitable methods.

[0040] In one embodiment, after the step of forming a protective layer on the side of the wafer close to the first pad, the board-level manufacturing method of the wafer-based semiconductor structure further includes: thinning the back side of the wafer.

[0041] The back side of the wafer can be thinned by grinding. After thinning the back side of the wafer, gap 12 may or may not be exposed. The second intermediate structure obtained when gap 12 is exposed after wafer thinning is as follows: Figure 5 As shown.

[0042] In step 140, the plurality of wafers are mounted on the first carrier board, with the protective layer facing the first carrier board; the first carrier board is a panel-level carrier board.

[0043] Panel-level carriers refer to large carriers used in panel-level packaging processes. Panel-level carriers can be rectangular or other shapes. They can be stainless steel substrates, polymer substrates, etc.

[0044] Step 140 yields the following result: Figure 6 And the third intermediate structure shown in 7. For example... Figure 6 As shown in Figure 7, a plurality of wafers 10 may be mounted on the first carrier 20. The wafers 10 may be mounted on the first carrier 20 by means of an adhesive layer 21, and the adhesive layer 21 may be made of an easy-to-peel material so that the first carrier 20 may be separated from the wafers 10 in the future. For example, the adhesive layer 21 may be made of a heat-release material that can be heated to lose its stickiness.

[0045] In step 150, a first molding compound is formed, which at least covers the side surface of the wafer.

[0046] Step 150 yields the following result: Figure 8 The fourth intermediate structure is shown. (As shown in the image) Figure 8 As shown, the first molding compound 14 covers both the side surface and the back surface of each wafer 10. In other embodiments, the first molding compound 14 may cover only the side surface of each wafer 10.

[0047] In one embodiment, before forming the first molding layer 14, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surfaces of the wafer 10 and the first substrate 20, so that the first molding layer 14 can be more closely connected to the wafer 10 and the first substrate 20, and to prevent delamination or cracking.

[0048] In one embodiment, the first molding layer 14 can be a polymer, resin, resin composite material, or polymer composite material. For example, the first molding layer 14 can be a resin with fillers, wherein the fillers are inorganic particles. The first molding layer 14 can be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0049] In step 160, the first carrier plate is peeled off to obtain the first encapsulated structure, and the first encapsulated structure is attached to the second carrier plate, with the protective layer facing away from the second carrier plate.

[0050] The second carrier is a panel-level carrier.

[0051] In this step, after the first substrate is peeled off, the protective layer 13 is exposed. In some embodiments, the first substrate 20 can be directly and mechanically peeled off from the first molding layer 14 and the wafer 10. In other embodiments, the first molding layer 14 and the wafer 10 are bonded to the first substrate 20 by an adhesive layer 21, and when the material of the adhesive layer 21 is a heat-removing material, the adhesive layer 21 can also be heated to reduce its stickiness, thereby peeling off the first substrate 20.

[0052] Step 160 yields the following result: Figure 9 The fifth intermediate structure is shown. (As shown in the image) Figure 9 As shown, the first molding structure is attached to the second carrier plate 22 by an adhesive layer 23. The adhesive layer 23 can be made of an easy-to-peel material so that the second carrier plate 22 can be peeled off from the first molding layer 14 in the future. For example, the adhesive layer can be made of a heat-removing material that can lose its stickiness by heating.

[0053] In step 170, using the positioning structure as an alignment marker, a first rewiring structure is formed on the protective layer to bring out the first solder pad.

[0054] In one embodiment, prior to step 170, the board-level manufacturing method of the wafer-based semiconductor structure further includes: forming vias on the protective layer to expose the first bonding pads.

[0055] This step yields the following result: Figure 10 and Figure 11 The sixth intermediate structure shown, in which Figure 11 This is a magnified view of a portion of the sixth intermediate structure. (See attached image.) Figure 10 and Figure 11 As shown, a plurality of through holes 131 are formed on the protective layer 13, and each through hole 131 exposes a solder pad 15.

[0056] In one embodiment, the positioning structure can be a target point set on the front side of the wafer. Using the positioning structure as an alignment marker can prevent the position of the formed first redistribution structure from shifting, thereby improving the accuracy of the first redistribution structure.

[0057] In one embodiment, the first redistribution structure includes a first redistribution layer electrically connected to the first pads, and a first conductive post located on the side of the first redistribution layer facing away from the first chip. The first redistribution layer includes a plurality of first conductive traces, each of the first pads being electrically connected to one of the first conductive traces, and each of the first conductive traces having a first conductive post on the side facing away from the first chip.

[0058] In one embodiment, the minimum spacing between adjacent first pads is less than the minimum spacing between two first conductive posts electrically connected to them. This configuration increases the minimum spacing between the conductive posts extending from the first pads, reducing the precision requirements for the subsequent redistribution layer formed on top of the first redistribution layer.

[0059] Furthermore, the area of ​​the first conductive post is larger than the area of ​​the first solder pad electrically connected to it. This also helps to reduce the accuracy requirements of the subsequent rewiring layer formed on top of the first rewiring layer.

[0060] In one embodiment, step 170 can be completed through the following process: First, a first redistribution layer is formed on the side of the protective layer 13 opposite to the first chip 11.

[0061] This step yields the following result: Figure 12 and Figure 13 The seventh intermediate structure shown is Figure 12 and Figure 13 These are all enlarged views of the seventh intermediate structure. For example... Figure 12 and Figure 13 As shown, the first redistribution layer includes a plurality of first conductive traces 161, which are electrically connected through conductive portions 132 located within vias 131. In some embodiments, the conductive portions 132 and the first conductive traces 161 can be formed in the same process step. Thus, the conductive portions 132 and the first conductive traces 161 can be formed simultaneously in a single process step, which helps simplify the semiconductor packaging process. In other embodiments, the conductive portions 132 and the first conductive traces 161 may not be formed simultaneously; the conductive portions 132 may be formed first, followed by the first conductive traces 161.

[0062] Subsequently, an insulating layer is formed covering the first conductive trace 161 and the exposed protective layer 13.

[0063] This step yields the following result: Figure 14 The eighth intermediate structure shown is Figure 14 This is a magnified view of a portion of the eighth intermediate structure. (See image below.) Figure 14 As shown, the insulating layer 17 covers each of the first conductive traces 161 and the exposed protective layer 13.

[0064] Subsequently, a through-hole is formed on the insulating layer to expose the first conductive trace 161.

[0065] This step yields the following result: Figure 15 The ninth intermediate structure shown, Figure 15 This is a magnified view of a portion of the ninth intermediate structure. (See image below.) Figure 15As shown, through holes 171 are formed on the insulating layer 17 to expose the first conductive trace 161. The through holes 171 can correspond one-to-one with the first conductive trace 161, and each through hole 171 exposes the corresponding first conductive trace 161.

[0066] Subsequently, a first conductive pillar is formed in the through-hole 171 of the insulating layer 17 to obtain a first redistribution layer including the first conductive pillar and the first conductive trace.

[0067] This step yields the following result: Figure 16 The tenth intermediate structure shown, Figure 16 This is a magnified view of a portion of the tenth intermediate structure. (See image below.) Figure 16 As shown, a first conductive post 162 is formed within a through-hole 171, and the first conductive post 162 is in direct contact with the first conductive trace 161. The first redistribution layer 16 includes the first conductive post 162 and the first conductive trace 161.

[0068] In some embodiments, the first conductive trace 161 and the first conductive post 162 may be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The material of the first conductive trace 161 and the first conductive post 162 may be a metallic material, such as copper.

[0069] In one embodiment, after step 170, the board-level manufacturing method of the wafer-based semiconductor structure further includes: forming solder balls on the side of the first conductive pillar opposite to the first chip.

[0070] This step yields the following result: Figure 17 The eleventh intermediate structure shown is Figure 17 This is a magnified view of a portion of the eleventh intermediate structure. (See image below.) Figure 17 As shown, solder ball 18 is located on the side of the first conductive post 162 opposite to the first chip 11. Solder ball 18 facilitates the soldering of the resulting semiconductor structure to other components. The material of solder ball 18 can be tin.

[0071] In step 180, the second carrier plate is peeled off to obtain a semiconductor intermediate structure.

[0072] Step 180 yields the following result: Figure 18 The semiconductor intermediate structure shown.

[0073] In one embodiment, the second carrier plate 22 can be directly and mechanically peeled off from the first molding layer 14. In other embodiments, the first molding layer 14 and the second carrier plate 22 are bonded together by an adhesive layer 23. When the material of the adhesive layer 23 is a heat-removing material, the adhesive layer 23 can be heated to reduce its stickiness, thereby peeling off the second carrier plate 22.

[0074] In step 190, the semiconductor intermediate structure is cut to obtain multiple semiconductor structures, each semiconductor structure including at least one of the first chips.

[0075] The steps can be followed to obtain the following: Figure 19 Or such as Figure 20 The semiconductor structure shown. (As shown in the image) Figure 19 and Figure 20 As shown, the semiconductor structure includes a first chip 11, a first molding compound 14 located on the back of the first chip 11, and a first redistribution structure 16 located on the front of the first chip 11. Figure 19 and Figure 20 The semiconductor structure includes a first chip 11. In other embodiments, the semiconductor structure may include two or more first chips 11.

[0076] The wafer-based semiconductor structure board-level manufacturing method provided in this application mounts multiple wafers onto a first substrate at the panel level and uses panel-level equipment to fabricate a first redistribution structure. This not only reduces manufacturing costs but also allows for simultaneous chip packaging of multiple wafers, significantly improving packaging efficiency. Since the chips within the same wafer do not undergo relative position changes due to steps such as dicing, forming the first molding compound, or filling the protective layer before forming the first redistribution structure, and no chip mounting is performed, the fabrication accuracy of the first redistribution layer is well guaranteed. Simultaneously, this application embodiment dices the wafer on the side closest to the first bonding pad, creating a gap smaller than the wafer thickness between adjacent first chips. A protective layer is formed on the side of the wafer closest to the first bonding pad, allowing the material of the protective layer to enter the gap. This not only maintains the relative positions of the chips within the wafer but also buffers the wafer material against the material of the first molding compound, preventing wafer breakage due to the difference in expansion coefficients between the molding compound and the wafer.

[0077] Example 2 In Embodiment 2, only the differences from Embodiment 1 are described; the similarities with Embodiment 1 will not be repeated. In this embodiment, the minimum spacing between adjacent first solder pads is less than the minimum spacing between the two first conductive posts electrically connected to them.

[0078] In this embodiment, step 170 can yield the following result: Figure 21 and Figure 22 The twelfth intermediate structure shown. (Example) Figure 21 and Figure 22As shown, the first redistribution structure 16 includes a first redistribution layer electrically connected to the first pad 15, and a first conductive post 162 located on the side of the first redistribution layer facing away from the first chip 11. The first redistribution layer includes a plurality of first conductive traces 161, each of the first pads 15 being electrically connected to one of the first conductive traces 161, and each of the first conductive traces 161 having a first conductive post 162 on the side facing away from the first chip 11. The difference between this embodiment and Embodiment 1 is that an insulating layer is not formed during the formation of the first redistribution layer in this embodiment. After step 190 of cutting the semiconductor intermediate structure to obtain a plurality of semiconductor structures, the following is obtained: Figure 23 The semiconductor structure shown.

[0079] In one embodiment, after step 190 of cutting the semiconductor intermediate structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes: First, the plurality of semiconductor structures are mounted on a third carrier board, with the first conductive post facing away from the third carrier board; the third carrier board is a panel-level carrier board.

[0080] This step yields the following result: Figure 24 The thirteenth intermediate structure is shown. (See example...) Figure 24 As shown, the semiconductor structure is mounted on the third carrier 28 via an adhesive layer 29. The adhesive layer 29 can be made of an easily peelable material to facilitate the subsequent separation of the third carrier 28 from the semiconductor structure. For example, the adhesive layer 29 can be made of a thermally desiccant that loses its adhesiveness upon heating. The third carrier supports the semiconductor structure, facilitating subsequent packaging processes; if the third carrier is a panel-level carrier, then panel-level equipment can be used for subsequent packaging processes.

[0081] Subsequently, a second molding compound is formed, which covers the side surface of the semiconductor structure and the surface facing away from the third substrate, with the first conductive post exposed in the second molding compound.

[0082] Figure 25 This is a schematic diagram of the fourteenth intermediate structure obtained after the formation of the second molding layer. Figure 26 This is a schematic diagram of the fifteenth intermediate structure obtained after thinning the second molding layer. Figure 25 As shown, the initially formed second molding compound 31 covers the side of the semiconductor structure and the first conductive pillar 162. After the second molding compound 31 is thinned, the first conductive pillar 162 is exposed away from the surface of the first chip 11.

[0083] In one embodiment, the second molding layer 31 can be a polymer, resin, resin composite material, or polymer composite material. For example, the second molding layer 31 can be a resin with fillers, wherein the fillers are inorganic particles. The second molding layer 31 can be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0084] Subsequently, a second rewiring structure is formed on the surface of the second molding layer opposite to the first chip, and the second rewiring structure is electrically connected to the first conductive pillar.

[0085] This step yields the following result: Figure 27 The sixteenth intermediate structure shown. (Example) Figure 27 As shown, the second redistribution structure 19 includes a second conductive trace 191 and a second conductive post 192 located on the side of the second conductive trace 191 away from the first chip 11. Each second conductive trace 191 may have a second conductive post 192 formed on it, and each second conductive trace 191 is in direct contact with a first conductive trace 161.

[0086] In one embodiment, the orthographic projection of the second conductive post onto the surface of the first chip facing away from the second conductive post is located outside the first chip. And / or, the minimum spacing between adjacent second conductive posts is greater than the minimum spacing between adjacent first conductive posts. And / or, in one embodiment, the number of second conductive posts is greater than the number of first conductive posts. This facilitates electrical connection of the second conductive posts to other structures.

[0087] In one embodiment, the second conductive trace 191 and the second conductive post 192 can be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The material of the second conductive trace 191 and the second conductive post 192 can be a metallic material, such as copper.

[0088] In one embodiment, after forming the second redistribution structure, the semiconductor structure manufacturing method may further include: forming an insulating material layer covering the second redistribution structure, wherein the second conductive pillars are exposed away from the surface of the first chip, revealing the insulating material layer. After forming the insulating material layer, the desired result is... Figure 28 The seventeenth intermediate structure shown.

[0089] like Figure 28 As shown, the insulating material layer 193 covers the second rewiring structure 19, and the second conductive post 192 is exposed away from the surface of the first chip 11, thus protecting the second rewiring structure 19.

[0090] The distance from the side of the insulating material layer 193 away from the first chip 11 is approximately the same as the distance from the side of the second conductive post 192 away from the first chip 11, so that the surface of the second conductive post 192 just exposes the insulating material layer 193. During the formation of the insulating material layer 193, the initially formed insulating material layer 193 can cover the surface and sides of the second conductive post 192, and then the insulating material layer 193 is thinned to expose the surface of the second conductive post 192 away from the first chip 11.

[0091] In one embodiment, the orthographic projection of the second conductive post 192 onto the surface of the first chip 11 opposite to the second conductive post 192 is located outside the first chip 11. This arrangement reduces the density of the second conductive post 192, facilitating its connection to other structures.

[0092] Subsequently, the third substrate is peeled off to obtain the semiconductor packaging structure.

[0093] Subsequently, the semiconductor packaging structure is cut to obtain multiple substructures, each of which includes at least one of the first chips.

[0094] This step yields the following result: Figure 29 The substructure shown. For example... Figure 29 As shown, the substructure includes a first chip 11. In other embodiments, the substructure may also include two or more first chips 11.

[0095] The wafer-based semiconductor structure board-level manufacturing method provided in this application has the same effect as Embodiment 1. By mounting multiple wafers on a first substrate at the panel level and using panel-level equipment to fabricate the first redistribution structure, not only can manufacturing costs be reduced, but chip packaging of multiple wafers can also be performed simultaneously, greatly improving packaging efficiency. Since the chips in the same wafer do not change their relative positions due to steps such as cutting, forming the first molding compound, or filling the protective layer before forming the first redistribution structure, and no chip mounting is performed, the fabrication accuracy of the first redistribution layer is well guaranteed. At the same time, this application embodiment cuts the side of the wafer near the first pad to form a gap smaller than the wafer thickness between adjacent first chips, and forms a protective layer on the side of the wafer near the first pad, allowing the material of the protective layer to enter the gap. This not only keeps the relative positions of the chips in the wafer unchanged, but also buffers the wafer material and the material of the first molding compound, preventing the wafer from cracking due to the difference in the coefficient of thermal expansion between the molding compound and the wafer. Furthermore, in this embodiment, the wafer is diced to form a semiconductor structure with a first redistribution structure, and after the semiconductor structure is mounted on a third substrate, subsequent packaging steps, including the formation of a second redistribution structure, are performed using panel-level equipment. Although undesirable changes in the relative positions of the chips occur during the dicing, semiconductor structure mounting, and formation of the second molding compound before the formation of the second redistribution structure, the packaging accuracy can still be guaranteed because the preceding steps have reduced the precision requirements for forming the second redistribution layer on the first redistribution layer. Moreover, this embodiment can form second conductive pillars with larger spacing, larger area, and a greater number, which is more conducive to the electrical connection between the second conductive pillars and other structures.

[0096] Example 3: In Example 3, only the differences from Example 1 are described, and the similarities with Example 1 will not be repeated.

[0097] In this embodiment, the first rewiring structure includes a first rewiring layer electrically connected to the first pad, the first rewiring layer including a plurality of first conductive traces, and each first pad being electrically connected to one of the first conductive traces. Prior to step 180 of stripping the second substrate, the wafer-based semiconductor structure board-level manufacturing method further includes: An insulating layer is formed covering the first redistribution layer; A plurality of first openings are formed on the insulating layer, each first opening exposing a portion of a first conductive trace.

[0098] This step yields the following result: Figure 30 The eighteenth intermediate structure shown, Figure 30 This is a magnified view of a portion of the eighteenth intermediate structure. (See image below.) Figure 30 As shown, a first opening 171 is formed on the insulating layer 17 to expose the first conductive trace 161. The first opening 171 can correspond one-to-one with the first conductive trace 161, and each first opening 171 exposes the corresponding first conductive trace 161.

[0099] In one embodiment, the minimum spacing between adjacent first pads 15 is less than the minimum spacing between the first openings 171 corresponding to the two first conductive traces 161 connected to them. This arrangement helps to reduce the accuracy requirements of the subsequently formed second rewiring structure. In one embodiment, the dicing of the semiconductor intermediate structure to obtain a plurality of semiconductor structures includes an insulating layer 17. After step 180 of dicing the semiconductor intermediate structure to obtain a plurality of semiconductor structures, the wafer-based board-level manufacturing method for the semiconductor structure further includes: First, the plurality of semiconductor structures are mounted on a fourth substrate, with the first opening facing the fourth substrate; the fourth substrate is a panel-level substrate.

[0100] This step yields the following result: Figure 31 The nineteenth intermediate structure shown. (As shown) Figure 31 As shown, multiple semiconductor structures can be mounted on the fourth carrier 24 via the adhesive layer 25. The adhesive layer 25 can be made of an easily peelable material so that the first carrier 20 can be subsequently peeled off from other structures. For example, the adhesive layer 25 can be made of a thermally desiccant that can be de-adhesive by heating.

[0101] Subsequently, a third molding layer is formed, which at least covers the sidewalls of the semiconductor structure.

[0102] This step yields the following result: Figure 32 The twentieth intermediate structure is shown. (Example) Figure 32 As shown, the third molding layer 18 covers the side of the semiconductor structure and the surface of the semiconductor structure opposite to the first opening 171.

[0103] In one embodiment, the third molding layer 18 can be a polymer, resin, resin composite material, or polymer composite material. For example, the third molding layer 18 can be a resin with fillers, wherein the fillers are inorganic particles. The third molding layer 18 can be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0104] Subsequently, the fourth carrier plate is peeled off to obtain the second encapsulated structure.

[0105] In one embodiment, the fourth carrier plate 24 can be directly and mechanically peeled off from the third molding layer 18 and the insulating layer 17. In other embodiments, the third molding layer 18 and the insulating layer 17 are bonded to the fourth carrier plate 24 by an adhesive layer 25. When the material of the adhesive layer 25 is a heat-removing material, the adhesive layer can be heated to reduce its stickiness, thereby allowing the fourth carrier plate 24 to be peeled off.

[0106] Subsequently, a second rewiring structure is formed on the surface of the third molding layer near the first opening, and the second rewiring structure is electrically connected to the first rewiring structure through the first opening.

[0107] In one embodiment, before forming the second rewiring structure, the second molding layer can be first mounted on a sixth carrier board, which is a panel-level carrier board. The sixth carrier board can provide support for the second molding structure. Since the sixth carrier board is a panel-level carrier board, panel-level equipment can be used to form the second rewiring structure.

[0108] After mounting the second molding structure onto the sixth substrate and forming the second rewiring structure, the following can be obtained: Figure 33 The twenty-first intermediate structure is shown. (See example...) Figure 33 As shown, the third molding layer 18 is attached to the sixth carrier board 26 via the adhesive layer 27; the second redistribution structure 19 includes a second conductive trace 191 and a second conductive post 192 located on the side of the second conductive trace 191 facing away from the first chip 11. Each second conductive trace 191 may have a second conductive post 192 formed on it, and each second conductive trace 191 is electrically connected to a first conductive trace 161 through a conductive part 172 in a first opening 171.

[0109] In one embodiment, the conductive portion 172 and the second conductive trace 191 can be formed in the same process step. This allows both the conductive portion 172 and the second conductive trace 191 to be formed simultaneously in a single process step, simplifying the semiconductor packaging process. In other embodiments, the conductive portion 172 and the second conductive trace 191 may not be formed simultaneously; the conductive portion 172 may be formed first, followed by the second conductive trace 191.

[0110] In one embodiment, the conductive portion 172, the second conductive trace 191, and the second conductive post 192 can be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The materials of the conductive portion 172, the second conductive trace 191, and the second conductive post 192 can be metallic materials, such as copper.

[0111] In one embodiment, after forming the second redistribution structure, the semiconductor structure manufacturing method may further include: forming an insulating material layer covering the second redistribution structure, wherein the surface of the second conductive pillar exposes the insulating material layer. After forming the insulating material layer, a structure as follows can be obtained: Figure 34 The twenty-second intermediate structure shown.

[0112] like Figure 34 As shown, the insulating material layer 193 covers the second redistribution structure 19, the exposed insulating layer 17, and the exposed third molding compound 18. The second conductive post 192 faces away from the surface of the first chip 11, exposing the insulating material layer 193. The insulating material layer 193 protects the second redistribution structure 19.

[0113] The distance from the side of the insulating material layer 193 away from the first chip 11 is approximately the same as the distance from the side of the second conductive post 192 away from the first chip 11, so that the surface of the second conductive post 192 just exposes the insulating material layer 193. During the formation of the insulating material layer 193, the initially formed insulating material layer 193 can cover the surface and sides of the second conductive post 192. Subsequently, the insulating material layer 193 is thinned to expose the surface of the second conductive post 192 away from the first chip 11.

[0114] In one embodiment, the orthographic projection of the second conductive post 192 onto the surface of the first chip 11 opposite to the second conductive post 192 is located outside the first chip 11. And / or, the minimum spacing between adjacent second conductive posts 192 is greater than the minimum spacing between adjacent first openings 171. And / or, the number of second conductive posts 192 is greater than the number of first openings 171. This arrangement facilitates the connection of the second conductive posts 192 to other structures.

[0115] In one embodiment, after the step of forming the insulating material layer covering the second redistribution structure, the board-level manufacturing method of the wafer-based semiconductor structure further includes: The sixth substrate was peeled off to obtain the semiconductor packaging structure; The obtained semiconductor package structure is cut to obtain multiple substructures, each of which includes at least one first chip.

[0116] This step yields the following result: Figure 35 The substructure shown. For example... Figure 35 As shown, the substructure includes a first chip 11.

[0117] In this embodiment, the conductive portion 172 and the second conductive trace 191 can be formed in the same process step, which helps to simplify the manufacturing process.

[0118] Example 4 In Example 4, only the differences from Example 1 are described, and the similarities with Example 1 will not be repeated.

[0119] In this embodiment, prior to step 150 of forming the first molding layer, the wafer-based semiconductor structure board-level manufacturing method further includes the following steps: The side of the wafer facing away from the first bonding pad is thinned to expose the gap.

[0120] The above steps can yield the following result: Figure 36 The twenty-third intermediate structure is shown. (Example) Figure 36 As shown, gap 12 exposes the surface of wafer 10 away from protective layer 13, and gap 12 penetrates wafer 10. Multiple first chips 11 of the same wafer 10 are bonded together by protective layer 13.

[0121] In one embodiment, after the step of thinning the side of the wafer away from the first bonding pad to expose the gap, the board-level manufacturing method of the wafer-based semiconductor structure further includes: A metal layer is formed on the side of the wafer opposite to the protective layer.

[0122] This step yields the following result: Figure 37 The twenty-fourth intermediate structure is shown. (Example) Figure 37 As shown, metal layer 32 covers the surface of wafer 10 away from protective layer 13.

[0123] In one embodiment, the metal layer 32 can be formed by coating a silver paste or copper paste onto the surface of the wafer 10 away from the protective layer 13. Alternatively, a DAF film (Die Attach Film) can be attached to the surface of the wafer 10 away from the protective layer 13.

[0124] In one embodiment, the metal layer 32 does not cover the gap 12, that is, the metal layer 32 is a patterned film layer. Or, as Figure 37 As shown, the metal layer 32 covers the gap 12, and the metal layer 32 forms a recess 321 at the gap 12.

[0125] In this embodiment, prior to step 150 of forming the first molding layer, the wafer-based semiconductor structure board-level manufacturing method further includes the following steps: Using the gap as an alignment marker, multiple second chips are mounted on the side of the wafer away from the first bonding pad, and a second chip is provided on the back side of each first chip; the surface of the second chip away from the first chip is provided with a second bonding pad.

[0126] This step yields the following result: Figure 38 The twenty-fifth intermediate structure is shown. (Example) Figure 38 As shown, each of the first chips 11 has a second chip 33 on its back side. By using the gap 12 as an alignment mark, the mounting accuracy of the second chip 33 can be improved, avoiding misalignment of the second chip 33 and thus improving the mounting accuracy of the second chip 33.

[0127] In one embodiment, when the material of the metal layer 32 is copper paste or silver paste, after the step of mounting multiple second chips on the side of the wafer away from the first bonding pad, the board-level manufacturing method of the wafer-based semiconductor structure further includes: curing the metal layer 32, and mounting the second chips onto the wafer using the silver paste or copper paste. By curing the metal layer 32, the second chips 33 can be more firmly fixed on the metal layer 32.

[0128] In one embodiment, when the metal layer covers the gap and the metal layer forms a recess in the gap, the step of mounting a plurality of second chips on the side of the wafer away from the first pad, using the gap as an alignment marker, includes: mounting a plurality of second chips on the side of the wafer away from the first pad, using the recess formed by the metal layer in the gap as an alignment marker.

[0129] In this embodiment, step 140 can yield the following result: Figure 39 The twenty-sixth intermediate structure is shown. (Example) Figure 39 The wafer 10 is attached to the first carrier 20 via an adhesive layer 21. The adhesive layer 21 can be made of an easily peelable material so that the first carrier 20 can be subsequently separated from the wafer 10. For example, the adhesive layer 21 can be made of a thermally desiccant that can be heated to lose its adhesiveness. The second chip 33 is positioned away from the first carrier 20.

[0130] In this embodiment, step 150 can yield the following result: Figure 40 The twenty-seventh intermediate structure is shown. (See example...) Figure 40 As shown, the first molding compound 14 covers the side of the wafer 10 and the second chip 33, as well as the surface of the second chip 33 that is away from the first chip 11, and the second chip 33 is not exposed by the first molding compound 14.

[0131] In this embodiment of the application, step 160 can yield the following result: Figure 41 The twenty-eighth intermediate structure shown. (Example) Figure 41 As shown, the first molding compound includes a wafer 10 and a second chip 33. The first molding compound is attached to the second substrate 22 by an adhesive layer 23. The adhesive layer 23 can be made of an easy-to-peel material so that the second substrate 22 can be peeled off from the first molding compound 14 in the future. For example, the adhesive layer can be made of a heat-removing material that can lose its stickiness by heating.

[0132] In the embodiments of this application, when... Figure 41 After forming multiple through holes 131 on the protective layer 13 of the 28th intermediate structure shown, the result is as follows: Figure 42 and Figure 43 The twenty-ninth intermediate structure shown, Figure 43 This is a magnified view of a portion of the intermediate structure of the twenty-ninth section. (See image below.) Figure 42 and Figure 43 As shown, a plurality of through holes 131 are formed on the protective layer 13, and each through hole 131 exposes a first solder pad 15.

[0133] In this embodiment of the application, step 170 can yield the following result: Figure 44 The thirtieth intermediate structure shown is Figure 44 This is a magnified view of a portion of the thirtieth intermediate structure. (See image below.) Figure 30As shown, the first redistribution structure 16 includes a first redistribution layer and a first conductive post 162. The first redistribution layer includes a plurality of first conductive traces 161. Each first pad 15 is electrically connected to one of the first conductive traces 161. Each first conductive trace 161 has a first conductive post 162 on the side away from the first chip 11. The first conductive trace 161 is electrically connected to the first pad 15 through a conductive part 132 located in the via 131.

[0134] In this embodiment of the application, step 190 can yield the following result: Figure 45 The semiconductor structure shown. Figure 44 As shown, the semiconductor structure includes the first chip 11 and the second chip 33.

[0135] In one embodiment, after step 190 of cutting the semiconductor intermediate structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes the following steps: First, the plurality of semiconductor structures are mounted on a fifth carrier board, with the first redistribution structure facing away from the fifth carrier board; the fifth carrier board is a panel-level carrier board.

[0136] This step yields the following result: Figure 46 The thirty-first intermediate structure shown. (Example) Figure 46 As shown, the semiconductor structure is mounted on the fifth substrate 41 via an adhesive layer 42. The fifth substrate 41 provides support for the semiconductor structure, facilitating further encapsulation of the semiconductor structure using panel-level equipment.

[0137] Subsequently, a fourth molding layer is formed, which at least covers the side surface of the semiconductor structure.

[0138] This step yields the following result: Figure 47 The thirty-second intermediate structure is shown. (Example) Figure 47 As shown, the fourth molding layer 43 covers the side of the semiconductor structure and the surface of the semiconductor structure facing away from the fifth substrate 41, and the first conductive post 162 of the first redistribution structure 16 is exposed in the fourth molding layer 43.

[0139] In one embodiment, the initially formed fourth molding compound 43 may cover the surface of the first conductive post 162 facing away from the first chip 11. By thinning the fourth molding compound 43, the surface of the first conductive post 162 facing away from the first chip 11 is exposed. The fourth molding compound 43 may be thinned by grinding.

[0140] Subsequently, a third rewiring structure is formed on the side of the fourth molding layer opposite to the fifth substrate. The third rewiring structure is electrically connected to the first rewiring structure, and the orthographic projection of the third rewiring structure on the fifth substrate is located outside the orthographic projection of the first chip on the fifth substrate.

[0141] This step yields the following result: Figure 48 The thirty-third intermediate structure shown. (Example) Figure 48 As shown, the third redistribution structure 44 includes a third redistribution layer and third conductive pillars 442. The third redistribution layer includes a plurality of third conductive traces 441, and each third conductive trace 441 is provided with a third conductive pillar 442 opposite to the surface of the first chip 11. Each third conductive trace 441 is in direct contact with a first conductive pillar 162. The portion of the third conductive trace 441 and the portion of the third conductive pillar 442 projected onto the fifth carrier 41 are located outside the projected portion of the first chip 11 onto the fifth carrier 41.

[0142] In one embodiment, after the step of forming the third redistribution structure, the board-level manufacturing method of the wafer-based semiconductor structure further includes: forming an insulating film layer that covers the third redistribution structure, and exposing the insulating film layer away from the surface of the first chip.

[0143] This step yields the following result: Figure 49 The thirty-fourth intermediate structure is shown. (Example) Figure 49 As shown, the insulating film layer 49 covers the exposed sides of the fourth molding layer 43, the third conductive trace 441, and the third conductive post 442. The third conductive post 442 is exposed away from the surface of the first chip 11, where the insulating film layer 49 is exposed. The insulating film layer 49 protects the third redistribution structure 44.

[0144] Subsequently, the fifth substrate is peeled off, and a second opening is formed on the fourth molding layer to expose a portion of the first redistribution structure.

[0145] In one embodiment, after peeling off the fifth carrier board, the resulting encapsulation structure can be mounted on the seventh carrier board, with the third rewiring structure facing the seventh carrier board; the seventh carrier board is a panel-level carrier board. This step yields the following... Figure 50 The thirty-fifth intermediate structure is shown. (Example) Figure 50 As shown, the insulating film layer 45 is attached to the seventh carrier board 46 via the adhesive layer 47. The seventh carrier board 46 serves as a support, and since it is a panel-level carrier board, it can be further encapsulated using panel-level equipment.

[0146] In one embodiment, after the package structure obtained by peeling off the fifth substrate is mounted onto the seventh substrate, the wafer-based semiconductor structure board-level manufacturing method further includes: forming a third opening on the first molding compound to expose a portion of the metal layer.

[0147] In one embodiment, after the package structure obtained by peeling off the fifth substrate is mounted onto the seventh substrate, the board-level manufacturing method of the wafer-based semiconductor structure further includes: forming a fourth opening on the first molding compound to expose the second bonding pad.

[0148] After forming the second, third, and fourth openings, the following can be obtained: Figure 51 The thirty-sixth intermediate structure is shown. (Example) Figure 51 As shown, the second opening 431 exposes a portion of the third conductive trace 441 of the third redistribution structure 44, the third opening 141 exposes a portion of the metal layer 32, and the fourth opening 142 exposes the pads of the second chip 33.

[0149] In one embodiment, the second opening 431, the third opening 141, and the fourth opening 142 can be formed by etching the molding compound.

[0150] Subsequently, a first connecting post is formed within the second opening, and a fourth rewiring structure is formed on the surface of the first molding layer opposite to the first chip. The fourth rewiring structure is electrically connected to the third rewiring structure through the first connecting post, and the fourth rewiring structure is electrically connected to the second pad.

[0151] In one embodiment, the wafer-based semiconductor structure board-level manufacturing method further includes: forming a second connecting post located within the third opening and a heat sink located on the second connecting post away from the first chip, the heat sink being electrically connected to the metal layer through the second connecting post.

[0152] After forming the first connecting post, the fourth rewiring structure, the second connecting post, and the heat sink, the following can be obtained: Figure 52 The thirty-seventh intermediate structure is shown. (See example...) Figure 52 As shown, one end of the first connecting post 51 located in the second opening 431 is electrically connected to the third redistribution structure 44, and the other end is electrically connected to the fourth redistribution structure 54 located on the side of the first molding layer 14 away from the first chip 11; one end of the second connecting post 52 located in the third opening 141 is electrically connected to the metal layer 32, and the other end is electrically connected to the heat sink 55; the fourth redistribution structure 54 is electrically connected to the second pad of the second chip 33 through the third connecting post 53 located in the fourth opening 142.

[0153] That is, the second pad of the second chip 33 is electrically connected to the first pad 15 of the first chip 11 via the third connecting post 53, the fourth redistribution structure 54, the first connecting post 51, the third redistribution structure 44, and the first redistribution structure 16, thereby realizing the interconnection between the first chip 11 and the second chip 33. The heat sink 55 is electrically connected to the metal layer 32 via the second connecting post 52. The metal layer 32 is located between the back of the first chip 11 and the back of the second chip 33. The heat generated by the first chip 11 and the second chip 33 can be conducted to the heat sink 55 through the metal layer 32, and then the heat sink 55 dissipates the heat.

[0154] In one embodiment, a conductive contact layer 54 is formed between the heat sink 55 and the first molding compound 14, and the heat sink 55 is electrically connected to the second connecting post 52 through the conductive contact layer 54. The fourth redistribution structure may include a plurality of fourth conductive traces, and the conductive contact layer 54 and the fourth conductive traces may be formed simultaneously.

[0155] In one embodiment, after forming the heat sink 55, the board-level manufacturing method of the wafer-based semiconductor structure further includes: forming an insulating material film layer covering the heat sink and the fourth redistribution structure.

[0156] This step yields the following result: Figure 53 The thirty-eighth intermediate structure shown. (Example) Figure 53 As shown, the insulating material film 57 covers the heat sink 55, the fourth redistribution structure 54, the exposed first molding compound 14 and the exposed fourth molding compound 43, and the insulating material film 57 is exposed on the surface of the heat sink 55 away from the first chip 11.

[0157] In one embodiment, after the step of forming the insulating material film layer, the wafer-based semiconductor structure board-level manufacturing method further includes the following steps: The semiconductor packaging structure was obtained by peeling off the seventh substrate; The semiconductor package structure is cut to obtain multiple substructures, each substructure including at least one first chip and at least one second chip.

[0158] The above steps can yield the following result: Figure 54 The substructure shown. For example... Figure 54 As shown, the substructure includes a first chip 11 and a second chip 33.

[0159] In one embodiment, the second chip 33 may be an unpackaged chip, a packaged chip, or a passive device.

[0160] The wafer-based semiconductor structure board-level manufacturing method provided in this application uses the gap as an alignment mark when mounting the second chip, which can improve the mounting accuracy of the second chip and avoid the second chip from shifting. It also realizes the simultaneous packaging of multiple chips and the interconnection of different chips. By setting a heat sink and a metal layer, the metal layer conducts the heat generated by the first chip 11 and the second chip 33 to the heat sink, and then the heat sink dissipates the heat, which helps to improve the performance of the semiconductor structure.

[0161] It should be noted that the accompanying drawings provided in this application are only schematic and may differ from the actual structure. For example, some drawings do not show the solder pads on the front of the chip, but in reality, the solder pads on the front of the chip are electrically connected to the redistribution structure.

[0162] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0163] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0164] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A wafer-based semiconductor structure board-level manufacturing method, characterized in that, include: A plurality of wafers and a first substrate are provided, wherein the wafers include a plurality of interconnected first chips and a plurality of first pads are provided on the front side of the first chips; The wafer is cut on the side closest to the first bonding pad to create a gap between adjacent first chips, the depth of which is less than the thickness of the wafer. A protective layer is formed on the side of the wafer near the first bonding pad, and the material of the protective layer enters into the gap; The plurality of wafers are mounted on the first carrier board, with the protective layer facing the first carrier board; the first carrier board is a panel-level carrier board. A first molding compound is formed, wherein the first molding compound covers at least one side of the wafer; Peel off the first carrier plate to obtain the first encapsulated structure, and attach the first encapsulated structure to the second carrier plate, with the protective layer facing away from the second carrier plate; A first rewiring structure is formed on the protective layer to bring out the first solder pad; The second substrate is peeled off to obtain the semiconductor intermediate structure; The semiconductor intermediate structure is cut to obtain multiple semiconductor structures, each semiconductor structure including at least one of the first chips.

2. The wafer-based semiconductor structure board-level manufacturing method according to claim 1, characterized in that, The first rewiring structure includes a first rewiring layer electrically connected to the first pad and a first conductive post located on the side of the first rewiring layer away from the first chip; the first rewiring layer includes a plurality of first conductive traces, each of the first pads is electrically connected to one of the first conductive traces, and each of the first conductive traces is provided with a first conductive post on the side away from the first chip; the minimum spacing between adjacent first pads is less than the minimum spacing between two first conductive posts electrically connected to them.

3. The wafer-based semiconductor structure board-level manufacturing method according to claim 2, characterized in that, The first redistribution structure includes a first redistribution layer electrically connected to the first pad, and a first conductive post located on the side of the first redistribution layer opposite to the first chip; After cutting the semiconductor intermediate structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes: The plurality of semiconductor structures are mounted on a third carrier board, with the first conductive post facing away from the third carrier board; the third carrier board is a panel-level carrier board. A second molding compound is formed, which covers the side surface of the semiconductor structure and the surface facing away from the third substrate, and the first conductive pillar is exposed in the second molding compound. A second rewiring structure is formed on the surface of the second molding layer opposite to the first chip, and the second rewiring structure is electrically connected to the first conductive pillar. The third substrate is peeled off to obtain a semiconductor packaging structure; The semiconductor package structure is cut to obtain multiple substructures, each of which includes at least one of the first chips.

4. The wafer-based semiconductor structure board-level manufacturing method according to claim 3, characterized in that, The second redistribution structure includes a second redistribution layer and a second conductive post located on the side of the second redistribution layer opposite to the first chip; the orthographic projection of the second conductive post on the surface of the first chip opposite to the second conductive post is located outside the first chip; And / or, the minimum spacing between adjacent second conductive posts is greater than the minimum spacing between adjacent first conductive posts; And / or, the number of the second conductive pillars is greater than the number of the first conductive pillars.

5. The wafer-based semiconductor structure board-level manufacturing method according to claim 1, characterized in that, The first rewiring structure includes a first rewiring layer electrically connected to the first pad, the first rewiring layer including a plurality of first conductive traces, and each of the first pads being electrically connected to one of the first conductive traces; Before stripping the second carrier substrate, the wafer-based semiconductor structure board-level manufacturing method further includes: An insulating layer is formed covering the first redistribution layer; A plurality of first openings are formed on the insulating layer, each first opening exposing a portion of a first conductive trace; the minimum spacing between adjacent first pads is less than the minimum spacing between the first openings corresponding to two first conductive traces connected to them. After cutting the semiconductor intermediate structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes: The plurality of semiconductor structures are mounted on a fourth substrate, with the first opening facing the fourth substrate; the fourth substrate is a panel-level substrate. A third molding compound is formed, the third molding compound covering at least the side surface of the semiconductor structure; Peel off the fourth carrier plate to obtain the second encapsulated structure; A second rewiring structure is formed on the surface of the third molding layer near the first opening, and the second rewiring structure is electrically connected to the first rewiring structure through the first opening.

6. The wafer-based semiconductor structure board-level manufacturing method according to claim 1, characterized in that, Before forming the first molding compound, the wafer-based semiconductor structure board-level manufacturing method further includes: using the gap as an alignment mark, mounting a plurality of second chips on the side of the plurality of wafers away from the first bonding pad, with a second chip respectively provided on the back side of each first chip; and providing a second bonding pad on the surface of the second chip away from the first chip. The semiconductor structure includes the first chip and the second chip; after cutting the intermediate semiconductor structure to obtain multiple semiconductor structures, the wafer-based semiconductor structure board-level manufacturing method further includes: The plurality of semiconductor structures are mounted on a fifth substrate, with the first redistribution structure facing away from the fifth substrate; the fifth substrate is a panel-level substrate. A fourth molding compound is formed, the fourth molding compound covering at least the side surface of the semiconductor structure; A third rewiring structure is formed on the side of the fourth molding layer away from the fifth substrate. The third rewiring structure is electrically connected to the first rewiring structure. The orthographic projection of the third rewiring structure on the fifth substrate is located outside the orthographic projection of the first chip on the fifth substrate. Peel off the fifth substrate and form a second opening on the fourth molding layer to expose a portion of the third redistribution structure; A first connecting post is formed within the second opening, and a fourth rewiring structure is formed on the surface of the first molding layer opposite to the first chip. The fourth rewiring structure is electrically connected to the third rewiring structure through the first connecting post, and the fourth rewiring structure is electrically connected to the second pad.

7. The wafer-based semiconductor structure board-level manufacturing method according to claim 6, characterized in that, Before forming the first molding compound layer, the wafer-based semiconductor structure board-level manufacturing method further includes: The side of the plurality of wafers facing away from the first bonding pad is thinned to expose the gap.

8. The wafer-based semiconductor structure board-level manufacturing method according to claim 7, characterized in that, After thinning the side of the plurality of wafers away from the first bonding pad to expose the gap, the wafer-based semiconductor structure board-level manufacturing method further includes: A metal layer is formed on the side of the plurality of wafers opposite to the protective layer; the second chip is mounted on the metal layer; After the fifth substrate is stripped, the wafer-based semiconductor structure board-level manufacturing method further includes: A third opening is formed on the first molding layer to expose a portion of the metal layer; A second connecting post is formed within the third opening, and a heat sink is formed on the second connecting post away from the first chip. The heat sink is electrically connected to the metal layer through the second connecting post.

9. The wafer-based semiconductor structure board-level manufacturing method according to claim 8, characterized in that, The metal layer does not cover the gap; or... The metal layer covers the gap, and the metal layer forms a recess in the gap; Using the gap as an alignment marker, multiple second chips are mounted on the side of the plurality of wafers opposite to the first bonding pad, including: Using the recess formed by the metal layer at the gap as an alignment mark, a plurality of second chips are mounted on the side of the plurality of wafers away from the first bonding pad.

10. The wafer-based semiconductor structure board-level manufacturing method according to claim 8, characterized in that, The material of the metal layer is silver paste or copper paste; After mounting multiple second chips on the side of the plurality of wafers away from the first bonding pad, the wafer-based semiconductor structure board-level manufacturing method further includes: The silver paste or copper paste is cured, and the second chip is mounted on the plurality of wafers using the silver paste or copper paste.

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