Power device termination region structure and method of fabrication thereof

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a power device terminal region structure and a manufacturing method thereof. The manufacturing method of the power device terminal region structure comprises the following steps: providing a base layer of a power device terminal region; forming a contact hole at a position of an active region, so that the upper surface of the base layer is exposed in the contact hole; forming an isolation layer covering the surface of an interlayer dielectric layer and the surface of the contact hole; depositing a tungsten layer on the isolation layer, so that the tungsten layer covers at least all the isolation layers in contact with the contact hole; etching back the tungsten layer to form a remaining tungsten layer, so that there is no tungsten residue on the surface of the terminal structure, there is no tungsten residue on the isolation layer at the bottom of the contact hole, and there is tungsten residue on the side wall of the contact hole due to the etching rate; depositing a supplementary isolation layer, so that the supplementary isolation layer at least completely covers in the contact hole; and depositing an aluminum layer, which at least fills the contact hole. The power device terminal region structure is formed by the above method.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit fabrication technology, specifically to a power device terminal region structure and its fabrication method. Background Technology

[0002] To achieve better power device performance, a termination structure is needed to isolate the active and non-active regions of the power device.

[0003] Typically, the terminal structure of power devices is formed using the LOCOS (Local Oxidation Of Silicon) process. This involves oxygen diffusing into the underlying silicon of the device and reacting with it to form an oxide layer. The growth characteristics of the oxide result in a surface step relative to the underlying silicon, which necessitates that the contact holes in the terminal area be large in size to avoid affecting the photolithographic focusing of the contact holes.

[0004] In the fabrication of contact holes in the terminal region of power devices, related technologies first form an isolation layer covering the inner surface of the contact hole, then form a tungsten layer covering the inner surface of the isolation layer, then etch back the tungsten layer, and finally fill the contact hole with aluminum. However, during the etch-back process of the tungsten layer, because the contact hole is large, even after the tungsten on the surface of the structure is anisotropically removed, the tungsten layer at the bottom of the contact hole is also etched away, exposing the isolation layer beneath the tungsten layer. Furthermore, the deposition of the tungsten layer may generate reactants that corrode the isolation layer to some extent, causing voids in the isolation layer in contact with the W. This results in the aluminum, when subsequently filled, contacting the isolation layer through these voids with the underlying silicon, leading to aluminum-silicon intersolution. Summary of the Invention

[0005] This application provides a power device terminal region structure and its fabrication method, which can solve the problem of aluminum-silicon intersolution in the power device terminal region structure in related technologies.

[0006] To address the technical problems described in the background art, a first aspect of this application provides a method for fabricating a power device terminal region structure, the method comprising the following steps performed sequentially:

[0007] A substrate layer is provided for the terminal region of a power device. An interlayer dielectric layer is formed on the substrate layer. The substrate layer includes an active region and an active region. A liner layer is formed between the interlayer dielectric layer and the substrate layer at the location of the active region. A thick oxide layer is formed between the interlayer dielectric layer and the substrate layer at the location of the active region. A surface step is formed between the thick oxide layer and the substrate layer.

[0008] A contact hole is formed at the location of the active region, so that the upper surface of the substrate layer is exposed in the contact.

[0009] An isolation layer is formed covering the surface of the interlayer dielectric layer and the surface of the contact hole;

[0010] A tungsten layer is deposited on the isolation layer such that the tungsten layer covers at least the isolation layer that contacts the side surface of the contact hole and the isolation layer that contacts the bottom surface of the contact hole.

[0011] The tungsten layer is etched back to form a residual tungsten layer, such that the residual tungsten layer at least covers the isolation layer that contacts the side of the contact hole;

[0012] A supplementary isolation layer is deposited such that the supplementary isolation layer at least completely covers the contact hole;

[0013] An aluminum layer is deposited to form an aluminum layer that at least fills the contact hole.

[0014] Optionally, the step of forming an isolation layer covering the surface of the interlayer dielectric layer and the surface of the contact hole includes:

[0015] First, titanium is deposited to form a titanium layer covering the surface of the interlayer dielectric layer and the surface of the contact hole;

[0016] Titanium nitride is then deposited on the titanium layer to form a first titanium nitride layer covering the titanium layer.

[0017] Optionally, in the step of first depositing titanium to form a titanium layer covering the surface of the interlayer dielectric layer and the surface of the contact hole, the thickness of the titanium layer is 400 Å to 500 Å.

[0018] Optionally, in the step of depositing titanium nitride on the titanium layer to form a first titanium nitride layer covering the titanium layer, the thickness of the first titanium nitride layer is 800 Å to 1000 Å.

[0019] Optionally, the step of depositing a supplementary isolation layer such that the supplementary isolation layer at least completely covers the contact hole includes:

[0020] Titanium nitride is deposited to form a second titanium nitride layer, such that the second titanium nitride layer at least completely covers the surface of the remaining tungsten layer at the side position of the contact hole and the surface of the isolation layer at the bottom position of the contact hole.

[0021] Optionally, in the step of depositing titanium nitride to form a second titanium nitride layer such that the second titanium nitride layer at least completely covers the surface of the remaining tungsten layer at the side position of the contact hole and the surface of the insulating layer at the bottom position of the contact hole, the thickness of the second titanium nitride layer is 200 Å to 300 Å.

[0022] To address the technical problems described in the background art, a second aspect of this application provides a power device termination region structure, characterized in that the power device termination region structure includes:

[0023] A base layer for the terminal region of a power device, an interlayer dielectric layer is formed on the base layer, the base layer includes an active region and an active region, a pad layer is formed between the interlayer dielectric layer and the base layer at the location of the active region, a thick oxide layer is formed between the interlayer dielectric layer and the base layer at the location of the active region, and a surface step is formed between the thick oxide layer and the base layer.

[0024] A contact hole is formed at the location of the active region, and the upper surface of the substrate layer is exposed in the contact hole;

[0025] An isolation layer covering the surface of the interlayer dielectric layer and the surface of the contact hole;

[0026] A tungsten layer, which covers the tungsten layer on the insulating layer that contacts the side of the contact hole;

[0027] A supplementary isolation layer covers the surface of the tungsten layer and the surface of the isolation layer at the bottom of the contact hole;

[0028] An aluminum layer that at least fills the contact hole with the supplementary insulating layer.

[0029] Optionally, the isolation layer includes a titanium layer covering the upper surface of the interlayer dielectric layer and the bottom and side surfaces of the contact hole, and a first titanium nitride layer covering the titanium layer.

[0030] Optionally, the thickness of the titanium layer ranges from 400 Å to 500 Å.

[0031] Optionally, the thickness of the first titanium nitride layer ranges from 800 Å to 1000 Å.

[0032] Optionally, the thickness of the supplementary isolation layer ranges from 200 Å to 300 Å.

[0033] The technical solution of this application has at least the following advantages: by depositing a thin supplementary isolation layer after etching back, the consumption of the isolation layer caused by the deposition of the tungsten layer and the etching back of the tungsten layer is compensated, and the isolation effect of the isolation layer on the aluminum and silicon substrate is improved, avoiding the problem of silicon-aluminum mutual solubility as described in the background art. At the same time, the thickness of the supplementary isolation layer deposited in this embodiment is relatively thin, which can avoid the problem of film peeling caused by directly depositing a thicker isolation layer, thereby improving the reliability of the device. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating a method for fabricating a power device terminal region structure according to an embodiment of this application is shown;

[0036] Figure 2 A schematic cross-sectional view of the base layer provided in step S1 is shown.

[0037] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S2 is shown;

[0038] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S3 is shown;

[0039] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S5 is shown;

[0040] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S6 is shown;

[0041] Figure 7 A cross-sectional view of the terminal region structure of a power device provided in one embodiment is shown. Detailed Implementation

[0042] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0045] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0046] Figure 1 A flowchart illustrating a method for fabricating a power device terminal region structure according to an embodiment of this application is shown. Figure 1 As can be seen from this, the fabrication method of the power device termination region structure includes the following steps performed sequentially:

[0047] Step S1: Provide a substrate layer for the power device terminal region, on which an interlayer dielectric layer is formed. The substrate layer includes an active region and an active region. A pad layer is formed between the interlayer dielectric layer and the substrate layer at the location of the active region. A thick oxide layer is formed between the interlayer dielectric layer and the substrate layer at the location of the active region. A surface step is formed between the thick oxide layer and the substrate layer.

[0048] Reference Figure 2 It shows a schematic cross-sectional view of the base layer provided in step S1, from Figure 2 As can be seen, an interlayer dielectric layer 120 is formed on the substrate layer 110. The substrate layer 110 also includes an active region 111 and an active region 112. A liner layer 130 is formed between the interlayer dielectric layer 120 and the substrate layer 110 at the location of the active region 111. A thick oxide layer 140 is formed between the interlayer dielectric layer 120 and the substrate layer 110 at the location of the active region 112. A surface step is formed between the thick oxide layer 140 and the substrate layer 100, that is, the surface of the thick oxide layer 140 of the active region 223 is higher than the surface of the substrate layer 100 of the active region 111.

[0049] For example, a pad layer 130 with a thickness ranging from 200 Å to 500 Å and a thick oxide layer 140 with a thickness ranging from 3000 Å to 5000 Å can be formed by the LOCOS process, wherein the pad layer 130 and the thick oxide layer 140 are made of silicon dioxide.

[0050] Step S2: Form a contact hole at the location of the active region, so that the upper surface of the substrate layer is exposed in the contact.

[0051] Reference Figure 3 It shows a schematic cross-sectional view of the device after step S2 is completed, from Figure 3 As can be seen, the interlayer dielectric layer 120 and the pad layer 130 are etched sequentially to form a contact hole 200 at the location of the active region 111, through which the upper surface of the substrate layer 110 is exposed. The contact hole 200 includes a bottom surface and a side surface.

[0052] Because of the surface steps described in step S1, the contact hole 200 needs to be large in size to avoid affecting the photolithographic focusing of the contact hole 200. The size of the contact hole is greater than 5um*5um.

[0053] Step S3: Form an isolation layer covering the surface of the interlayer dielectric layer and the surface of the contact hole.

[0054] Step S3 can be achieved by sequentially performing the following steps S31 and S32:

[0055] Step S31: Deposit titanium to form a titanium layer covering the surface of the interlayer dielectric layer and the surface of the contact hole.

[0056] Step S32: Deposit titanium nitride on the titanium layer to form a first titanium nitride layer covering the titanium layer.

[0057] Reference Figure 4 It shows a schematic cross-sectional view of the device after step S3 is completed, from Figure 4 As can be seen from the diagram, the isolation layer 150 includes a titanium layer 151 covering the upper surface of the interlayer dielectric layer 120 and the bottom and sides of the contact hole 200, and a first titanium nitride layer 152 covering the titanium layer 151.

[0058] The isolation layer 150 is located between the substrate layer 110 and the subsequently formed aluminum layer, and serves to isolate the substrate layer 110 and the aluminum layer, so as to prevent silicon-aluminum intersolution between the silicon substrate layer and aluminum, which would affect the reliability of the active region extraction.

[0059] For example, the thickness of the titanium layer 151 in this embodiment can be in the range of 400 Å to 500 Å, and the thickness of the first titanium nitride layer 152 can be in the range of 800 Å to 1000 Å.

[0060] Step S4: Deposit a tungsten layer on the isolation layer such that the tungsten layer covers at least the isolation layer that contacts the side surface of the contact hole and the isolation layer that contacts the bottom surface of the contact hole.

[0061] During the process of depositing a tungsten layer on the isolation layer, the tungsten layer consumes the isolation layer, which may create voids in the isolation layer.

[0062] Step S5: Etch back the tungsten layer to form a residual tungsten layer, such that the residual tungsten layer at least covers the isolation layer that contacts the side of the contact hole.

[0063] Reference Figure 5 It shows a schematic cross-sectional view of the device after step S5 is completed, from Figure 5 It can be seen that the remaining tungsten layer 300 after etching covers the isolation layer 150 that contacts the side of the contact hole 200.

[0064] Because the contact holes in the terminal area of ​​the power device need to be large, that is, the bottom plane size of the contact hole is large, the etching rate of the tungsten layer on the bottom surface of the contact hole is greater than that of the tungsten layer on the side surface of the contact hole during the tungsten layer back etching. Therefore, after the tungsten layer back etching step is completed, the remaining tungsten layer covers the isolation layer on the side surface of the contact hole, making the isolation layer on the bottom surface of the contact hole exposed. Furthermore, there may be voids in the exposed isolation layer due to consumption. If aluminum is directly filled into the contact hole after step S5, aluminum may directly contact the silicon substrate through the voids in the isolation layer, causing silicon-aluminum intersolubility, which is detrimental to the reliability of the device.

[0065] Step S6: Deposit a supplementary isolation layer such that the supplementary isolation layer at least completely covers the contact hole.

[0066] Step S6 can be completed by depositing titanium nitride to form a second titanium nitride layer, such that the second titanium nitride layer at least completely covers the surface of the remaining tungsten layer at the side position of the contact hole and the surface of the isolation layer at the bottom position of the contact hole.

[0067] Reference Figure 6 It shows a schematic cross-sectional view of the device after step S6 is completed, from Figure 6 As can be seen, the deposited supplementary isolation layer 153 covers the contact hole, that is, it covers the surface of the remaining tungsten layer 300 in the contact hole and the surface of the isolation layer 150 exposed in the contact hole. The supplementary isolation layer 153 also covers the surface of the isolation layer 150 outside the contact hole.

[0068] For example, the thickness of the deposited supplementary isolation layer 153 can range from 200 Å to 300 Å.

[0069] Step S7: Deposit an aluminum layer that at least fills the contact hole.

[0070] Reference Figure 7 It shows a schematic cross-sectional view of the device after step S7 is completed, from Figure 7 As can be seen, the aluminum layer 400 fills the contact hole with the supplementary isolation layer 153.

[0071] In this embodiment, a thin supplementary isolation layer is deposited after the etch-back process to compensate for the consumption of the isolation layer caused by the deposition of the tungsten layer and the etch-back process, and to enhance the isolation effect of the isolation layer on the aluminum and silicon substrates, thereby avoiding the silicon-aluminum miscibility problem described in the background art. At the same time, the thin thickness of the supplementary isolation layer deposited in this embodiment can avoid the problem of film peeling caused by directly depositing a thicker isolation layer, thus improving the reliability of the device.

[0072] This application also provides a power device termination region structure, which is composed of... Figure 1 The power device terminal region structure shown is fabricated using the method described.

[0073] Continue to refer to Figure 7 It also shows a cross-sectional view of the power device terminal region structure provided in one embodiment, from Figure 7 As can be seen from this, the terminal region structure of this power device includes:

[0074] A base layer 110 is formed in the terminal region of the power device. An interlayer dielectric layer 120 is formed on the base layer 110. The base layer 110 includes an active region 111 and an active region 112. A pad layer 130 is formed between the interlayer dielectric layer 120 and the base layer 110 at the location of the active region 111. A thick oxide layer 140 is formed between the interlayer dielectric layer 120 and the base layer 110 at the location of the active region 112. A surface step is formed between the thick oxide layer 140 and the base layer 110.

[0075] A contact hole is formed at the location of the active region 111, and the upper surface of the base layer 110 is exposed in the contact hole.

[0076] An isolation layer 150 covers the surface of the interlayer dielectric layer 120 and the surface of the contact hole;

[0077] A tungsten layer 300 covers the isolation layer 150 that contacts the side of the contact hole.

[0078] A supplementary isolation layer 153 is provided, which covers the surface of the tungsten layer 300 and the surface of the isolation layer 150 at the bottom of the contact hole.

[0079] Aluminum layer 400, which at least fills the contact hole with the supplementary isolation layer 153.

[0080] Exemplarily, the isolation layer 150 includes a titanium layer 151 covering the upper surface of the interlayer dielectric layer 120 and the bottom and side surfaces of the contact hole 200, and a first titanium nitride layer 152 covering the titanium layer 151. The supplementary isolation layer 153 may be made of titanium nitride. The thickness of the titanium layer ranges from 400 Å to 500 Å, the thickness of the first titanium nitride layer ranges from 800 Å to 1000 Å, and the thickness of the supplementary isolation layer ranges from 200 Å to 300 Å.

[0081] In this embodiment, a thin supplementary isolation layer is deposited after the etch-back process to compensate for the consumption of the isolation layer caused by the deposition of the tungsten layer and the etch-back process, and to enhance the isolation effect of the isolation layer on the aluminum and silicon substrates, thereby avoiding the silicon-aluminum miscibility problem described in the background art. At the same time, the thin thickness of the supplementary isolation layer deposited in this embodiment can avoid the problem of film peeling caused by directly depositing a thicker isolation layer, thus improving the reliability of the device.

[0082] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a power device terminal region structure, characterized in that, The method for fabricating the power device terminal region structure includes the following steps performed sequentially: A substrate layer is provided for the terminal region of a power device. An interlayer dielectric layer is formed on the substrate layer. The substrate layer includes an active region and an active region. A liner layer is formed between the interlayer dielectric layer and the substrate layer at the location of the active region. A thick oxide layer is formed between the interlayer dielectric layer and the substrate layer at the location of the active region. A surface step is formed between the thick oxide layer and the substrate layer. A contact hole is formed at the location of the active region, so that the upper surface of the substrate layer is exposed in the contact. An isolation layer is formed covering the surface of the interlayer dielectric layer and the surface of the contact hole; A tungsten layer is deposited on the isolation layer such that the tungsten layer covers at least the isolation layer that contacts the side surface of the contact hole and the isolation layer that contacts the bottom surface of the contact hole; The tungsten layer is etched back to form a residual tungsten layer, such that the residual tungsten layer at least covers the isolation layer that contacts the side of the contact hole; A supplementary isolation layer is deposited such that the supplementary isolation layer at least completely covers the contact hole; An aluminum layer is deposited to form an aluminum layer that at least fills the contact hole.

2. The method for fabricating the power device terminal region structure as described in claim 1, characterized in that, The step of forming an isolation layer covering the surface of the interlayer dielectric layer and the surface of the contact hole includes: First, titanium is deposited to form a titanium layer covering the surface of the interlayer dielectric layer and the surface of the contact hole; Titanium nitride is then deposited on the titanium layer to form a first titanium nitride layer covering the titanium layer.

3. The method for fabricating the power device terminal region structure as described in claim 2, characterized in that, In the step of first depositing titanium to form a titanium layer covering the surface of the interlayer dielectric layer and the surface of the contact hole, the thickness of the titanium layer is 400 Å to 500 Å.

4. The method for fabricating the power device terminal region structure as described in claim 2, characterized in that, In the step of depositing titanium nitride on the titanium layer to form a first titanium nitride layer covering the titanium layer, the thickness of the first titanium nitride layer is 800 Å to 1000 Å.

5. The method for fabricating the power device terminal region structure as described in claim 1, characterized in that, The step of depositing a supplementary isolation layer, such that the supplementary isolation layer at least completely covers the contact hole, includes: Titanium nitride is deposited to form a second titanium nitride layer, such that the second titanium nitride layer at least completely covers the surface of the remaining tungsten layer at the side position of the contact hole and the surface of the isolation layer at the bottom position of the contact hole.

6. The method for fabricating the power device terminal region structure as described in claim 5, characterized in that, In the step of depositing titanium nitride to form a second titanium nitride layer such that the second titanium nitride layer at least completely covers the surface of the remaining tungsten layer at the side position of the contact hole and the surface of the isolation layer at the bottom position of the contact hole, the thickness of the second titanium nitride layer is 200 Å to 300 Å.

7. A power device termination region structure, characterized in that, The power device terminal region structure includes: A base layer for the terminal region of a power device, an interlayer dielectric layer is formed on the base layer, the base layer includes an active region and an active region, a pad layer is formed between the interlayer dielectric layer and the base layer at the location of the active region, a thick oxide layer is formed between the interlayer dielectric layer and the base layer at the location of the active region, and a surface step is formed between the thick oxide layer and the base layer. A contact hole is formed at the location of the active region, and the upper surface of the substrate layer is exposed in the contact hole; An isolation layer covering the surface of the interlayer dielectric layer and the surface of the contact hole; A tungsten layer, which covers the tungsten layer on the insulating layer that contacts the side of the contact hole; A supplementary isolation layer covers the surface of the tungsten layer and the surface of the isolation layer at the bottom of the contact hole; An aluminum layer that at least fills the contact hole with the supplementary insulating layer.

8. The power device termination region structure as described in claim 7, characterized in that, The isolation layer includes a titanium layer covering the upper surface of the interlayer dielectric layer and the bottom and side surfaces of the contact hole, and a first titanium nitride layer covering the titanium layer.

9. The power device termination region structure as described in claim 8, characterized in that, The thickness of the titanium layer ranges from 400 Å to 500 Å.

10. The power device termination region structure as described in claim 8, characterized in that, The thickness of the first titanium nitride layer ranges from 800 Å to 1000 Å.

11. The power device termination region structure as described in claim 7, characterized in that, The thickness of the supplementary isolation layer ranges from 200 Å to 300 Å.

Images