Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method. The method comprises the following steps: providing a substrate; forming a first epitaxial layer of a first conductive type and a second epitaxial layer of a second conductive type on one side surface of the substrate; etching the second epitaxial layer to form a patterned epitaxial layer and a first groove; forming a covering layer of the first conductive type covering the second epitaxial layer and the exposed first epitaxial layer; forming a second groove corresponding to the first groove; forming a sacrifice layer in the second groove; performing ion implantation on the covering layer based on the sacrifice layer to form an initial body region and an initial source region; forming a patterned mask layer; performing ion implantation on the covering layer based on the patterned mask layer to form an isolation layer; the isolation layer separates the initial body region into a plurality of body regions and separates the initial source region into a plurality of source regions; and removing the patterned mask layer and the sacrifice layer. The method provided by the application can improve the morphology quality of the semiconductor structure, and reduce the preparation difficulty and the preparation cost.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Technology

[0002] Trench semiconductor devices can increase the device density per unit wafer area, and compared with planar semiconductor devices, they have better performance and lower manufacturing costs, making them highly favored by the market.

[0003] However, during the etching process to form trenches, the surface of the trenches is damaged, resulting in defects. Furthermore, as the critical dimensions of semiconductors continue to shrink, etching trenches with high aspect ratios becomes increasingly difficult. These problems hinder the further development of trench-type semiconductor devices. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its preparation method to address the above-mentioned technical problems, which can improve the morphological quality of the semiconductor structure and further reduce the preparation difficulty and cost.

[0005] On the one hand, some embodiments of this application provide a method for preparing a semiconductor structure, including the following steps.

[0006] Provide substrate;

[0007] A first epitaxial layer of a first conductivity type is formed on one side surface of the substrate;

[0008] A second epitaxial layer of a second conductivity type is formed on the surface of the first epitaxial layer opposite to the substrate;

[0009] The second epitaxial layer is etched to form a patterned epitaxial layer, in which a first trench is formed, and the first trench penetrates the patterned epitaxial layer along the thickness direction;

[0010] A capping layer of the first conductivity type is formed, which covers the patterned epitaxial layer and the exposed first epitaxial layer; a second trench corresponding to the first trench is formed in the capping layer;

[0011] A sacrificial layer is formed in the second trench;

[0012] Ion implantation is performed on the capping layer based on the sacrificial layer to form an initial body region and an initial source region that are sequentially stacked in the capping layer along the direction away from the substrate.

[0013] A patterned mask layer is formed, which has an opening pattern. The orthographic projection of the opening pattern onto the substrate surface coincides with the orthographic projection of the patterned epitaxial layer onto the substrate surface.

[0014] Ion implantation is performed on the capping layer based on a patterned mask layer to form an isolation layer; the isolation layer divides the initial volume region into multiple volume regions and the initial source region into multiple source regions;

[0015] Remove the graphical mask layer and the sacrificial layer.

[0016] In this embodiment, a first epitaxial layer of a first conductivity type and a second epitaxial layer of a second conductivity type are sequentially formed on one side surface of the substrate. After patterning the second epitaxial layer to form a patterned epitaxial layer and a first trench, an epitaxial capping layer is then formed to create the second trench, which can create a second trench with fewer defects. At the same time, it is beneficial that the capping layer of the conformal patterned epitaxial layer can form a second trench with a smaller linewidth corresponding to the first trench, so that the etching process in related technologies is not required to prepare the second trench. This reduces the difficulty of forming the second trench and ensures the morphological quality of the second trench and other semiconductor devices subsequently formed in the second trench.

[0017] Based on this, an initial body region, an initial source region, and an isolation layer are sequentially formed in the capping layer on both sides of the trench using ion implantation. The isolation layer effectively separates the body and source regions, significantly simplifying the fabrication process. Furthermore, the isolation layer, together with the previously formed patterned epitaxial layer, provides electrical shielding for the second trench and other devices subsequently formed within it, eliminating the need for high-energy ion implantation to form the shielding layer in a single step, as is done in related technologies. This further reduces the complexity of the process and consequently lowers the fabrication cost.

[0018] In some embodiments, the step of ion implanting the cover layer based on the patterned mask layer to form an isolation layer includes: ion implanting the initial source region based on the patterned mask layer to form an ion implantation layer of a second conductivity type that is in contact with the initial body region, wherein the ion implantation layer, the patterned epitaxial layer, and the initial body region between the ion implantation layer and the patterned epitaxial layer together constitute the isolation layer.

[0019] In this embodiment, by adjusting the ion implantation energy, the formation depth of the ion implantation layer is controlled to not exceed the initial body region. This helps to reduce the required implantation energy while ensuring basic shielding for the second trench and other semiconductor devices subsequently formed in the second trench, thereby further reducing the process difficulty.

[0020] In other embodiments, the step of ion implantation of the capping layer based on the patterned mask layer to form an isolation layer includes: ion implantation of the initial source region and the initial body region based on the patterned mask layer to form an ion implantation layer of a second conductivity type that contacts the patterned epitaxial layer, wherein the ion implantation layer and the patterned epitaxial layer together constitute the isolation layer.

[0021] In this embodiment, by adjusting the ion implantation energy, the ion implantation layer is controlled to contact the aforementioned patterned epitaxial layer, so that the ion implantation layer and the patterned epitaxial layer can jointly provide better electrical shielding function.

[0022] In some embodiments, during the formation of the capping layer, the growth rate of the capping layer away from the surface of the first epitaxial layer in the patterned epitaxial layer is greater than the growth rate of the capping layer in the first trench.

[0023] In this embodiment, by adjusting the material growth rate in each direction during the formation of the capping layer, the coverage area and film thickness of the capping layer can be accurately adjusted, thereby improving the morphological quality of the second trench obtained based on the first trench, and thus improving the performance of the semiconductor device.

[0024] In some embodiments, the bottom surface of the second trench is lower than the top surface of the patterned epitaxial layer.

[0025] In some embodiments, the first conductivity type includes N-type, and the second conductivity type includes P-type.

[0026] In other embodiments, the first conductivity type includes P-type, and the second conductivity type includes N-type.

[0027] In some embodiments, the materials of the first epitaxial layer, the second epitaxial layer, and the capping layer all include silicon carbide; the material of the sacrificial layer includes polycrystalline silicon.

[0028] In some embodiments, after removing the patterned mask layer and the sacrificial layer, the method further includes the following steps.

[0029] A dielectric layer is formed on the sidewalls and bottom of the second trench;

[0030] A conductive layer is formed in the second trench; the dielectric layer and the conductive layer together constitute the gate structure.

[0031] In this embodiment, a gate structure is fabricated based on the second trench with better morphological quality formed above, so as to improve the performance of the obtained gate structure.

[0032] In some embodiments, the method further includes the following steps.

[0033] The substrate is thinned from the side of the substrate away from the first epitaxial layer.

[0034] A back electrode is formed on the side of the thinned substrate that is away from the first epitaxial layer.

[0035] In this embodiment, by forming a back electrode on the surface of the substrate away from the first epitaxial layer, the back electrode can be used as a drain, and the back electrode, substrate and gate structure can together constitute a semiconductor device with complete electrical functions, thus broadening the application of this application.

[0036] On the other hand, some embodiments of this application provide a semiconductor structure prepared using the semiconductor structure preparation methods described in the foregoing embodiments. This semiconductor structure also possesses the technical advantages of the semiconductor structure preparation methods described in the foregoing embodiments, and will not be detailed here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in some embodiments;

[0039] Figure 2 This is a schematic diagram of the structure obtained after performing step S200 in some embodiments;

[0040] Figure 3 This is a schematic diagram of the structure obtained after performing step S300 in some embodiments;

[0041] Figure 4 This is a schematic diagram of the structure obtained after performing step S400 in some embodiments;

[0042] Figure 5 This is a schematic diagram of the structure obtained after performing step S500 in some embodiments;

[0043] Figure 6 This is a schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some embodiments;

[0044] Figure 7 This is a schematic diagram of the structure obtained after performing step S600 in some embodiments;

[0045] Figure 8 This is a schematic diagram of the structure obtained after performing step S700 in some embodiments;

[0046] Figure 9This is a schematic diagram of the structure obtained after executing step S800 in some embodiments;

[0047] Figure 10 This is a schematic diagram of the structure obtained after executing step S900 in some embodiments;

[0048] Figure 11 This is a schematic diagram of the structure obtained after another execution step S900 provided in some embodiments;

[0049] Figure 12 This is a schematic diagram of the structure obtained after performing step S1000 in some embodiments;

[0050] Figure 13 This is a schematic flowchart of a method for fabricating another semiconductor structure provided in some embodiments;

[0051] Figure 14 This is a schematic diagram of the structure obtained after performing step S1100 in some embodiments;

[0052] Figure 15 This is a schematic diagram of the structure obtained after performing step S1200 in some embodiments;

[0053] Figure 16 This is a schematic diagram of the structure obtained after performing step S1400 in some embodiments; it is also a schematic diagram of the structure of a semiconductor structure in some embodiments.

[0054] Explanation of reference numerals in the attached figures:

[0055] S1-Substrate, 1-First epitaxial layer, 2-Second epitaxial layer, 2A-Patterned epitaxial layer, 3-Capping layer, 4'-Sacrificial material layer, 4-Sacrificial layer, 5-Patterned mask layer, 6-Ion implantation layer, 7-Isolation layer, 8-Dielectric layer, 9-Conductive layer, 10-Back electrode;

[0056] TR1 - First trench, TR2 - Second trench, A1' - Initial volume region, A1 - Volume region, A2' - Initial source region, A2 - Source region, P1 - Opening pattern. Detailed Implementation

[0057] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0059] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0061] Trench semiconductor devices are favored by the market because they increase the density of arrangement per unit wafer area, resulting in better performance and lower manufacturing costs compared to planar semiconductor devices.

[0062] However, during the etching process to form trenches, the trench surface is damaged, resulting in defects. Furthermore, with the continuous miniaturization of semiconductor critical dimensions, etching trenches with high aspect ratios is increasingly difficult. In addition, during ion implantation of trench-type semiconductor devices, the greater the implantation depth, the higher the energy requirement for ion implantation. Conventional medium-current implanters are insufficient to meet these requirements. To meet the ion implantation requirements of deeper regions, high-energy implanters are needed, thereby increasing the investment cost of manufacturing equipment. These problems hinder the further development of trench-type semiconductor devices.

[0063] Please see Figure 1 This application provides a method for fabricating a semiconductor structure, which can improve the morphological quality of the obtained semiconductor structure and further reduce the fabrication difficulty and cost. The fabrication method includes the following steps.

[0064] S100 provides a substrate.

[0065] S200, a first epitaxial layer of a first conductivity type is formed on one side surface of the substrate.

[0066] S300, a second epitaxial layer of a second conductivity type is formed on the surface of the first epitaxial layer away from the substrate.

[0067] S400, etch the second epitaxial layer to form a patterned epitaxial layer, in which a first trench is formed, the first trench penetrating the patterned epitaxial layer along the thickness direction.

[0068] S500, a capping layer of the first conductivity type is formed, the capping layer covers the second epitaxial layer and the exposed first epitaxial layer; a second trench corresponding to the first trench is formed in the capping layer.

[0069] S600, a sacrificial layer is formed in the second trench;

[0070] S700 involves ion implantation of the capping layer based on the sacrificial layer to form an initial bulk region and an initial source region that are sequentially stacked in the capping layer in the direction away from the substrate.

[0071] S800, forming a patterned mask layer, the patterned mask layer having an opening pattern, the orthographic projection of the opening pattern on the substrate surface coincides with the orthographic projection of the patterned epitaxial layer on the substrate surface.

[0072] S900 performs ion implantation on the capping layer based on a patterned mask layer to form an isolation layer; the isolation layer divides the initial volume region into multiple volume regions and the initial source region into multiple source regions.

[0073] S1000, removes the patterned mask layer and sacrificial layer.

[0074] In this embodiment, a first epitaxial layer of a first conductivity type and a second epitaxial layer of a second conductivity type are sequentially formed on one side surface of the substrate. After patterning the second epitaxial layer to form a patterned epitaxial layer and a first trench, an epitaxial capping layer is then formed to create the second trench, which can create a second trench with fewer defects. At the same time, it is beneficial that the capping layer of the conformal patterned epitaxial layer can form a second trench with a smaller linewidth corresponding to the first trench, so that the etching process in related technologies is not required to prepare the second trench. This reduces the difficulty of forming the second trench and ensures the morphological quality of the second trench and other semiconductor devices subsequently formed in the second trench.

[0075] Based on this, an initial body region, an initial source region, and an isolation layer are sequentially formed in the capping layer on both sides of the trench using ion implantation. The isolation layer effectively separates the body and source regions, significantly simplifying the fabrication process. Furthermore, the isolation layer, together with the previously formed patterned epitaxial layer, provides electrical shielding for the second trench and other devices subsequently formed within it, eliminating the need for high-energy ion implantation to form the shielding layer in a single step, as is done in related technologies. This further reduces the complexity of the process and consequently lowers the fabrication cost.

[0076] In step S100, please refer to Figure 1 S100 and Figure 2 Substrate S1 is provided.

[0077] For example, the substrate S1 can be made of any combination of semiconductor materials, insulating materials, conductive materials, or such materials. For instance, the substrate S1 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate S1 can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. This application does not limit this application.

[0078] To more clearly illustrate the implementation process of each process step in the semiconductor structure fabrication method provided in this application, the following embodiments and figures are illustrated using a substrate S1 comprising a single-layer structure as an example.

[0079] In step S200, please refer to Figure 1 S200 and Figure 2 A first epitaxial layer 1 of a first conductivity type is formed on one side surface of the substrate S1.

[0080] For example, a first epitaxial layer 1 can be formed on one side surface of the substrate S1 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0081] For example, the material of the first epitaxial layer 1 may include: monocrystalline silicon, polycrystalline silicon, silicon oxide, silicon nitride, or silicon carbide. In some examples, the material of the first epitaxial layer 1 includes silicon carbide.

[0082] For example, in-situ doping of the first conductivity type can be performed during the formation of the first epitaxial layer 1; or the first epitaxial layer 1 can be doped with ions of the first conductivity type after its formation. This application does not limit this.

[0083] In some embodiments, the first conductivity type includes N-type. Correspondingly, the impurity elements doped into the first epitaxial layer 1 include phosphorus, arsenic, bismuth, or antimony.

[0084] In other embodiments, the first conductivity type includes P-type. Correspondingly, the impurity elements doped into the first epitaxial layer 1 include boron, indium, or gallium.

[0085] For example, in the first epitaxial layer 1 of the first conductivity type, the doping concentration of impurity elements ranges from 10^16 / cm^3 to 10^18 / cm^3. 3 For example, it can be 10^16 / cm 3 10^17 / cm 3 Or 10^18 / cm 3 .

[0086] In step S300, please refer to Figure 1 S300 and Figure 3 A second epitaxial layer 2 of a second conductivity type is formed on the surface of the first epitaxial layer 1 opposite to the substrate S1.

[0087] For example, a second epitaxial layer 2 can be formed on the surface of the first epitaxial layer 1 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0088] For example, the material of the second epitaxial layer 2 may include: monocrystalline silicon, polycrystalline silicon, silicon oxide, silicon nitride, or silicon carbide. In some examples, the material of the second epitaxial layer 2 includes silicon carbide.

[0089] For example, the thickness of the second epitaxial layer 2 ranges from 500 nm to 1500 nm, such as 500 nm, 800 nm, 1000 nm, 1300 nm, or 1500 nm. In some examples, the thickness of the second epitaxial layer 2 is, for example, 1000 nm.

[0090] For example, in-situ doping of the second conductivity type can be performed during the formation of the second epitaxial layer 2; or ion implantation of the second conductivity type can be performed on the second epitaxial layer 2 after its formation. This application does not limit this.

[0091] In some embodiments, the second conductivity type includes P-type. Correspondingly, the impurity elements doped into the second epitaxial layer 2 include boron, indium, or gallium.

[0092] In other embodiments, the second conductivity type includes N-type. Correspondingly, the impurity elements doped into the second epitaxial layer 2 include phosphorus, arsenic, bismuth, or antimony.

[0093] It is understood that in the embodiments of this application, both the first conductivity type and the second conductivity type can be matched to the type of semiconductor product being prepared, and this application does not limit this. In the following embodiments, the first conductivity type includes N-type and the second conductivity type includes P-type as examples for further explanation.

[0094] For example, in the second epitaxial layer 2 of the second conductivity type, the doping concentration of impurity elements ranges from 10^16 / cm^2.3 ~10^18 / cm 3 For example, it can be 10^16 / cm 3 10^17 / cm 3 Or 10^18 / cm 3 .

[0095] In step S400, please refer to Figure 1 S400 and Figure 4 The second epitaxial layer 2 is etched to form a patterned epitaxial layer 2A. A first trench TR1 is formed in the patterned epitaxial layer 2A, and the first trench TR1 penetrates the patterned epitaxial layer 2A along the thickness direction.

[0096] For example, the second epitaxial layer 2 can be etched using a wet etching process or a dry etching process to form a patterned epitaxial layer 2A and a first trench TR1. The first trench TR1 penetrates the patterned epitaxial layer 2A and exposes a portion of the surface of the first epitaxial layer 1.

[0097] For example, a dry etching process can be used to etch the second epitaxial layer 2, so as to accurately control the formation position, direction and depth of the first trench TR1 by adjusting the process parameters such as the etching direction and etching time of the dry etching, so as to ensure the morphological quality of the first trench TR1.

[0098] In step S500, please refer to Figure 1 S500 and Figure 5 A first conductive type capping layer 3 is formed, which covers the second epitaxial layer 2 and the exposed first epitaxial layer 1; a second trench TR2 corresponding to the first trench TR1 is formed in the capping layer 3.

[0099] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to form the second epitaxial layer 2 on the surface of the second epitaxial layer 2 and the exposed first epitaxial layer 1.

[0100] For example, a vapor deposition process can be used, and by adjusting process parameters such as deposition thickness, the second epitaxial layer 2 can conformally cover the portion of the first trench TR1 to form a second trench TR2.

[0101] For example, a vapor deposition process can be used, and by adjusting process parameters such as deposition direction, the growth rate of the capping layer 3 away from the surface of the patterned epitaxial layer 2A is greater than the growth rate of the capping layer 3 within the first trench TR1 during the formation of the capping layer 3, thereby controlling the lateral dimension of the final obtained second trench TR2.

[0102] For example, the bottom surface of the second trench TR2 is lower than the top surface of the patterned epitaxial layer 2A.

[0103] In step S600, please refer to Figure 1 S600 in Figure 6 and Figure 7 A sacrificial layer 4 is formed in the second trench TR2.

[0104] For example, the sacrificial layer 4 can be prepared using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0105] For example, a sacrificial material layer 4' that fills the second trench TR2 and covers the surface of the cover layer 3 can be formed first, and then the portion of the sacrificial material layer 4' located on the surface of the cover layer 3 can be removed, so that the portion of the sacrificial material layer 4' retained in the second trench TR2 constitutes the sacrificial layer 4.

[0106] For example, a reverse etching process or a chemical mechanical polishing process can be used to partially remove the sacrificial material layer 4'.

[0107] For example, the material of the sacrificial material layer 4' may include photoresist, monocrystalline silicon, or polycrystalline silicon. In some examples, the material of the sacrificial material layer 4' is, for example, polycrystalline silicon.

[0108] In step S700, please refer to Figure 1 S700 and Figure 8 Ion implantation is performed on the capping layer 3 based on the sacrificial layer 4 to form an initial body region A1' and an initial source region A2' that are sequentially stacked in the capping layer 3 along the direction away from the substrate S1.

[0109] For example, first, a high-energy ion implantation is performed on the capping layer 3 to form an initial body region A1' in the lower part of the capping layer 3, and then a low-energy ion implantation is performed on the capping layer 3 to form an initial source region A2' in the upper part of the capping layer 3.

[0110] For example, the initial body region A1' is of the second conductivity type, the initial source region A2' is of the first conductivity type, and the impurity concentration in the initial source region A2' is greater than the impurity concentration in the initial body region A1'.

[0111] For example, the impurity elements forming the initial body region A1' include phosphorus, arsenic, bismuth, or antimony; the impurity elements forming the initial source region A2' include boron, indium, or gallium.

[0112] For example, in the initial body region A1', the doping concentration of impurity elements ranges from 10^16 / cm^2. 3 ~10^18 / cm 3 For example, it can be 10^16 / cm 310^17 / cm 3 Or 10^18 / cm 3 .

[0113] For example, in the initial source region A2', the doping concentration of impurity elements ranges from 10^18 / cm^2. 3 ~10^20 / cm 3 For example, it could be 10^18 / cm 3 10^19 / cm 3 Or 10^20 / cm 3 .

[0114] In step S800, please refer to Figure 1 S800 and Figure 9 A patterned mask layer 5 is formed, and the patterned mask layer 5 has an opening pattern P1. The orthographic projection of the opening pattern P1 onto the surface of the substrate S1 coincides with the orthographic projection of the patterned epitaxial layer 2A onto the surface of the substrate S1.

[0115] For example, a mask material layer can be formed on the sacrificial layer 4 and the capping layer 3, and then a patterned mask layer 5 can be formed by etching the mask material layer; or a photolithography process can be used to directly form a patterned mask layer 5 composed of photoresist. This application does not limit this.

[0116] For example, a photoresist with the inverse shape of the photoresist used to form the patterned epitaxial layer 2A in step S400 can be used to prepare the patterned mask layer 5. For instance, if a positive photoresist is used in step S400, a negative photoresist is used in this step; or if a negative photoresist is used in step S400, a positive photoresist is used in this step. In this way, the same etching mask as that used to form the patterned epitaxial layer 2A in step S400 can be used to prepare the patterned mask layer 5, further reducing the preparation cost.

[0117] In step S900, please refer to Figure 1 S900 in Figure 10 and Figure 11 Ion implantation is performed on the capping layer 3 based on the patterned mask layer 5 to form the isolation layer 7; the isolation layer 7 divides the initial body region A1' into multiple body regions A1 and the initial source region A2' into multiple source regions A2.

[0118] Here, the specific structure of the obtained isolation layer 7 can be controlled by adjusting the injected energy, thereby controlling the isolation performance of the isolation layer 7 to meet the needs of different semiconductor products. The following embodiments illustrate several different fabrication methods for the isolation layer 7.

[0119] Please see Figure 10In some embodiments, ion implantation is performed on the initial source region A2' based on the patterned mask layer 5 to form a second conductivity type ion implantation layer 6 in contact with the initial body region A1'. The ion implantation layer 6, the patterned epitaxial layer 2A, and the initial body region A1' between the ion implantation layer 6 and the patterned epitaxial layer 2A together constitute the isolation layer 7.

[0120] Here, the bottom of the ion implantation layer 6 can be flush with the top of the initial body region A1'; or it can extend into the initial body region A1'.

[0121] For example, the ion implantation layer 6 is of the second conductivity type, and correspondingly, the impurity elements forming the ion implantation layer 6 include: phosphorus, arsenic, bismuth or antimony.

[0122] For example, in the ion implantation layer 6, the doping concentration of impurity elements ranges from 10^18 / cm^2. 3 ~10^20 / cm 3 For example, it can be 10^16 / cm 3 10^17 / cm 3 Or 10^18 / cm 3 .

[0123] Please see Figure 11 In other embodiments, ion implantation is performed on the initial source region A2' and the initial body region A1' based on the patterned mask layer 5 to form a second conductivity type ion implantation layer 6 in contact with the patterned epitaxial layer 2A. The ion implantation layer 6 and the patterned epitaxial layer 2A together constitute an isolation layer 7.

[0124] Here, the bottom of the ion implantation layer 6 can be flush with the top of the patterned epitaxial layer 2A; or it can extend into the patterned epitaxial layer 2A.

[0125] For example, the ion implantation layer 6 is of the second conductivity type, and correspondingly, the impurity elements forming the ion implantation layer 6 include: phosphorus, arsenic, bismuth or antimony.

[0126] For example, in the ion implantation layer 6, the doping concentration of impurity elements ranges from 10^18 / cm^2. 3 ~10^20 / cm 3 For example, it can be 10^16 / cm 3 10^17 / cm 3 Or 10^18 / cm 3 .

[0127] In step S1000, please refer to Figure 1 S1000 and Figure 12 Remove the patterned mask layer 5 and the sacrificial layer 4.

[0128] For example, the patterned mask layer 5 and the sacrificial layer 4 can be removed using grinding and / or etching processes.

[0129] For example, a wet etching process can be used, employing an etchant with a high selectivity to achieve better removal of the patterned mask layer 5 and the sacrificial layer 4.

[0130] It is worth noting that in some embodiments, related semiconductor devices can be further fabricated based on the structure obtained in step S1000 to obtain semiconductor products with complete electrical functions.

[0131] For example, please refer to Figure 13 The method further includes steps S1100 to S1400.

[0132] S1100, a dielectric layer is formed on the sidewalls and bottom of the second trench.

[0133] S1200, a conductive layer is formed in the second trench; the dielectric layer and the conductive layer together constitute the gate structure.

[0134] S1300, the substrate is thinned from the side surface of the substrate away from the first epitaxial layer.

[0135] S1400, a back electrode is formed on the side surface of the thinned substrate away from the first epitaxial layer.

[0136] In this embodiment, a gate structure is fabricated based on the aforementioned second trench with better morphological quality, which helps to improve the performance of the obtained gate structure. Furthermore, a back electrode is formed on the surface of the substrate opposite to the first epitaxial layer, allowing the back electrode to serve as the drain. This enables the back electrode, substrate, and gate structure to collectively constitute a semiconductor device with complete electrical functions, thus broadening the application of this application.

[0137] In step S1100, please refer to Figure 13 S1100 and Figure 14 A dielectric layer 8 is formed on the sidewall and bottom of the second trench TR2.

[0138] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to form a dielectric layer 8 on the sidewalls and bottom of the second trench TR2.

[0139] For example, the material of dielectric layer 8 may include silicon oxide, silicon nitride, silicon oxynitride, or hafnium dioxide.

[0140] For example, a silicon oxide layer as dielectric layer 8 can be formed on the sidewalls and bottom of the second trench TR2 using a thermal oxidation process. The silicon oxide layer obtained by the thermal oxidation process can have a uniform thickness and can repair interface damage in the second trench TR2. This helps to ensure the morphological quality of dielectric layer 8, thereby improving the electrical performance of the semiconductor structure.

[0141] In step S1200, please refer to Figure 13 S1100 and Figure 15 A conductive layer 9 is formed in the second trench TR2; the dielectric layer 8 and the conductive layer 9 together constitute the gate structure.

[0142] For example, a conductive layer 9 can be formed in the second trench TR2 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, electroplating, or vapor deposition.

[0143] In some embodiments, the material of the conductive layer 9 may include a semiconductor material or a metal material.

[0144] For example, the material of conductive layer 9 can be doped polycrystalline silicon.

[0145] For example, the material of conductive layer 9 can be one or more of aluminum, copper, titanium and tungsten.

[0146] In step S1300, please refer to Figure 13 S1300 and Figure 16 The substrate S1 is thinned from the side surface of the substrate S1 away from the first epitaxial layer 1.

[0147] For example, a grinding process is used to grind the surface of the substrate S1 away from the first epitaxial layer 1 to reduce it to a preset thickness.

[0148] For example, a wafer thinner can be used to perform the grinding process to more precisely control the grinding thickness and obtain better surface quality.

[0149] In step S1400, please refer to Figure 13 S1400 and Figure 16 A back electrode 10 is formed on the side surface of the thinned substrate S1 that is away from the first epitaxial layer 1.

[0150] For example, processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and electroplating can be used to form the back electrode 10 covering the substrate S1 away from the surface of the first epitaxial layer 1.

[0151] For example, the back electrode 10 can be a single-layer structure or a multi-layer structure.

[0152] For example, in some embodiments where the back electrode 10 has a multilayer structure, the back electrode 10 may include a titanium layer, a nickel layer and a gold layer stacked sequentially along the direction away from the substrate S1.

[0153] Please continue reading. Figure 16 Some embodiments of this application also provide a semiconductor structure, which is prepared using the semiconductor structure preparation method described in the foregoing embodiments.

[0154] For example, the semiconductor structure includes: a substrate S1, a first epitaxial layer 1, a patterned epitaxial layer 2A, a capping layer 3, a second trench TR2, a gate structure, and a back electrode 10. The first epitaxial layer 1 and the patterned epitaxial layer 2A are sequentially formed on one side surface of the substrate S1; the capping layer 3 covers the patterned epitaxial layer 2A and the exposed surface of the first epitaxial layer 1; the second trench TR2 is located in the capping layer, and the bottom surface of the second trench TR2 is lower than the top surface of the patterned epitaxial layer 2A; body regions A1 and source regions A2 are formed in the capping layer 3 and stacked along a direction away from the substrate S1. Multiple body regions A1 and multiple source regions A2 are separated by an isolation layer 7.

[0155] For example, the first epitaxial layer 1, the capping layer 3, and the source region A2 are of the first conductivity type; the patterned epitaxial layer 2A, the body region A1, and the isolation layer 7 are of the second conductivity type.

[0156] For example, the materials of the first epitaxial layer 1, the patterned epitaxial layer 2A, and the capping layer 3 all include silicon carbide.

[0157] In some embodiments, the semiconductor structure further includes a dielectric layer 8 and a conductive layer 9 formed in a second trench TR2; the dielectric layer 8 and the conductive layer 9 together constitute a gate structure.

[0158] For example, the material of dielectric layer 8 may include silicon oxide, silicon nitride, silicon oxynitride, or hafnium dioxide.

[0159] For example, the material of the conductive layer 9 may be doped polycrystalline silicon; or it may include one or more of the following: aluminum, copper, titanium and tungsten.

[0160] In some embodiments, the semiconductor structure further includes a back electrode 10 located on the surface of the substrate S1 away from the first epitaxial layer 1.

[0161] For example, the back electrode 10 can be a single-layer structure or a multi-layer structure.

[0162] For example, in some embodiments where the back electrode 10 has a multilayer structure, the back electrode 10 may include a titanium layer, a nickel layer and a gold layer stacked sequentially along the direction away from the substrate S1.

[0163] In the embodiments described above, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0164] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first epitaxial layer of a first conductivity type is formed on one side surface of the substrate; A second epitaxial layer of a second conductivity type is formed on the surface of the first epitaxial layer opposite to the substrate; The second epitaxial layer is etched to form a patterned epitaxial layer, wherein a first trench is formed in the patterned epitaxial layer and the first trench penetrates the patterned epitaxial layer along the thickness direction; A capping layer of a first conductivity type is formed, the capping layer covering the patterned epitaxial layer and the exposed first epitaxial layer; a second trench corresponding to the first trench is formed in the capping layer; A sacrificial layer is formed in the second trench; Ion implantation is performed on the capping layer based on the sacrificial layer to form an initial body region and an initial source region that are sequentially stacked in the capping layer in a direction away from the substrate; A patterned mask layer is formed, wherein the patterned mask layer has an opening pattern, and the orthographic projection of the opening pattern onto the substrate surface coincides with the orthographic projection of the patterned epitaxial layer onto the substrate surface. Ion implantation is performed on the cover layer based on the patterned mask layer to form an isolation layer; The isolation layer divides the initial volume region into multiple volume regions and the initial source region into multiple source regions; Remove the patterned mask layer and the sacrificial layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of ion implantation of the cover layer based on the patterned mask layer to form an isolation layer includes: Ion implantation is performed on the initial source region based on the patterned mask layer to form an ion implantation layer of a second conductivity type that is in contact with the initial body region. The ion implantation layer, the patterned epitaxial layer, and the initial body region between the ion implantation layer and the patterned epitaxial layer together constitute the isolation layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of ion implantation of the cover layer based on the patterned mask layer to form an isolation layer includes: Ion implantation is performed on the initial source region and the initial body region based on the patterned mask layer to form an ion implantation layer of a second conductivity type that is in contact with the patterned epitaxial layer. The ion implantation layer and the patterned epitaxial layer together constitute the isolation layer.

4. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that, During the formation of the capping layer, the growth rate of the capping layer away from the surface of the first epitaxial layer in the patterned epitaxial layer is greater than the growth rate of the capping layer in the first trench.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The bottom surface of the second trench is lower than the top surface of the patterned epitaxial layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The first conductivity type includes N-type, and the second conductivity type includes P-type; or The first conductivity type includes P-type, and the second conductivity type includes N-type.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first epitaxial layer, the second epitaxial layer, and the capping layer are all made of silicon carbide; the sacrificial layer is made of polycrystalline silicon.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After removing the patterned mask layer and the sacrificial layer, the method further includes: A dielectric layer is formed on the sidewalls and bottom of the second trench; A conductive layer is formed in the second trench; the dielectric layer and the conductive layer together constitute a gate structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The method further includes: The substrate is thinned from the side surface of the substrate opposite to the first epitaxial layer; A back electrode is formed on the side surface of the thinned substrate that is away from the first epitaxial layer.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method as described in any one of claims 1 to 9.

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