A grindable heat sink for multi-mold packaging

Abstract

A semiconductor package may include a semiconductor die stack, comprising a top die and one or more core dies below the top die. The semiconductor package may also include a metal heat sink plated on the top surface of the top die and having multiple sides coplanar with corresponding sides of multiple sidewalls of the semiconductor die stack. A molding part may surround the semiconductor die stack and the metal heat sink, wherein the molding part includes an upper surface coplanar with the exposed upper surface of the metal heat sink, and both the upper surface of the molding part and the exposed upper surface of the metal heat sink are mechanically modified. For example, the metal heat sink and the die may be simultaneously polished with a polishing pad, and the result may show polishing marks.

Description

Technical Field

[0001] This invention generally relates to semiconductor device packaging, and particularly to semiconductor device packaging with grindable heat sinks. background

[0002] Semiconductor manufacturers are constantly seeking to create smaller, faster, and more powerful devices, and to provide higher-density components for a wide variety of products, such as computers, mobile phones, watches, cameras, etc. One way to increase the speed and power of semiconductor devices without significantly increasing their footprint is to vertically stack multiple semiconductor chips in a single package. However, the increased power leads to the generation of more heat in the device. This heat problem is further amplified by the higher density and reduced surface area of ​​the stacked die.

[0003] Brief description of the drawings

[0004] Referring to the drawings below will provide a better understanding of many aspects of current technology. The components in the drawings are not necessarily shown to scale. Their focus is on clearly illustrating the principles of current technology.

[0005] Figure 1 is a cross-sectional view of a semiconductor device package according to an embodiment of the present invention.

[0006] Figure 2A is a cross-sectional view of a semiconductor wafer mounted on a carrier according to an embodiment of the present invention.

[0007] Figure 2B is a cross-sectional view of a thinned semiconductor wafer mounted on a carrier according to an embodiment of the present invention.

[0008] Figure 2C is a cross-sectional view of a semiconductor wafer having a seed layer according to an embodiment of the present invention.

[0009] Figure 2D is a cross-sectional view of a semiconductor wafer having a metallized layer according to an embodiment of the present invention.

[0010] Figure 2E is a cross-sectional view of a plurality of semiconductor molds having a metal-plated layer according to an embodiment of the present invention.

[0011] Figure 2F is a cross-sectional view of an intermediate semiconductor structure including multiple semiconductor die stacks according to an embodiment of the present invention.

[0012] Figure 2G is a cross-sectional view of an intermediate semiconductor structure comprising multiple semiconductor die stacks after grinding, according to an embodiment of the present invention.

[0013] Figure 2H is a cross-sectional view of a plurality of single-chip semiconductor mold packages according to an embodiment of the present invention.

[0014] Figure 3 is a cross-sectional view of a semiconductor device including a semiconductor device assembly coated with a grindable metal heat sink according to an embodiment of the present invention.

[0015] Figure 4 is a flowchart illustrating a method for manufacturing a semiconductor device package according to an embodiment of the present invention.

[0016] Figure 5 is a schematic diagram of a system including a semiconductor device according to an embodiment of the present invention. Detailed description

[0017] Throughout this invention, numerous specific details have been discussed to provide a thorough and enabling description of embodiments of the invention. Those skilled in the art will recognize that the invention can be practiced without one or more of these specific details. Well-known structures and / or operations typically associated with semiconductor devices may not be shown and / or described in detail to avoid obscuring other aspects of the invention. Generally, it should be understood that various other devices, systems, and / or methods beyond these specific embodiments of the invention may be within the scope of this invention.

[0018] The term "semiconductor device" generally refers to a solid-state device that incorporates semiconductor materials. A semiconductor device may include, for example, a semiconductor substrate, a wafer, a panel, or a single wafer derived from a wafer or substrate. A semiconductor device may also include one or more device layers deposited on a substrate.

[0019] The term "semiconductor device package" can refer to an arrangement in which one or more semiconductor devices are integrated into a common package. A semiconductor package may include a housing, molded part, or enclosure that partially or completely encapsulates at least one semiconductor device. A semiconductor package may also include a substrate carrying one or more semiconductor devices. The substrate may be attached to or otherwise incorporated into said housing or enclosure.

[0020] The term "semiconductor device assembly" can refer to an assembly consisting of one or more semiconductor devices, semiconductor device packages, and / or substrates, which may include inserts, supports, and / or other suitable substrates. Semiconductor device assemblies can be manufactured in (but not limited to) discrete package forms, strip or matrix forms, and / or wafer panel forms.

[0021] As manufacturers continue to increase the number of molds in 3D integrated circuits and packaging, overheating caused by multiple mold stacks has become a significant problem. Temperature fluctuations within these stacks can cause component and interconnect deformation, degrade performance, and ultimately lead to device failure. Furthermore, customers who purchase devices with multiple mold stacks for their products often require post-mold grinding, such as for producing thinner phones, laptops, and watches. Traditional heatsinks use thermal interface materials (such as thermal paste or thermal adhesive) attached to the top mold. However, these thermal interface materials cannot withstand the forces of the grinding process. This may require customers to thin the device and apply separate heatsinks, increasing the number of steps and overall cost.

[0022] To address these issues, embodiments of the present invention provide a semiconductor device package including a grindable heat sink plated on a top mold of a stack of semiconductor molds. The plated heat sink eliminates the need for thermal interface materials. The semiconductor device stack and the grindable heat sink can be embedded within a molded part. The molded part provides additional support for the heat sink and allows customers to grind both the molded part and the heat sink simultaneously as needed, thinning the package without grinding the top mold or requiring a separate heat sink. To manufacture these packages, the top mold can be mounted on a virtual carrier, thinned, and plated with a grindable heat sink material. This can be a wafer-level process, where the heat sink material is plated before the semiconductor wafer is peeled from the carrier and diced into individual plating molds. The plated top mold can then be mounted on a stack of semiconductor molds, encapsulated by the molded part, and ground to expose the heat sink.

[0023] Figure 1 is a cross-sectional view of a semiconductor device package 100 according to an embodiment of the present invention. Package 100 includes a stack of semiconductor molds 102 mounted on a substrate 104. Package 100 also includes a molding compound 140 surrounding the stack of semiconductor molds 102. The stack of semiconductor molds 102 may include a top mold 106 plated with a metal heat sink 112. The metal heat sink may be copper, aluminum, or other suitable heat sink material. As shown, the upper surface of the heat sink 112 and the upper surface of the molding compound 140 may become coplanar due to grinding of the molding compound 140 and the heat sink 112. For example, the molding compound 140 and the heat sink 112 may be ground using a grinding wheel or grinding disc. Thus, the heat sink 112 may exhibit a grinding finish. The heat sink 112 and the molding compound 140 may be further ground, for example by a customer using the semiconductor device package 100 in a larger system.

[0024] The top mold 106 can be prefabricated using a metal heat sink 112 and then mounted on the core mold 108 using any suitable process. For example, the top mold 106 can be thermo-bonded (TCB) to the core mold 108a. A mold-attached film (such as a non-conductive film or CV film) can serve as a spacer between the molds of the stack 102. The top mold 106 can be fabricated together with the metal heat sink 112 by depositing a metal layer on the semiconductor wafer. In some embodiments, a seed layer is deposited on the wafer prior to deposition, for example by physical vapor deposition (PVD). For example, the seed layer can be a very thin layer of copper or titanium. The seed layer can be approximately 1 micrometer thick. The fabrication process is described in more detail in Figures 2A-E below.

[0025] The stack of semiconductor dies 102 may include the top die 106 and one or more core dies 108. For example, the core die 108 may be a memory die, such as a DRAM die for a high-bandwidth memory (HBM) device. Alternatively, the core die 108 may be other types of memory, such as SRAM, SDRAM, or flash memory, or a non-memory device. The thickness of the core die 108 may be approximately the same as that of the top die 106. For example, the core die 108 and the top die 106 may each be approximately 50 micrometers thick. Although Figure 1 shows a total of five dies including the top die 106 and the core die 108, embodiments of the invention may include more dies, such as 8, 12, 16, or more dies. In some embodiments, the stack 102 may have as few as one die, i.e., only one top die 106. Furthermore, in some embodiments, the dies of the stack 102 may have the same dimensions (as shown in Figure 1) or different dimensions. The dies of the stack 102 may have different stacking arrangements, such as a tapered stack, a suspended die stack, etc.

[0026] The stack of semiconductor molds 102 can be interconnected via through-silicon vias (TSVs) and bumps. In some embodiments, the molds of the stack 102 can be connected using bonding wires instead of TSVs, or connected outside of TSVs. For example, spacers between molds can provide the space required to attach bonding wires to the molds. The bonding wires can then be coupled to pads on a package substrate 104 (not shown).

[0027] Package substrate 104 may be or include an interposer, a printed circuit board, a dielectric isolator, another semiconductor die (e.g., a logic die), or another suitable substrate. Package substrate 104 may include pads electrically coupled to semiconductor die stack 102. In some embodiments, package substrate 104 includes additional semiconductor components (e.g., doped silicon wafers or ferrosilicon wafers), non-conductive components (e.g., various ceramic substrates, such as alumina (Al2O3) etc.), aluminum nitride, and / or conductive portions (e.g., interconnect circuits, TSVs, etc.). Package substrate 104 may further include electrical connectors 124 (e.g., pads, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) electrically coupled to package substrate 104 and configured to electrically couple package 100 to an external device (not shown). Package substrate 104 may optionally include one or more signal routing structures or layers (not shown), which include conductive components such as traces, vias, etc., that transmit signals between electrical connector 124 and semiconductor die stack 102.

[0028] Figures 2A-G illustrate the assembly of semiconductor devices at different stages of the manufacturing process. Figure 2A is a cross-sectional view of a semiconductor wafer 200 mounted on a carrier 250 according to an embodiment of the present invention. The semiconductor wafer 200 can be mounted on the carrier 250 using standard mounting procedures. For example, a temporary mounting adhesive 202 can be used to mount the wafer 200 to the carrier. The carrier 250 can be made of glass or other suitable materials.

[0029] Figure 2B is a cross-sectional view of the semiconductor wafer 200 of Figure 2A, after being thinned and mounted on a carrier, according to an embodiment of the present invention. The semiconductor wafer can be thinned by post-grinding 200 (e.g., using a grinding wheel). The semiconductor wafer 200 can be thinned to a thickness of approximately 50 micrometers.

[0030] Figure 2C is a cross-sectional view of a semiconductor wafer 200 having a seed layer 204 according to an embodiment of the present invention. The seed layer 204 can be deposited on the back side of the semiconductor wafer 200 by a PVD method, such as sputtering or evaporation deposition. The seed layer may include a metal (e.g., copper or titanium 200) and facilitates the electroplating of a metal layer on the semiconductor wafer 200, as shown in Figure 2D below. In some embodiments, the back side of the semiconductor wafer 200 is passivated before the seed layer 204 is deposited. Passivation can remove contaminants on the surface of the semiconductor wafer 200 and improve the adhesion of the plated metal layer. For example, the semiconductor wafer 200 can be passivated by forming a passivation layer of silicon nitride or silicon oxide by chemical vapor deposition (CVD). The passivation layer and the seed layer 204 together can be less than 1 micrometer thick.

[0031] Figure 2D is a cross-sectional view of a semiconductor wafer 200 having a metal plating layer 206 according to an embodiment of the present invention. The electroplating of the metal plating layer 206 can be facilitated by the seed layer 204 of Figure 2C. The metal plating layer 206 may comprise a metal suitable for a heat sink, such as copper or aluminum. The metal layer 206 may have a thickness of approximately 50 to 250 micrometers, 100 to 200 micrometers, 125 to 175 micrometers, etc. For example, the metal layer 206 may be approximately 135 micrometers thick. The metal plating layer 206 may be similar to the metal heat sink 112 of Figure 1, except that it is plated on the semiconductor wafer 200 instead of a separate die. After the metal layer 206 is plated, the semiconductor wafer 200 can be peeled off from the carrier 250.

[0032] Figure 2E is a cross-sectional view of a plurality of semiconductor molds 200a-c having metal-plated layers 206a-c according to an embodiment of the present invention. After being peeled from the carrier 250 of Figures 2A-D, the semiconductor wafer 200 of Figures 2A-D having the metal layer 206 can be diced to form a plurality of semiconductor molds, including semiconductor molds 200a-c respectively having metal layers 206a-c. The semiconductor wafer 200 and the metal layer 206 can be diced along one or more kerfs using a dicing saw. Other suitable dicing methods known in the art can be used, as long as they can diced the metal layer 206 in addition to dicing the wafer 200. Depending on the dicing method, evidence of dicing can be displayed along the sidewalls of the metal layer 206a-c or the semiconductor wafer 200a-c. For example, the sidewalls of the metal layers 206a-c or the sidewalls of the semiconductor mold 200a-c may display markings related to mechanical changes, such as saw marks from a saw or blade. In some embodiments, the saw blades may be arranged in a straight line pattern.

[0033] Figure 2F is a cross-sectional view of an intermediate semiconductor structure 210 comprising multiple semiconductor die stacks 212a-c according to an embodiment of the present invention. Figure 2F shows three semiconductor die stacks 212a-c for illustrative purposes only, but the intermediate semiconductor structure 210 may include a greater number of die stacks depending on the size of the dies. For example, the wafer may be a circle with a diameter of 300 mm, and the die may be a 10x10 mm square. The semiconductor wafer stacks 212a-c may also include a greater number of dies in each wafer stack, such as 8, 12, or 16 dies.

[0034] Each of the semiconductor die stacks 212a-c may include a top die with a metal layer, similar to the semiconductor die stack 102 of FIG. 1. Each semiconductor die stack 212a-c can be formed by mounting one of the semiconductor die stacks 200a-c from FIG. 2E onto a core die stack 214. Thus, semiconductor die 200a-c serves as the top die of the semiconductor die stack 212a-c, similar to the top die 106 of FIG. 1. Semiconductor dies 200a-c can be mounted by thermocompression bonding (TCB), where TCB applies heat to the bonding impact die. TCB is typically a slow process, and the metal layer 206a-c on the back of the semiconductor die 200a-c can improve the transfer of applied heat, thereby enhancing the TCB process compared to conventional dies. Prior to TCB, a die attachment film (e.g., NCF) can be laminated onto the die. Alternatively, capillary bottom filler (CUF) can be applied to fill the gaps between the die stacks after TCB.

[0035] The core dies 214 can be mounted together using a process similar to that used to mount the top semiconductor die 200a, for example, by using a laminated die to attach a TCB film. The core dies 214 can be electrically interconnected via TSVs, which require less space between dies compared to wire bonding. However, bonding wires can also be used. The core dies 214 can be memory dies, such as DRAM.

[0036] Semiconductor die stacks 212a-c can be mounted on interface (IF) wafer 216. For example, core die 214 can be mounted on IF wafer 216 via TCB. IF wafer 216 may include multiple dies. For example, IF wafer 216 may include multiple logic dies, such as memory controllers or GPUs. In some embodiments, IF wafer 216 may include dies similar to core die 214. For example, both core die 214 and IF wafer 216 may contain memory dies. IF wafer 216 may include electrical connections such as circuitry or TSVs; for example, the IF wafer may include TSVs that can be exposed after back-side thinning.

[0037] After the semiconductor molds 200a-c are stacked on the core mold 214, the semiconductor die stacks 212a-c and the metal layers 206a-c can be at least partially surrounded by the molded part 220. For example, the molded part 220 can encapsulate these components. The molded part 220 can be any suitable molding compound used in semiconductor packaging, such as epoxy resin, and can be formed by injection molding, transfer molding, or compression molding.

[0038] Figure 2G is a cross-sectional view of an intermediate semiconductor structure 210 comprising a plurality of polished semiconductor die stacks 212a-c, according to an embodiment of the present invention. The intermediate semiconductor structure 210 can be polished using an abrasive wheel or polishing disc. Therefore, the metal layers 206a-c can show evidence of mechanical changes indicating wear of the wheel or disc. For example, evidence of such mechanical changes may include swirls, grooves, or other marks. The molded part 220 can be polished until the metal layers 206a-c are exposed and flush with the mold. This produces a device with an embedded heat sink, which can withstand further polishing by users who want thinner devices. After polishing and exposing the metal layers 206a-c, the intermediate semiconductor structure 210 can be attached to a carrier, and the IF wafer 216 can be thinned.

[0039] Figure 2H is a cross-sectional view of multiple diced semiconductor device packages 210a-c according to an embodiment of the present invention. The intermediate semiconductor structure 210 of Figure 2G can be diced into semiconductor device packages 210a-c by a dicing saw or other suitable dicing mechanism. Each of the diced semiconductor device packages 210a-c can be similar to the semiconductor device package 100 in Figure 1. As shown, the IF wafer 216 shown in Figure 2G can be diced into individual 216a-c dies. Furthermore, the intermediate semiconductor structure 210 of Figure 2G can be subjected to additional processing, such as back-side grinding, as part of the dicing process. For example, as shown in Figure 2G, due to such grinding, the dies 216a-c may be thinner than the IF wafer 216.

[0040] Figure 3 is a cross-sectional view of a semiconductor device assembly 300 including a semiconductor device package 302 coated with a grindable metal heat sink 306 according to an embodiment of the present invention. The semiconductor device package 302 may be similar to Figure 1 Semiconductor device package 100 and single-slice semiconductor device packages 210a-c of FIG. 2H. Semiconductor device package 302 includes a grindable metal heat sink 306 similar to the metal heat sink 112 of FIG. 1 and 2H and metal layers 206a-c.

[0041] Semiconductor device assembly 300 may be a memory device, such as a high-bandwidth memory (HBM) device. For example, semiconductor device package 302 may include a DRAM die stack interconnected by TSVs and mounted on a package substrate 310 adjacent to processor chip 304, such as a graphics processing unit (GPU) die. Semiconductor device package 302 may be coupled to processor die 304 (not shown) via an insert. Package substrate 310 may be mounted on PCB 320 as part of a larger system, for example using electrical connector 315. Note that this is only an illustrative example, and semiconductor device packages including embedded grindable heat sinks can be used in a variety of devices or systems, as described in Figure 5 below.

[0042] Figure 4 is a flowchart illustrating a method 400 for manufacturing a semiconductor device package according to an embodiment of the present invention. At 405, a metal layer is deposited onto a semiconductor wafer. For example, the metal layer may be similar to metal layer 206 of Figure 2D. In some embodiments, the semiconductor wafer is passivated prior to electroplating. The electroplating of the metal layer may include depositing a seed layer, such as… Figure 2C And the 2D seed layer 204.

[0043] At 410, the semiconductor wafer and the metal layer plated at 405 are diced to produce a semiconductor mold of multiple semiconductor dies. A portion of the metal layer remains plated on the semiconductor die. For example, the semiconductor wafer and metal layer can be diced using a dicing saw or other suitable dicing process. In some embodiments, the portion of the semiconductor die plated with the metal layer can then be mounted on a stack of semiconductor dies by methods such as thermoforming.

[0044] At 415, the semiconductor mold from step 410 encapsulates a molded part. For example, the molded part may be similar to molded part 140 of FIG. 1 and molded part 220 of FIG. 2F-H. In some embodiments, the molded package is mounted on a semiconductor die stack on a wafer, such as IF wafer 216 in FIG. 2F.

[0045] At 420, the molded part and the metal layer are ground. Grinding of the molded part and the metal layer can be performed simultaneously, for example, using a grinding wheel or grinding disc. After grinding at 420, the ground shaped surface of the metal layer may be coplanar with the ground surface. In some embodiments, the metal layer may exhibit grinding marks consistent with the wear of the grinding wheel.

[0046] Figure 5 is a schematic diagram of a system 500 including semiconductor devices according to an embodiment of the present invention. Any semiconductor device and / or chip having the features described in Figures 1-4 above can be incorporated into numerous larger and / or more complex systems, one representative example being the system 500 shown in Figure 5. System 500 may include a processor 502, a memory 505 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 506, and / or other subsystems or components 508. Semiconductor molds and / or packages as described in Figures 1-4 above may be included in any of the elements shown in Figure 5. The resulting system 500 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 500 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptops, internet devices, handheld devices (e.g., PDAs, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative examples of System 500 include lights, cameras, vehicles, etc. Regarding these and other examples, System 500 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of System 500 may accordingly include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0047] As can be understood from the foregoing, specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications can be made without departing from the scope of the invention. Therefore, the present invention is not limited except for the appended claims.

Claims

1. A semiconductor device package, comprising: A semiconductor die stack, comprising a top die and one or more core dies below the top die; A metal heat sink is plated on the top surface of the top mold and has multiple sides that are coplanar with corresponding sides of multiple sidewalls of the semiconductor mold stack. The seed layer between the top mold and the metal radiator; and A molded part surrounding the semiconductor die stack and the metal heat sink, the molded part including an upper surface coplanar with the exposed upper surface of the metal heat sink. The upper surface of the molded part and the exposed upper surface of the metal heat sink are both mechanically modified.

2. The semiconductor device package of claim 1, wherein the mechanically altered upper surface of the metal heat sink includes scratches.

3. The semiconductor device package of claim 1, wherein each of the plurality of sides and each of the plurality of sidewalls is mechanically altered.

4. The semiconductor device package of claim 3, wherein the mechanically altered side of the metal heat sink includes saw marks.

5. The semiconductor device package of claim 1, wherein the metal heat sink has a thickness between 100 micrometers and 200 micrometers.

6. The semiconductor device package of claim 1, wherein the metal heat sink is made of copper.

7. The semiconductor device package of claim 1, wherein the semiconductor die stack includes a die attachment film located between the top die and the one or more core dies.

8. The semiconductor device package of claim 1, wherein the top surface of the top mold is passivated.

9. A method for manufacturing a semiconductor device package, comprising: A metal layer is deposited on the back side of the semiconductor wafer; The semiconductor wafer is diced from the metal layer to produce a plurality of semiconductor molds, each of which is plated with a portion of the metal layer; A semiconductor die stack is formed, comprising a top die and one or more core dies below the top die. The top mold is one of the plurality of semiconductor molds. The portion of the metal layer forms a metal heat sink plated on the top surface of the top mold, the metal heat sink having multiple sides that are coplanar with corresponding sides of multiple sidewalls of the semiconductor mold stack; One of the plurality of semiconductor molds is encapsulated using a molding part; as well as Grinding the molded part and the portion of the metal layer, wherein after grinding, the surface of the ground molded part is coplanar with the ground surface of the portion of the metal layer. The molded part surrounds the semiconductor mold stack and the metal heat sink, and the molded part includes an upper surface coplanar with the exposed upper surface of the metal heat sink. The upper surface of the molded part and the exposed upper surface of the metal heat sink are both mechanically modified.

10. The method of claim 9, further comprising: The semiconductor wafer is mounted on a carrier before the metal layer is deposited on the back side of the semiconductor wafer; as well as After the metal layer is deposited, the semiconductor wafer is peeled off the carrier.

11. The method of claim 9, wherein depositing the metal layer comprises: The back side of the semiconductor wafer is passivated before the metal layer is deposited on the back side of the semiconductor wafer.

12. The method of claim 11, wherein depositing the metal layer further comprises: A seed layer is deposited on the passivated back side of the semiconductor wafer; as well as The metal layer is plated onto the seed layer.

13. The method of claim 9, further comprising: Before depositing the metal layer, the semiconductor wafer is thinned by chemical-mechanical planarization.

14. The method of claim 9, wherein forming the semiconductor mold stack comprises: Before using a molded component to encapsulate one of the plurality of semiconductor molds, the one of the plurality of semiconductor molds is mounted on a stack of the core mold. The molded part further encapsulates the stack of the core mold.

15. The method of claim 14, wherein the semiconductor mold is mounted on the semiconductor mold stack by thermoforming bonding.

16. The method of claim 9, wherein one of the plurality of semiconductor molds is a first semiconductor mold, the method further comprising: When using the molding part to encapsulate one of the plurality of semiconductor molds, the molding part is used to encapsulate a second semiconductor mold among the plurality of semiconductor molds, the second semiconductor mold having a second portion of the metal layer plated thereon; as well as While grinding the molded part and the portion of the metal layer, the second portion of the molded part and the metal layer is also ground. The first semiconductor mold and the second semiconductor mold are mounted on the same wafer, and After grinding the molded part and the second part of the metal layer, the ground surface of the molded part and the ground surface of the second part of the metal layer are coplanar with the second ground surface of the second part of the metal layer.

17. A semiconductor device assembly, comprising: Packaging substrate; Processor mold coupled to the packaging substrate; A semiconductor mold stack coupled to the packaging substrate and electrically connected to the processor mold, the semiconductor mold stack comprising: A top mold and multiple core molds below the top mold; A grindable metal heat sink is plated on the top surface of the top mold and has multiple sides that are coplanar with corresponding sides of multiple sidewalls of the semiconductor mold stack. The seed layer between the semiconductor mold and the metal heat sink; and The molded part surrounding the semiconductor mold stack and the grindable metal heat sink, The upper surface of the grindable metal heat sink is exposed to the molded part and is coplanar with the upper surface of the molded part. The upper surface of the molded part and the upper surface of the grindable metal radiator are both mechanically modified.

18. The semiconductor device assembly of claim 17, wherein the processor die is a graphics processing unit (GPU) die, and wherein the core die and the top die are memory dies.

19. The semiconductor device assembly of claim 17, wherein the upper surface of the grindable metal heat sink and the upper surface of the molded part show grinding marks from grinding wheel wear.

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