The voltage regulator circuit and its multi-stage amplifier circuit

Abstract

A voltage regulator circuit and a multi-stage amplifier circuit therein are disclosed. The multi-stage amplifier circuit includes: a preamplifier circuit for generating a preamplified signal based on the difference between a primary feedback signal and a primary reference signal related to an output signal; an output adjustment circuit for generating a drive signal based on the preamplified signal; and an output transistor controlled by the drive signal to generate an output signal. The output adjustment circuit includes: an adjustment transistor biased by the differential-mode current of the preamplified signal; and an impedance adjustment element biased by the differential-mode current of the preamplified signal, the resistance value of which is determined based on the difference between the adjustment feedback signal and the adjustment reference signal related to the output signal; the drive signal is determined based on the product of the resistance value of the impedance adjustment element and the differential-mode current of the preamplified signal, and the drain-source voltage of the adjustment transistor.

Description

Technical Field

[0001] This invention relates to a multi-stage amplifier circuit, and more particularly to a high-speed multi-stage amplifier circuit with multiple loops. The invention also relates to a voltage regulator circuit configured with the aforementioned multi-stage amplifier circuit. Background Technology

[0002] Figure 1 This invention discloses a prior art multi-stage amplifier circuit 100, comprising a preamplifier circuit 10 and an output stage circuit 20. The preamplifier circuit generates a preamplifier signal Vo1 based on the difference between input signals Vip and Vin. An output transistor MOL generates an output signal Vo based on the preamplifier signal Vo1. When the relationship between input signals Vip and Vin is in a steady state, the output transistor MOL determines the quiescent current of the output stage circuit 20 using a current mirror method based on the quiescent current of the preamplifier circuit. When the relationship between input signals Vip and Vin is transient, the output transistor MOL also provides partial current amplification. Vin is, for example, related to the output signal Vo.

[0003] Figure 1 The disadvantage of existing multi-stage amplifier circuits is that, under extremely low quiescent current applications, the output transistor MOL cannot provide the required current sink in real time, which may cause voltage overshoot. In addition, it may not be able to effectively absorb the leakage current of the output transistor MOH, resulting in excessively high voltage.

[0004] Figure 2 This illustrates a prior art multistage amplifier circuit 200. The multistage amplifier circuit 200 includes a preamplifier circuit 10 for generating a preamplified signal EAO based on the difference between a feedback signal VFB and a reference signal VREF. An output stage circuit 20 controls its output transistors MOH and MOL based on the preamplified signal EAO to generate an output signal Vo.

[0005] The output stage circuit 20 also includes an output adjustment circuit 25 for generating a drive signal VdrvL based on the preamplified signal EAO. The output transistor MOL is controlled by the drive signal VdrvL to generate an output signal Vo. The feedback signal VFB is related to the output signal Vo. The gate-source voltage of the output transistor MOL is determined by the drive signal VdrvL, which in turn determines the output current Io of the output signal Vo.

[0006] In this prior art, the output adjustment circuit 25 includes an adjustment transistor MC14 and an impedance adjustment element MC7. The adjustment transistor MC14 is biased by the branch current of the differential transistor M6. The impedance adjustment element MC7 is biased by the transistor M2 controlled by the preamplifier signal EAO, which generates a bias signal through transistor MC12 to adjust the resistance value of the impedance adjustment element MC7. The capacitor CM is a Miller compensation capacitor used for frequency compensation to improve stability.

[0007] When the output voltage Vo changes instantaneously, the difference between the feedback signal VFB and the reference signal VREF increases. The preamplifier signal EAO adjusts the resistance value of the impedance adjustment element MC7 through transistors M2 and MC12, thereby changing the drive signal VdrvL. This accelerates the output current Io that controls the output signal Vo. However, due to the effect of the Miller compensation capacitor CM, the preamplifier signal Vo1 reacts slowly. As a result, transistors MC12, MC7, and MC14 cannot respond quickly to the instantaneous change in output voltage Vo, and thus cannot quickly control the output transistors MOH and MOL to respond quickly to the instantaneous change in output voltage Vo. Summary of the Invention

[0008] According to one viewpoint, the present invention provides a multi-stage amplifier circuit, comprising: a preamplifier circuit for generating a preamplified signal based on the difference between a primary feedback signal and a primary reference signal; at least one output adjustment circuit for generating a drive signal based on the preamplified signal; at least one output transistor controlled by the corresponding drive signal to generate an output signal; wherein the primary feedback signal is related to the output signal, wherein a gate-source voltage of the output transistor is determined according to the drive signal, thereby determining an output current of the output signal; wherein the first output adjustment circuit includes: an adjustment transistor controlled by the preamplifier circuit for generating a preamplified signal based on the difference between a primary feedback signal and a primary reference signal; at least one output adjustment circuit for generating a drive signal based on the difference between a primary feedback signal and a primary reference signal; at least one output adjustment circuit for generating a drive signal based on the difference between a primary feedback signal and a primary reference signal; wherein the primary feedback signal is related to the output signal, wherein a gate-source voltage of the output transistor is determined according to the drive signal, thereby determining an output current of the output signal; wherein the first output adjustment circuit includes: an adjustment transistor controlled by the primary feedback signal ... first output adjustment circuit includes: a gate-source voltage of the output transistor for generating a drive signal based on the difference between a primary feedback signal and a primary reference signal; wherein the first output adjustment circuit includes: a gate-source voltage of the output transistor for generating a drive signal based on the difference between a primary feedback signal and a primary reference signal; wherein the first output adjustment circuit includes: a gate-source voltage of the output transistor for generating a drive signal based on the difference between a primary feedback signal and a primary reference signal; wherein the first output adjustment circuit includes: a gate-source voltage of the output transistor for generating a drive signal based on the difference between The system comprises: a differential-mode current biased by the preamplified signal; and an impedance adjustment circuit coupled to the adjustment transistor, the impedance adjustment circuit comprising: an impedance adjustment element biased by the differential-mode current of the preamplified signal, the resistance value of the impedance adjustment element being determined based on the difference between an adjustment feedback signal and an adjustment reference signal, wherein the adjustment feedback signal is related to the output signal; wherein the drive signal is determined based on a drain-source voltage of the adjustment transistor and a voltage across the impedance adjustment element, wherein the voltage across the impedance adjustment element is determined based on the product of the resistance value of the impedance adjustment element and the differential-mode current of the preamplified signal.

[0009] In a preferred embodiment, the impedance adjustment circuit further includes a transconductance amplifier circuit, which includes: a pair of differential transistors that generate an adjustment signal based on the difference between the adjustment feedback signal and the adjustment reference signal; and a transconductance transistor corresponding to the impedance adjustment element, wherein a resistance value of the transconductance transistor is adjusted according to the adjustment signal.

[0010] In a preferred embodiment, the resistance value of the transconducting transistor has a linear relationship with respect to the difference between the adjustment feedback signal and the adjustment reference signal.

[0011] In a preferred embodiment, when the output signal is transient, the transconducting transistor is biased and operates in the saturation region, thereby causing the resistance value of the transconducting transistor to be linearly adjusted according to the adjustment signal.

[0012] In a preferred embodiment, the transconducting transistor is connected in series with the regulating transistor.

[0013] In a preferred embodiment, the transconductance amplifier circuit is biased by a common-mode current of the preamplified signal.

[0014] In a preferred embodiment, the preamplifier circuit is configured as an operational amplifier to generate at least one pair of complementary transducer currents based on the difference between the primary feedback signal and the primary reference signal, wherein the common-mode current and the differential-mode current of the preamplifier signal are determined based on the pair of transducer currents.

[0015] In a preferred embodiment, the adjustment transistor is diode-coupled.

[0016] In a preferred embodiment, the gate of the adjustment transistor is biased by the drive signal.

[0017] In a preferred embodiment, the transconductance amplifier circuit further includes a load transistor coupled in a diode manner, wherein a current flowing through one of the pair of differential transistors is used to bias the load transistor to generate the adjustment signal.

[0018] In a preferred embodiment, there is an offset between an adjustment target value corresponding to the output adjustment circuit and an output target value of the preamplifier circuit, such that when the output signal exceeds the output target value by more than the offset value, the output adjustment circuit...

[0019] In a preferred embodiment, the at least one output transistor includes a first output transistor and a second output transistor having complementary conductivity types, and the at least one output adjustment circuit includes a first output adjustment circuit and a second output adjustment circuit, which are respectively used to generate the corresponding drive signal according to the preamplified signal, and correspondingly control the first output transistor and the second output transistor to generate the output signal.

[0020] In a preferred embodiment, the circuit configuration of the first output adjustment circuit and the circuit configuration of the second output adjustment circuit are complementary to each other, thereby making the drive signal of the first output adjustment circuit and the drive signal of the second output adjustment circuit complementary to each other, and thus making the first output transistor and the second output transistor generate the output signal in a push-pull manner.

[0021] In a preferred embodiment, the first output transistor, the second output transistor, the first output adjustment circuit, and the second output adjustment circuit are configured as an AB-level output stage circuit.

[0022] In a preferred embodiment, the multi-stage amplifier circuit is configured as an operational amplifier.

[0023] In a preferred embodiment, the multi-stage amplifier circuit further includes a compensation capacitor coupled between the preamplified signal and the output signal to provide frequency compensation.

[0024] From another perspective, the present invention also provides a regulator circuit comprising: a multi-stage amplifier circuit as described in any of the preceding embodiments; and a feedback circuit coupled to the output signal for generating the main feedback signal and the adjustment feedback signal, such that the multi-stage amplifier circuit adjusts the output signal to a target output value.

[0025] In a preferred embodiment, the output adjustment circuit has an output offset value between an adjustment target value and the output target value, such that when the output signal exceeds the output target value by more than the offset value, the corresponding output adjustment circuit controls the corresponding output transistor according to the adjustment target value, thereby instantly and quickly adjusting the output signal so that it does not exceed the sum of the output target value and the offset value.

[0026] The multi-stage amplifier circuit of the present invention can control the bias current of the output transistor with another loop in an instantaneous manner, so as to improve the loop bandwidth and response speed.

[0027] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0028] Figure 1This demonstrates existing multi-stage amplifier circuits.

[0029] Figure 2 This demonstrates existing multi-stage amplifier circuits.

[0030] Figure 3 A circuit block diagram showing an embodiment of the multi-stage amplifier circuit of the present invention is shown.

[0031] Figure 4 and Figure 5 This diagram shows two embodiments of the adjusting transistor in the multi-stage amplifier circuit of the present invention.

[0032] Figure 6 and Figure 7 This diagram shows two embodiments of the multi-stage amplifier circuit of the present invention, which includes multiple output transistors.

[0033] Figure 8 This diagram shows a circuit block diagram of an embodiment of the transconductance amplifier circuit in the multi-stage amplifier circuit of the present invention.

[0034] Figures 9-11 This invention shows circuit diagrams of several embodiments of the transconductance amplifier circuit in the multi-stage amplifier circuit of the present invention.

[0035] Figure 12 and Figure 13 The circuit block diagrams shown illustrate two embodiments of the multi-stage amplifier circuit of the present invention, which include complementary output transistors.

[0036] Figure 14 and Figure 15 This invention shows circuit diagrams illustrating two specific embodiments of a multi-stage amplifier circuit that includes complementary output transistors.

[0037] Figure 16 and Figure 17 Circuit diagrams showing two specific embodiments of the multi-stage amplifier circuit of the present invention configured as an operational amplifier.

[0038] Figure 18 A circuit diagram showing a specific embodiment of the voltage regulator circuit of the present invention is shown.

[0039] Explanation of symbols in the diagram

[0040] 10: Preamplifier Circuit

[0041] 100, 200, 300, 400, 500, 600, 700: Multistage amplifier circuits

[0042] 1600, 1700: Multistage amplifier circuit

[0043] 106: Transconductance Amplifier

[0044] 1800: Voltage Regulator Circuit

[0045] 20: Output stage circuit

[0046] 21, 22, 25: Output adjustment circuit

[0047] 211: Impedance Adjustment Circuit

[0048] 2109, 2110, 21_11: Transconductance amplifier circuit

[0049] 2111: Impedance Adjustment Element

[0050] 2114, 2214: Transconductance amplifier circuits

[0051] 212: Adjusting the transistor

[0052] 218: Transconductance Amplifier Circuit

[0053] 2181: Impedance Adjustment Element

[0054] 2182: Differential Pair

[0055] 50: Feedback circuit

[0056] CM: Compensation capacitor

[0057] EAO: Preamplifier signal

[0058] ICM1P, ICM1N, ICM2P, ICM2N: Common-mode current

[0059] IDM, IDM1, IDM2: Differential mode current

[0060] Io: Output current

[0061] MC7: Impedance Adjustment Element

[0062] M1, M2, M6, MC12: Transistors

[0063] M11, M12, M13, M14: Transistors

[0064] M1L, M2L, M1H, M2H: Differential transistors

[0065] M3L, M3H: Load transistors

[0066] M4, M4L, M4H: Transconducting transistors

[0067] M5L, M5H: Adjusting transistors

[0068] MC14: Adjusting transistor

[0069] MOH, MOL: Output transistors

[0070] VAL: Adjust signal

[0071] VdrvL, VdrvH: Drive signals

[0072] VFBL, VFBH: Adjust the feedback signal

[0073] VFB: Feedback signal

[0074] VFBP: Main Feedback Signal

[0075] VDS: Drain-Source Voltage

[0076] Vip, Vin: Input signals

[0077] Vo: Output signal

[0078] Vo1: Preamplifier signal

[0079] VREF: Reference Signal

[0080] VREFL, VREFH: Adjusting the reference signal Detailed Implementation

[0081] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0082] Figure 3 A circuit block diagram showing another embodiment of the multi-stage amplifier circuit of the present invention is shown. The multi-stage amplifier circuit 300 includes a preamplifier circuit 10 and an output stage circuit 20. The preamplifier circuit 10 generates a preamplified signal EAO based on the difference between a primary feedback signal VFBP and a primary reference signal VREFP. The output stage circuit 20 includes at least one output adjustment circuit (such as output adjustment circuit 21) and at least one output transistor (such as output transistor MOL). The output adjustment circuit 21 generates a drive signal VdrvL based on the preamplified signal EAO, and the output transistor MOL is controlled by the corresponding drive signal VdrvL to generate an output signal Vo.

[0083] The main feedback signal VFBP is related to the output signal Vo, where the gate-source voltage of the output transistor MOL is determined by the drive signal VdrvL, which in turn determines the output current Io of the output signal Vo.

[0084] In one embodiment, the output adjustment circuit 21 includes an adjustment transistor 212 and an impedance adjustment circuit 211. The adjustment transistor 212 is biased by the differential-mode current of the preamplified signal EAO, details of which will be described later.

[0085] Impedance adjustment circuit 211 is coupled to adjustment transistor 212. In one embodiment, impedance adjustment circuit 211 includes impedance adjustment element 2111, which is biased by the differential mode current IDM of the pre-amplified signal EAO. Simultaneously, as... Figure 3 As shown, the resistance value of the impedance adjustment element 2111 is determined according to the difference between the adjustment feedback signal VFBL and the adjustment reference signal VREFL, wherein the adjustment feedback signal VFBL is related to the output signal Vo.

[0086] The drive signal VdrvL is determined by the drain-source voltage VDS of the adjustment transistor 212 and the voltage across the impedance adjustment element 2111. The voltage across the impedance adjustment element 2111 is determined by the product of its resistance value and the differential-mode current IDM of the preamplified signal EAO. In this embodiment, since the resistance value of the impedance adjustment element 2111 is directly determined by the difference between the adjustment feedback signal VFBL and the adjustment reference signal VREFL, compared to... Figure 2 The multi-stage amplifier circuit 200, with its impedance adjustment element 2111, allows the resistance value to respond more quickly to changes in the output signal Vo (which also adjusts the feedback signal VFBL), thus enabling the drive signal VdrvL and the output current Io to respond more quickly, and consequently allowing the output signal Vo to return to a steady state more rapidly. Details will be provided in the following embodiments.

[0087] In one embodiment, the resistance value of the impedance adjustment element 2111 is positively correlated with the difference between the adjustment feedback signal VFBL and the adjustment reference signal VREFL.

[0088] Figure 4 and Figure 5 This diagram shows two embodiments of the adjusting transistor in the multi-stage amplifier circuit of the present invention. These two embodiments can correspond to... Figure 3 In one embodiment, the adjusting transistor 212 is diode-coupled ( Figure 4 In another embodiment, the gate of the adjusting transistor 212 is biased to the drive signal VdrvL ( Figure 5 ).

[0089] Figure 6 and Figure 7 This diagram shows two embodiments of the multi-stage amplifier circuit of the present invention, which includes multiple output transistors. Figure 6 and Figure 7 Corresponding to Figure 4and Figure 5 More specific embodiments, Figure 6 and Figure 7 The output stage circuit 20 further includes an output transistor MOH, which generates an output signal Vo based on the pre-amplified signal EAO. The output transistors MOH and MOL have complementary conductivity types. Figure 6 and Figure 7 In one embodiment, the output transistor MOH is a PMOS transistor, while the output transistor MOL is an NMOS transistor.

[0090] Figure 8 This diagram shows a circuit block diagram of an embodiment of the transconductance amplifier circuit in the multi-stage amplifier circuit of the present invention. In one embodiment, the impedance adjustment circuit 211 includes a transconductance amplifier circuit 218. In another embodiment, the transconductance amplifier circuit 218 includes a differential pair 2182 formed by a pair of differential transistors M1 and M2, and a transconductance transistor M4. The differential transistors M1 and M2 generate an adjustment signal VAL based on the difference between the adjustment feedback signal VFBL and the adjustment reference signal VREFL. In one embodiment, the adjustment signal VAL is generated based on the differential-mode current of the differential transistors M1 and M2. In this embodiment, the transconductance transistor M4L corresponds to the impedance adjustment element 2181, wherein the resistance value of the transconductance transistor M4L is adjusted according to the adjustment signal VAL.

[0091] Figures 9-11 This invention shows circuit diagrams illustrating several specific embodiments of the impedance adjustment circuit implemented using a transconductance amplifier circuit in the multi-stage amplifier circuit of the present invention.

[0092] In one embodiment, such as Figure 9 As shown, the transconductance amplifier circuit 2109 also includes a load transistor M3L coupled in a diode manner, wherein the current flowing through the differential transistor M1L is used to bias the load transistor, and an adjustment signal VAL is generated in a current mirror manner to adjust the resistance value of the transconductance transistor M4L.

[0093] like Figure 10 As shown, the transconductance amplifier circuit 2110 generates the drive signal VdrvL in a push-pull current control manner, as follows: Figure 11 As shown, the transconductance amplifier circuit 21_11 implements the adjustable resistance value transconductance transistor M4L and the drive signal VdrvL in a folded stacked manner, wherein the bias voltage VB is used to provide the gate bias voltage of transistors M3L' and M4L.

[0094] In one embodiment, the transconductance amplifier circuit is configured such that the resistance value of the transconductance transistor M4L has a linear relationship with respect to the difference between the adjustment feedback signal VFBL and the adjustment reference signal VREFL. In this case, compared to the response of the preamplifier circuit 10 to the drive signal VdrvL based on the difference between the main feedback signal VFBP and the main reference signal VREFP, when the adjustment feedback signal VFBL and the adjustment reference signal VREFL have a difference, the drive signal VdrvL can have a larger response amplitude. Therefore, for example, the multi-stage amplifier circuit in the aforementioned embodiment can improve the instantaneous response speed of the output transistor MOL, the output current Io, and the output signal Vo through the rapid response of the transconductance transistor (M4L) in the transconductance amplifier circuit. From one perspective, the transconductance amplifier circuit provides a feedforward loop in the multi-stage amplifier circuit.

[0095] Specifically, in one embodiment, when the output signal Vo changes instantaneously, the transconducting transistor M4L is biased and operates in the saturation region, thereby causing the resistance value of the transconducting transistor M4L to be linearly adjusted according to the adjustment signal VAL. Figure 9 For example, when the adjustment feedback signal VFBL rises and is higher than the adjustment reference signal VREFL, the differential transistor M1L and transistor M3L will receive a smaller current compared to the right branch. Therefore, the adjustment signal VAL will decrease, causing the resistance value of the transconducting transistor M4L to increase. On the other hand, the differential transistor M2L obtains a larger differential mode current IDM1, which in turn causes the drive signal VdrvL to increase effectively and quickly. This can quickly increase the current of the output transistor MOL, and make the output signal Vo respond quickly.

[0096] Figure 12 and Figure 13 The circuit block diagrams shown illustrate two embodiments of the multi-stage amplifier circuit of the present invention, which include complementary output transistors. Figure 12 and Figure 13 Corresponding to Figure 6 and Figure 7 More specific embodiments, Figure 12 and Figure 13 The output transistors MOH and MOL have complementary conductivity types. Figure 12 and Figure 13The output stage circuit 20 further includes an output adjustment circuit 22, which, using the same concept as the output adjustment circuit 21, adjusts the drive signal VdrvH based on the difference between the adjustment feedback signal VFBH and the adjustment reference signal VREFH, thereby controlling the output transistor MOH. In these two embodiments, the output transistor MOH and the output transistor MOL generate the output signal Vo in a push-pull manner. In this embodiment, the adjustment transistor M5L corresponds to the aforementioned adjustment transistor 212.

[0097] See also Figures 12-15 , Figure 14 and Figure 15 This invention shows circuit diagrams of two specific embodiments of a multi-stage amplifier circuit (multi-stage amplifier circuits 1400, 1500) including complementary output transistors. Figure 14 and Figure 15 Corresponding to Figure 12 and Figure 13 More specific embodiments. In one embodiment, such as Figure 14 and Figure 15 As shown, the circuit configuration of the output adjustment circuit 21 and the circuit configuration of the output adjustment circuit 22 are complementary in conductivity, thereby making the drive signal VdrvL generated by the output adjustment circuit 21 and the drive signal VdrvH generated by the output adjustment circuit 22 complementary to each other, thereby controlling the complementary output transistors MOL and MOH to generate the output signal Vo in a push-pull manner.

[0098] Specifically, transistors M1H, M2H, M3H, M4H, and M5H complementarily correspond to the functions of the aforementioned transistors M1L, M2L, M3L, M4L, and M5L, respectively, where transistors M5H and M5L correspond to the adjustment transistors in output adjustment circuit 22 and output adjustment circuit 21, respectively. The adjustment signal VAH complementarily corresponds to the adjustment signal VAL.

[0099] From one perspective, in one embodiment, the transducer M4L is connected in series with the regulating transistor M5L, and the transducer M4H is connected in series with the regulating transistor M5H. For example... Figure 14 and Figure 15As shown, in one embodiment, at an instant, when the feedback signal VFBP differs from the reference signal VREFP, but the signal from the preamplifier circuit 10 has not yet been effectively transmitted to the bias transistors M11 and M12 due to, for example, compensation, the large-signal common-mode currents ICM1P and ICM1N of the bias transistors M11 and M12 are substantially nearly equal under the above conditions. At this time, the transconductance amplifier circuit 2114 is substantially subjected to the common-mode currents ICM1P and ICM1N biased on the preamplifier signal EAO. On the other hand, the difference between the feedback signal VFBL and the reference signal VREFL is sufficient to cause the resistance value of the transconductance transistor M4L to change effectively in advance in response to the difference between the feedback signal VFBL and the reference signal VREFL. Therefore, the differential-mode current IDM1 of the transconductance amplifier circuit 2114 generates a drive signal VdrvL through the resistance values ​​of the transconductance transistor M4L and the adjustment transistor M5L. The drive signal VdrvL effectively responds to the difference between the feedback signal VFBL and the reference signal VREFL earlier, without being limited by the slower response speed of the preceding amplification signal EAO. The operation strategy of the transconductance amplifier circuit 2214 is the same as described above and will not be repeated here.

[0100] It is worth noting that, since the large-signal common-mode currents ICM1P and ICM1N of bias transistors M11 and M12 are practically equal (the same applies to ICM2P and ICM2N), therefore, from one perspective, as Figure 12 and Figure 13 As shown, transistor M5L (adjustment transistor) is biased by the differential mode current IDM1 of the preamplifier signal EAO, and transistor M5H (adjustment transistor) is biased by the differential mode current IDM2 of the preamplifier signal EAO.

[0101] From one perspective, in Figures 12-15 In this embodiment, the output transistor MOH, the output transistor MOL, the output adjustment circuit 22, and the output adjustment circuit 21 are configured as an AB-level output stage circuit.

[0102] Figure 16 and Figure 17 Circuit diagrams showing two specific embodiments of the multi-stage amplifier circuit of the present invention configured as an operational amplifier are illustrated. For example... Figure 16 and Figure 17As shown in these two embodiments, the multi-stage amplifier circuits 1600 and 1700 of the present invention are configured as operational amplifiers. In one embodiment, the preamplifier circuit 10 is configured as a transconductance amplifier (such as 106) to generate at least one pair of complementary transconductance currents (i.e., ICM1P and ICM1N, or ICM2P and ICM2N) based on the difference between the primary feedback signal VFBP and the primary reference signal VREFP, wherein the common-mode current and differential-mode current (i.e., IDM1 or IDM2) generated by the preamplifier signal are determined based on the aforementioned transconductance currents.

[0103] It is worth noting that, in one embodiment, the multi-stage amplifier circuit of the present invention (such as...) Figure 17 The multi-stage amplifier circuit (1700) also includes a Miller compensation capacitor CM, which is coupled between the output signal Vo and the pre-amplified signal EAO, to perform frequency compensation and improve the stability of the multi-stage amplifier circuit. Please also review Figure 1 and Figure 2 ,like Figure 1 and Figure 2 In the existing technology, when the output voltage Vo changes instantaneously, the effect of the Miller compensation capacitor CM will cause the front-end signal Vo1 to respond slowly. Therefore, the transistor MC14 cannot respond quickly to the instantaneous change of the output voltage Vo, and thus cannot quickly control the output transistors MOH and MOL to respond quickly to the instantaneous change of the output voltage Vo.

[0104] In contrast, the multi-stage amplifier circuit of this invention provides an output adjustment circuit (such as...). Figure 17 The output adjustment circuits 21 and 22 in the multi-stage amplifier circuit 1700, as mentioned above, can directly and quickly respond to the instantaneous change of the output voltage Vo, and can dominate the instantaneous response of the drive signals VdrvL and VdrvH in real time, thereby controlling the output transistors MOH and MOL to quickly respond to the instantaneous change of the output voltage Vo.

[0105] In one embodiment, the target adjustment value of the output signal Vo corresponding to the output adjustment circuit (21, 22) in the aforementioned embodiment is the same as the target output value of the output signal Vo corresponding to the preamplifier circuit 10. This can be achieved, for example, by having the same feedback gain and configuring the main reference signal VREFP, the adjustment reference signal VREFL, and the adjustment reference signal VREFH to be the same.

[0106] In another embodiment, the target adjustment value of the output signal Vo corresponding to the output adjustment circuit (21, 22) has an output offset value between it and the target output value of the output signal Vo corresponding to the preamplifier circuit 10, such that when the output signal Vo exceeds the target output value and is greater than the output offset value, the output adjustment circuit (21, 22) controls the main loop. Figure 3 For example, in one embodiment, the adjustment reference signal VREFL is greater than the main reference signal VREFP - the reference offset value. In this case, when the adjustment feedback signal VFBL is higher than the adjustment reference signal VREFL (that is, the output signal Vo is higher than the output target value and the output offset value), the loop controlled by the output adjustment circuit 21 will dominate the strength of the feedback. Therefore, even when the loop of the preamplifier 10 has not yet had enough response to control the output transistor MOL, the loop controlled by the output adjustment circuit 21 can dominate the control of the output transistor MOL.

[0107] Figure 18 This diagram shows a circuit schematic of a specific embodiment of the voltage regulator circuit of the present invention. The voltage regulator circuit 1800 may include any of the aforementioned multi-stage amplifier circuits and feedback circuit 50. For example, Figure 18 Therefore, as Figure 7 and Figure 9 The embodiments are combined, and the feedback circuit 50 is used, for example, to divide the output signal Vo to generate the main feedback signal VFBP and the adjustment feedback signal VFBL. In this embodiment, the preamplifier circuit 10 generates the preamplifier signal EAO according to the difference between the main feedback signal VFBP and the main reference signal VREFP, and then adjusts the output signal Vo to the output target value.

[0108] Furthermore, in this embodiment, the adjustment feedback signal VFBL of the output adjustment circuit 21 is directly coupled to the main feedback signal VFBP, wherein 2114 is, for example, the aforementioned transconductance amplifier circuit.

[0109] In one embodiment, the reference signal VREFP and the adjustment reference signal VREFL are configured to be the same.

[0110] In another embodiment, the adjustment reference signal VREFL is greater than the primary reference signal VREFP—a reference offset value. In this case, when the adjustment feedback signal VFBL is higher than the adjustment reference signal VREFL (i.e., indicating that the output signal Vo exceeds the output target value by more than the output offset value), the loop controlled by the output adjustment circuit 21 will dominate the strength of the feedback. Therefore, even when the loop of the preamplifier 10 has not yet had sufficient response to control the output transistor MOL, the loop controlled by the output adjustment circuit 21 can dominate the control of the output transistor MOL, thereby instantly and quickly adjusting the output signal Vo so that it does not exceed the sum of the output target value and the output offset value. In one embodiment, the above configuration can be applied to functions such as overvoltage protection, wherein the overvoltage threshold can be, for example, the sum of the aforementioned output target value and the output offset value.

[0111] Continue reading Figure 18On the other hand, in the embodiment where the adjustment reference signal VREFL and the main reference signal VREFP have a difference (reference offset value), under steady state, the output signal Vo is adjusted to the output target value by the pre-amplifier circuit 10 according to the difference between the main feedback signal VFBP and the main reference signal VREFP. Since the output signal is lower than the adjustment target value at this time, the adjustment feedback signal VFBL is lower than the adjustment reference signal VREFL. In this case, the common-mode currents ICM1P and ICM1N only flow through the differential transistor M1L and the load transistor M3L, while the differential transistor M2L is in the cutoff state and the transconductance transistor M4L is in the on state. Therefore, the adjustment transistor M5L and the output transistor MOL are also basically in the off state. In other words, in this embodiment, the multi-stage amplifier circuit of the present invention can save power loss during steady-state operation and can respond quickly in the instantaneous state.

[0112] It is worth noting that the multi-stage circuit operation of this invention, even when simulating the instantaneous response of the output signal Vo over a large signal range (e.g., exceeding the applicability of the small-signal model) and thereby obtaining the bias state, allows for reliable simulation calculations by further analyzing the gain or phase margins of the AC model. In contrast, existing technologies, when dealing with large variations in the output signal Vo, fail to effectively reflect the true stability through their AC model's gain or phase margin analysis.

[0113] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the broadest scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many combinations, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A multi-stage amplifier circuit, characterized in that, Include: A preamplifier circuit for generating a preamplified signal based on the difference between a primary feedback signal and a primary reference signal; At least one output adjustment circuit is provided to generate a drive signal based on the preamplified signal. as well as At least one output transistor is controlled by the corresponding drive signal to generate an output signal; The main feedback signal is related to the output signal, wherein the gate-source voltage of the output transistor is determined according to the drive signal, which in turn determines the output current of the output signal; Each of the at least one output adjustment circuit includes: A regulating transistor, biased by a differential current of the preamplified signal; and An impedance adjustment circuit is coupled to the gate and drain of the adjustment transistor, the impedance adjustment circuit comprising: An impedance adjustment element is biased by the differential mode current of the preamplified signal. The resistance value of the impedance adjustment element is determined based on the difference between an adjustment feedback signal and an adjustment reference signal, wherein the adjustment feedback signal is related to the output signal. The drive signal is determined by the drain-source voltage of the adjusting transistor and the voltage across the impedance adjustment element, wherein the voltage across the impedance adjustment element is determined by the product of the resistance value of the impedance adjustment element and the differential mode current of the preamplified signal.

2. The multi-stage amplifier circuit as described in claim 1, wherein, The impedance adjustment circuit also includes a transconductance amplifier circuit, which includes: A pair of differential transistors generates an adjustment signal based on the difference between the adjustment feedback signal and the adjustment reference signal; A transconducting transistor, corresponding to the impedance adjustment element, wherein a resistance value of the transconducting transistor is adjusted according to the adjustment signal.

3. The multi-stage amplifier circuit as described in claim 2, wherein, The resistance value of the transconducting transistor has a linear relationship with respect to the difference between the adjustment feedback signal and the adjustment reference signal.

4. The multi-stage amplifier circuit as described in claim 3, wherein, When the output signal changes instantaneously, the transconducting transistor is biased and operates in the saturation region, thereby causing the resistance value of the transconducting transistor to be linearly adjusted according to the adjustment signal.

5. The multi-stage amplifier circuit as described in claim 2, wherein, The transconducting transistor is connected in series with the regulating transistor.

6. The multi-stage amplifier circuit as described in claim 2, wherein, The transconducting amplifier circuit is biased by a common-mode current in the preamplified signal.

7. The multi-stage amplifier circuit as described in claim 6, wherein, The preamplifier circuit is configured as an operational amplifier to generate at least one pair of complementary transducer currents based on the difference between the primary feedback signal and the primary reference signal, wherein the common-mode current and the differential-mode current of the preamplifier signal are determined based on the pair of transducer currents.

8. The multi-stage amplifier circuit as described in claim 2, wherein, The regulating transistor is coupled in a diode manner.

9. The multi-stage amplifier circuit as described in claim 2, wherein, The gate of the adjusting transistor is biased by the drive signal.

10. The multi-stage amplifier circuit as described in claim 2, wherein, The transconductance amplifier circuit also includes a load transistor coupled in a diode manner, wherein a current flowing through one of the pair of differential transistors is used to bias the load transistor to generate the adjustment signal.

11. The multi-stage amplifier circuit as described in claim 2, wherein, The output adjustment circuit has an offset value between an adjustment target value and an output target value of the preamplifier circuit, such that when the output signal exceeds the output target value and the difference between the output signal and the output target value is greater than the offset value, the output adjustment circuit controls the corresponding output transistor according to the adjustment target value, thereby instantly and quickly adjusting the output signal so that it does not exceed the sum of the output target value and the offset value.

12. The multi-stage amplifier circuit as described in claim 2, wherein, The at least one output transistor includes a first output transistor and a second output transistor having complementary conductivity types. The at least one output adjustment circuit includes a first output adjustment circuit and a second output adjustment circuit, which are respectively used to generate the corresponding drive signal according to the preamplified signal, and correspondingly control the first output transistor and the second output transistor to generate the output signal.

13. The multi-stage amplifier circuit as described in claim 12, wherein, The circuit configuration of the first output adjustment circuit is complementary to that of the second output adjustment circuit, thereby making the drive signal of the first output adjustment circuit complementary to that of the second output adjustment circuit, and thus enabling the first output transistor and the second output transistor to generate the output signal in a push-pull manner.

14. The multi-stage amplifier circuit as described in claim 13, wherein, The first output transistor, the second output transistor, the first output adjustment circuit, and the second output adjustment circuit are configured as an AB-level output stage circuit.

15. The multi-stage amplifier circuit as described in claim 1, wherein, It also includes a compensation capacitor coupled between the preamplified signal and the output signal to provide frequency compensation.

16. The multi-stage amplifier circuit as described in claim 14, wherein, This multi-stage amplifier circuit is configured as an operational amplifier.

17. A voltage regulator circuit, characterized in that, Include: The multi-stage amplifier circuit as described in any one of claims 1 to 15; and A feedback circuit, coupled to the output signal, is used to generate the main feedback signal and the adjustment feedback signal, so that the multi-stage amplifier circuit adjusts the output signal to a target output value.

18. The voltage regulator circuit as described in claim 17, wherein, The output adjustment circuit has an output offset value between an adjustment target value and the output target value, such that when the output signal exceeds the output target value and the difference between the output signal and the output target value is greater than the offset value, the corresponding output adjustment circuit controls the corresponding output transistor according to the adjustment target value, thereby instantly and quickly adjusting the output signal so that it does not exceed the sum of the output target value and the offset value.

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