Duty cycle correction circuit and chip

Abstract

The application provides a duty cycle correction circuit and a chip. In two adjacent comparison periods, the voltage of a first input end and a second input end of a comparator is exchanged (or flipped), or the clock signal of an input end of a first charge pump module and an input end of a second charge pump is exchanged (or flipped), so that the influence of the input offset of the two input ends of the comparator on the high and low levels of the clock signal is the same, the inherent error of duty cycle adjustment is eliminated, and a clock signal with a more balanced duty cycle is finally obtained.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a duty cycle correction circuit and chip. Background Technology

[0002] Typically, clock signals are used as reference signals to synchronize the operating timing between internal and external circuits of certain chips (such as dynamic random access memory). However, when the clock signal from the external circuit is applied to the internal circuit, it often causes clock skew (including delay or clock deviation) due to signal paths within the internal circuit. Therefore, phase-locked loop (PLL) circuits and duty cycle correction circuits are usually used in conjunction to address this issue. The PLL circuit can be a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop) circuit, used to synchronize the clock signals of the internal and external circuits to resolve clock skew, ensuring sufficient clock delay margin between the chip's internal and external circuits, thereby improving the system's timing functionality. The duty cycle correction circuit adjusts the clock duty cycle (typically 50%), allowing data to be sampled on both the rising and falling edges of the clock signal (i.e., high-speed data input and output operations), thereby increasing the signal transmission rate.

[0003] However, existing duty cycle correction circuits have a fixed adjustment error in the duty cycle, which ultimately results in an eye diagram with different sizes of eyes being seen at the data transmission end. Summary of the Invention

[0004] The purpose of this invention is to provide a duty cycle correction circuit and chip that can eliminate the adjustment error of a fixed duty cycle.

[0005] To achieve the above objectives, the present invention provides a duty cycle correction circuit, comprising a first charge pump module, a second charge pump module, a comparator, a control module, a duty cycle correction module, and a frequency divider module; wherein in each comparison cycle, the frequency divider module generates a first clock signal and a second clock signal based on the clock signal output by the duty cycle correction module; the input terminal of the control module is connected to the output terminal of the comparator, and the control module is used to generate a corresponding control signal according to the comparison result of the comparator and provide it to the duty cycle correction module; the duty cycle correction module outputs a clock signal with a changing duty cycle according to the control signal output by the control module.

[0006] In the first comparison period, the first input terminal of the comparator is coupled to the output terminal of the first charge pump module, and the second input terminal of the comparator is coupled to the output terminal of the second charge pump module. In the second comparison period, the first input terminal of the comparator is coupled to the output terminal of the second charge pump module, and the second input terminal of the comparator is coupled to the output terminal of the first charge pump module. In both the first and second comparison periods, the input terminal of the first charge pump module receives the first clock signal, and the input terminal of the second charge pump module receives the second clock signal.

[0007] Alternatively, in the first comparison period, the input terminal of the first charge pump module receives the first clock signal, and the input terminal of the second charge pump module receives the second clock signal. In the second comparison period, the input terminal of the first charge pump module receives the second clock signal, and the input terminal of the second charge pump module receives the first clock signal. In both the first and second comparison periods, the first input terminal of the comparator is coupled to the output terminal of the first charge pump module, and the second input terminal of the comparator is coupled to the output terminal of the second charge pump module.

[0008] Optionally, the duty cycle correction circuit further includes first to fourth channel switches. The input terminals of the first and fourth channel switches are both connected to the output terminal of the first charge pump module. The input terminals of the second and third channel switches are both connected to the output terminal of the second charge pump module. The output terminals of the first and third channel switches are both connected to the first input terminal of the comparator. The output terminals of the second and fourth channel switches are both connected to the second input terminal of the comparator. The control terminals of the first and second channel switches are connected to a first control signal. The control terminals of the third and fourth channel switches are connected to a second control signal, and the second control signal is the inverted signal of the first control signal.

[0009] Optionally, the duty cycle correction circuit further includes a fifth channel switch and a sixth channel switch. The fifth channel switch is coupled between the input terminals of the frequency divider module and the first charge pump module, and the sixth channel switch is coupled between the input terminals of the frequency divider module and the second charge pump module. The control terminals of the fifth channel switch and the sixth channel switch are both connected to a third control signal.

[0010] Optionally, the duty cycle correction circuit further includes a third to a fifth channel switch. The fifth channel switch is coupled between the input terminals of the frequency divider module and the first charge pump module. The sixth channel switch is coupled between the input terminals of the frequency divider module and the second charge pump module. The input terminal of the third channel switch is connected to the input terminal of the sixth channel switch, and the output terminal of the third channel switch is connected to the output terminal of the fifth channel switch. The input terminal of the fourth channel switch is connected to the input terminal of the fifth channel switch, and the output terminal of the fourth channel switch is connected to the output terminal of the sixth channel switch. The control terminals of the fifth and sixth channel switches are both connected to a third control signal, and the control terminals of the third and fourth channel switches are both connected to a fourth control signal, which is the inverted signal of the third control signal.

[0011] Optionally, the duty cycle correction circuit further includes a first channel switch and a second channel switch. The first channel switch is coupled between the output terminal of the first charge pump module and the first input terminal of the comparator, and the second channel switch is coupled between the output terminal of the second charge pump module and the second input terminal of the comparator. The control terminals of the first channel switch and the second channel switch are both connected to a first control signal.

[0012] Optionally, the first charge pump module includes a first current source, a first MOSFET, a second MOSFET, a second current source, and a first capacitor, wherein the first current source, the first MOSFET, the second MOSFET, and the second current source are connected in series, one end of the first capacitor is connected to the series node of the first MOSFET and the second MOSFET to form the output terminal of the first charge pump module, and the gate terminal of the first MOSFET and the gate terminal of the second MOSFET are connected to form the input terminal of the first charge pump module.

[0013] And / or, the second charge pump module includes a third current source, a third MOSFET, a fourth MOSFET, a fourth current source, and a second capacitor, wherein the third current source, the third MOSFET, the fourth MOSFET, and the fourth current source are connected in series, one end of the second capacitor is connected to the series node of the third MOSFET and the fourth MOSFET to form the output terminal of the second charge pump module, and the gate terminal of the third MOSFET and the gate terminal of the fourth MOSFET are connected to form the input terminal of the second charge pump module.

[0014] Optionally, the duty cycle correction module includes a first inverter and multiple duty cycle correction units. The input terminal of the first inverter is interconnected with the input terminals of all the duty cycle correction units to form the input terminal of the duty cycle correction module, and the output terminal of the first inverter is interconnected with the output terminals of all the duty cycle correction units to form the output terminal of the duty cycle correction module.

[0015] Optionally, it further includes a negative feedback module, which includes a second inverter, a seventh channel switch, and an eighth channel switch. The input terminals of the second inverter and the seventh channel switch are both connected to the output terminal of the comparator. The output terminal of the second inverter is connected to the input terminal of the eighth channel switch. The output terminals of the seventh channel switch and the eighth channel switch are connected to the same input terminal of the control module. The control terminal of the seventh channel switch is connected to a first control signal, and the control terminal of the eighth channel switch is connected to a second control signal. The first control signal is the inverted signal of the second control signal.

[0016] Based on the same inventive concept, the present invention also provides a chip that includes the duty cycle correction circuit described in the present invention.

[0017] Optionally, the chip further includes a phase-locked loop circuit coupled to the duty cycle correction circuit; wherein the phase-locked loop circuit is disposed at the front end of the duty cycle correction circuit or at the rear end of the duty cycle correction circuit.

[0018] Optionally, the chip is a memory chip, and / or the phase-locked loop circuit is a PLL circuit or a DLL circuit.

[0019] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0020] 1. In two adjacent comparison cycles, the voltages at the first and second input terminals of the comparator are swapped (or flipped), or the clock signals at the input terminals of the first charge pump module and the second charge pump are swapped (or flipped). This makes the input offset of the two input terminals of the comparator have the same effect on the high and low levels of the clock, eliminating the inherent error of duty cycle adjustment and finally obtaining a clock signal with a more balanced duty cycle.

[0021] 2. By adding a negative feedback module between the comparator output and the control module, the feedback of the duty cycle correction circuit loop can be adjusted to always be negative feedback, thereby enhancing the stability of the duty cycle correction circuit, improving the nonlinear distortion of the duty cycle correction circuit, and suppressing the noise and interference inside the duty cycle correction circuit.

[0022] 3. When the duty cycle correction circuit is applied to chips such as DDR memory, it can improve the problem of seeing uneven eye diagrams at the data transmission end. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the circuit architecture design of an existing duty cycle correction circuit.

[0024] Figure 2 yes Figure 1The timing diagram of the duty cycle correction circuit is shown.

[0025] Figure 3 This is a schematic diagram of the specific circuit structure of the duty cycle correction circuit according to the first embodiment of the present invention.

[0026] Figure 4 yes Figure 3 A schematic diagram illustrating the specific circuit structure of the duty cycle correction module.

[0027] Figure 5 yes Figure 3 The timing diagram of the duty cycle correction circuit is shown.

[0028] Figure 6 This is a schematic diagram illustrating a specific circuit connection example of the duty cycle correction circuit according to the second embodiment of the present invention.

[0029] Figure 7 This is a schematic diagram illustrating a specific circuit connection example of the duty cycle correction circuit according to the third embodiment of the present invention.

[0030] Figure 8 and Figure 9 These are schematic diagrams illustrating two example chip architectures according to the fourth embodiment of the present invention. Detailed Implementation

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. Although the terms first, second, third, etc., may be used to describe various elements, components, and / or portions, these elements, components, and / or portions should not be limited by these terms. These terms are used merely to distinguish one element, component, or portion from another element, component, or portion. Therefore, without departing from the teachings of the invention, the first element, component, or portion discussed below may be referred to as the second element, component, or portion. When used herein, the singular forms of "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0032] Figure 1 The diagram shows an existing duty cycle correction circuit for adjusting the clock duty cycle. It includes a charge pump module, a comparator COMP, a control module, and a duty cycle correction module. The charge pump module converts the duty cycles of the clock signals CKA and CKB output by the duty cycle correction module into two analog voltages. The comparator COMP compares the analog voltages output by the charge pump module. The control module generates a control signal for the duty cycle correction module based on the comparison result of the comparator COMP. The duty cycle correction module receives the corresponding clock signal CLK and generates clock signals CKA and CKB (i.e., the duty cycle-adjusted clock signals) with varying duty cycles relative to the clock signal CLK, based on the control signal output by the control module.

[0033] The operating timing logic of the duty cycle correction circuit is as follows: Figure 2As shown in the diagram, the signal CMPE is the enable signal for comparator COMP, and comparator COMP is not working when CMPE is low. The clock signal CLK is the initial clock signal. This duty cycle correction circuit mainly consists of a charging / discharging stage, a comparison stage, and a duty cycle adjustment stage. In the charging / discharging stage, two clock signals, CKA and CKB, are sent to the charge pump module, and the high-level widths of CKA and CKB represent the low-level and high-level widths of CLK, respectively. The high levels of CKA and CKB represent the charging time of the nodes in the charge pump module used to output the corresponding analog voltages, while the low levels of CKA and CKB control the discharging time of those nodes. In the comparison stage and the duty cycle adjustment stage, the two clock signals CKA and CKB are not sent to the charge pump module. In the duty cycle adjustment stage, the charge pump is disconnected from the comparator, and the corresponding capacitor in the charge pump is discharged to 0. Finally, the two analog voltages output by the charge pump module can represent the low-level and high-level widths of CLK, respectively. After several charge-discharge cycles, the comparator COMP is enabled, comparing the magnitudes of the two analog voltages output by the charge pump module. The comparison result is output to the control module to generate a control signal for the duty cycle correction module, which adjusts the clock duty cycle.

[0034] The disadvantages of the duty cycle correction circuit described above are: the input offset voltage of the comparator COMP will cause the duty cycle correction circuit to have a fixed adjustment error.

[0035] Furthermore, when the aforementioned duty cycle correction circuit is applied to DDR memory chips, the clock signal ultimately output by the duty cycle correction circuit is the external clock signal of the DDR memory chip. When performing read and write operations on the DDR memory chip, data must be sent on both the rising and falling edges of this clock signal. If the duty cycle of this clock signal is lost, that is, if the duty cycle of the clock signal ultimately output by the duty cycle correction circuit is not 50%, then the width of the data sent on the rising and falling edges of this clock signal will be large and small, respectively. What is seen at the data sending end is an eye diagram with different sizes of eyes, and even the problem of incomplete data transmission may occur.

[0036] Based on this, the present invention provides a duty cycle correction circuit and chip that can swap (or flip) the voltages at the first and second input terminals of the comparator in two adjacent comparison cycles, or swap (or flip) the clock signals at the input terminals of the first charge pump module and the second charge pump. This makes the input misalignment of the two input terminals of the comparator have the same effect on the high and low levels of the clock, eliminating the inherent error of duty cycle adjustment and ultimately obtaining a clock signal with a more balanced duty cycle. It can also avoid the problem of seeing an uneven eye diagram at the data transmission end when the memory chip using this duty cycle correction circuit sees an uneven eye diagram.

[0037] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] First Embodiment

[0039] Please refer to Figure 3 This embodiment provides a duty cycle correction circuit, which includes a first charge pump module 10A, a second charge pump module 10B, a comparator (COMP) 11, a control module 12, a duty cycle correction module 13, and a frequency divider module 14.

[0040] The input terminal (unlabeled) of the frequency divider module 14 is coupled to the output terminal (unlabeled) of the duty cycle correction module 13. The frequency divider module 14 is used to generate a first clock signal CKA and a second clock signal CKB based on the clock signal CLKi (where i = 0 to m, and m is an integer greater than or equal to 0) output by the duty cycle correction module 13. The first clock signal CKA and the corresponding clock signal CLKi have the same duty cycle. The second clock signal CKB is the inverted signal of the first clock signal CKA. The sum of the duty cycle of the first clock signal CKA and the duty cycle of the second clock signal CKB is 1.

[0041] The first charge pump module 10A provides a first voltage VA converted from the duty cycle of the first clock signal CKA at its output terminal (unlabeled); the second charge pump module 10B provides a second voltage VB converted from the duty cycle of the second clock signal CKB at its output terminal (unlabeled).

[0042] The output terminal (unlabeled) of comparator 11 is coupled to the input terminal (unlabeled) of control module 12. Comparator 11 is used to compare the first voltage VA and the second voltage VB under the control of the comparison enable signal CMPE.

[0043] In this embodiment, two adjacent comparison periods are defined as the first comparison period and the second comparison period. During the first comparison period, the first input terminal "+" of comparator 11 is coupled to the output terminal of the first charge pump module 10A, and the second input terminal "-" of comparator 11 is coupled to the output terminal of the second charge pump module 10B. During the second comparison period, the first input terminal "+" of comparator 11 is coupled to the output terminal of the second charge pump module 10B, and the second input terminal of comparator 11 is coupled to the output terminal of the first charge pump module 10A. During both the first and second comparison periods, the input terminal of the first charge pump module 10A receives the first clock signal CKA, and the input terminal of the second charge pump module 10B receives the second clock signal CKB. Therefore, within any two adjacent comparison cycles, the first voltage VA and the second voltage VB are alternately input to the first input terminal "+" and the second input terminal "-" of comparator 11, thereby distributing the input offset voltage of comparator 11 evenly to the high-level and low-level phases of the first clock signal CKA and the second clock signal CKB. This eliminates the influence of the input offset voltage of comparator 11 on the clock duty cycle adjustment, thereby eliminating the inherent error of duty cycle adjustment. Ultimately, this allows the duty cycle correction circuit to output a clock signal with a more balanced duty cycle, improving the adjustment accuracy of the clock duty cycle by the duty cycle correction circuit.

[0044] The output of control module 12 is coupled to one input of duty cycle correction module 13, and control module 12 generates a corresponding adjustment control signal control based on the comparison result of comparator 11 and provides it to duty cycle correction module 13. Duty cycle correction module 13 adjusts the duty cycle of its output clock signal CLKi according to the adjustment control signal control output by control module 12.

[0045] As an example, please continue to refer to Figure 3 The first charge pump module 10A includes a first current source I1, a first MOSFET P1, a second MOSFET P2, a second current source I2, and a first capacitor C1. The first current source I1, the first MOSFET P1, the second MOSFET N1, and the second current source I2 are connected in series, and the gate terminals of the first MOSFET P1 and the second MOSFET P2 are interconnected to form the input terminal of the first charge pump module 10A, which is coupled to a first clock signal CKA. The first MOSFET P1 is positioned between the first current source I1 and the output terminal (not shown) of the first charge pump module 10A. The second MOSFET N1 is positioned between the second current source I2 and the output terminal of the first charge pump module 10A. One end of the first capacitor C1 is connected to the output terminal of the first charge pump module 10A, and the other end of the first capacitor C1 is grounded. In other words, the drains of the first MOSFET P1 and the second MOSFET N1, along with one end of the first capacitor C1, are interconnected to form the output terminal of the first charge pump module 10A.

[0046] The second charge pump module 10B includes a third current source I3, a third MOSFET P2, a fourth MOSFET N2, a fourth current source I4, and a second capacitor C2. The third current source I3, third MOSFET P2, fourth MOSFET N2, and fourth current source I4 are connected in series, and the gate terminals of the third MOSFET P2 and the fourth MOSFET N2 are interconnected, forming the input terminal of the second charge pump module 10B and coupled to the second clock signal CKB. The third MOSFET P2 is positioned between the third current source I1 and the output terminal of the second charge pump module 10B, and the fourth MOSFET N2 is positioned between the fourth current source I4 and the output terminal of the second charge pump module 10B. One end of the second capacitor C2 is connected to the output terminal of the second charge pump module 10B, and the other end of the second capacitor C2 is grounded. In other words, the drain terminals of the third MOSFET P2 and the fourth MOSFET N2, along with one end of the second capacitor C2, are interconnected, forming the output terminal of the second charge pump module 10B.

[0047] Optionally, the third MOSFET P2 and the first MOSFET P1 are both PMOS transistors, and the fourth MOSFET N2 and the second MOSFET N1 are both NMOS transistors. In other embodiments of the present invention, the third MOSFET P2 and the first MOSFET P1 can also be replaced with NMOS transistors or transistors, and the fourth MOSFET N2 and the second MOSFET N1 can also be replaced with PMOS transistors or transistors. In this case, the terminal connections of the first MOSFET P1, the second MOSFET N1, the third MOSFET P2, and the fourth MOSFET N2 can be adjusted adaptively.

[0048] Optionally, the duty cycle correction circuit in this embodiment further includes first to sixth channel switches Q1 to Q6. The first channel switch Q1 is coupled between the output terminal of the first charge pump module 10A and the first input terminal of the comparator 11; the second channel switch Q1 is coupled between the output terminal of the second charge pump module 10B and the second input terminal of the comparator 11; the third channel switch Q3 is coupled between the output terminal of the second charge pump module 10B and the first input terminal of the comparator 11; the fourth channel switch Q4 is coupled between the output terminal of the first charge pump module 10A and the second input terminal of the comparator 11; and the fifth channel switch Q5 is coupled between... At the output of the frequency divider module 14 and the input of the first charge pump module 10A, the sixth channel switch Q6 is coupled to the output of the frequency divider module 14 and the input of the second charge pump module 10B. The control terminals of the first channel switch Q1 and the second channel switch Q2 are connected to the first control signal CKS. The control terminals of the third channel switch Q3 and the fourth channel switch Q4 are connected to the second control signal CKS_B. The first control signal CKS is the inverted signal of the second control signal CKS_B. The control terminals of the fifth channel switch Q5 and the sixth channel switch Q6 are both connected to the third control signal CKC. Specifically, when the fifth channel switch Q5 is turned on, the first clock signal CKA is sent from the frequency divider module 14 to the first charge pump module 10A; when the sixth channel switch Q6 is turned on, the second clock signal CKB is sent from the frequency divider module 14 to the second charge pump module 10B; when the first channel switch Q1 or the fourth channel switch Q4 is turned on, the first voltage VA is sent to the first input terminal of the comparator 11; when the second channel switch Q2 or the third channel switch Q3 is turned on, the second voltage VB is sent to the second input terminal of the comparator 11. Thus, the first voltage VA and the second voltage VB can be switched and input to the first and second input terminals of the comparator 11 in two adjacent comparison cycles using the first control signal CKS and the second control signal CKS_B.

[0049] As an example, please refer to Figure 4The duty cycle correction module 13 in this embodiment includes a first inverter U1 and (n+1) duty cycle correction units 130 to 13n, where n is greater than or equal to 1 and is an integer. The input terminal of the first inverter U1 is interconnected with the input terminals of each duty cycle correction unit 130 to 13n to form the input terminal of the duty cycle correction module 13 for receiving the initial clock signal CLK. The output terminal of the first inverter U1 is interconnected with the output terminals of all the duty cycle correction units 130 to 13n to form the output terminal of the duty cycle correction module 13. Each duty cycle correction unit includes two PMOS transistors and two NMOS transistors. The source of the first PMOS transistor is connected to the power supply voltage VDD, and its drain is connected to the source of the second PMOS transistor. The gate of the first PMOS transistor is connected to the adjustment control signal EA. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and its gate is connected to the gate of the first NMOS transistor and connected to the initial clock signal CLK. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, and its gate is connected to the adjustment control signal EB. Specifically, for example, the duty cycle correction unit 130 includes PMOS transistors PM01 to PM02 and NMOS transistors NM01 to NM02. The source of PMOS transistor PM01 is connected to the power supply voltage VDD, and its drain is connected to the source of PMOS transistor PM02. The gate of PMOS transistor PM01 is connected to the adjustment control signal EA. <0> The drain of PMOS transistor PM02 is connected to the drain of NMOS transistor NM01. The gate of PMOS transistor PM02 is connected to the gate of NMOS transistor NM01 and connected to the initial clock signal CLK. The source of NMOS transistor NM01 is connected to the drain of NMOS transistor NM02. The source of NMOS transistor NM02 is grounded. The gate of NMOS transistor NM02 is connected to the adjustment control signal EB. <0> Similarly, the duty cycle correction unit 13n includes PMOS transistors PMn1 to PMn2 and NMOS transistors NMn1 to NMn2. The source terminal of PMOS transistor PMn1 is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of PMOS transistor PMn2. The gate terminal of PMOS transistor PMn1 is connected to the adjustment control signal EA. <n>The drain of PMOS transistor PMn2 is connected to the drain of NMOS transistor NMn1. The gate of PMOS transistor PMn2 is connected to the gate of NMOS transistor NMn1 and connected to the initial clock signal CLK. The source of NMOS transistor NMn1 is connected to the drain of NMOS transistor NMn2. The source of NMOS transistor NMn2 is grounded. The gate of NMOS transistor NMn2 is connected to the adjustment control signal EB. <n>Among them, EA <0> ~EA <n>and EB <0> ~EB <n>That is, the combination is the adjustment control signal generated by the control module 12 based on the comparison result of the comparator 11.

[0050] It should be understood that, in this embodiment, the comparison enable signal CMPE, the first control signal CKS, the second control signal CKS_B, and the third control signal CKC are used to control the timing of the entire duty cycle correction circuit in this embodiment. Their combination can be used to set the initial voltage and operating timing for the duty cycle correction circuit in this embodiment, wherein the operating timing is as follows: Figure 5 As shown. Therefore, the comparison enable signal CMPE, the control signal CKC, and the control signal CKS can all be provided by the control module 12, or the control logic of the comparison enable signal CMPE, the first control signal CKS, the second control signal CKS_B, and the third control signal CKC can all be integrated into the frequency divider module 14 (i.e., the comparison enable signal CMPE, the first control signal CKS, the second control signal CKS_B, and the third control signal CKC can all be provided by the frequency divider module 14), or the comparison enable signal CMPE, the first control signal CKS, the second control signal CKS_B, and the third control signal CKC can all be provided by a circuit outside the duty cycle correction circuit of this embodiment, or a portion of the comparison enable signal CMPE, the first control signal CKS, the second control signal CKS_B, and the third control signal CKC can be provided by one of the control module 12, the frequency divider module 14, and the external circuit, and another portion of the signals can be provided by the other of the control module 12, the frequency divider module 14, and the external circuit.

[0051] Please combine Figure 3 and Figure 5 In this embodiment, during the charging and discharging phase, the control signal CKC controls the fifth channel switch Q5 and the sixth channel switch Q6 to be turned on. The first clock signal CKA and the second clock signal CKB are respectively sent to the input terminals of the first charge pump module 10A and the second charge pump module 10B. As a result, a first voltage VA related to the first clock signal CKA is generated at the output terminal of the first charge pump module 10A, and a second voltage VB related to the second clock signal CKB is generated at the output terminal of the second charge pump module 10B. During the comparison phase and the duty cycle adjustment phase, the control signal CKC controls the fifth channel switch Q5 and the sixth channel switch Q6 to be turned off, so that the first clock signal CKA and the second clock signal CKB are not sent to the charge pump module 10. During the duty cycle adjustment phase, the control signal CKS controls the first to fourth channel switches Q1 to Q4 to be turned off or on.

[0052] The principle behind the duty cycle correction module 13 adjusting the clock duty cycle is as follows:

[0053] In the first comparison cycle, the initial clock signal CLK (which can be regarded as CLK0) is sent to the frequency divider module 14, and the generated first clock signal CKA and second clock signal CKB are denoted as CKA0 and CKB0. The first voltage VA generated based on CKA0 is input to the first input terminal of comparator 11, and the second voltage VB generated based on CKB0 is input to the second input terminal of comparator 11. After comparing VA and VB, comparator 11 determines whether the duty cycle of the initial clock signal CLK is greater than the target value (e.g., 50%) or less than the target value. If the duty cycle of the initial clock signal CLK is greater than the target value, the duty cycle correction module 13 reduces the duty cycle of the initial clock signal CLK; otherwise, it increases the duty cycle of the initial clock signal CLK, thereby obtaining the clock signal CLK1 with adjusted duty cycle.

[0054] In the second comparison cycle, the frequency divider module 14 generates first clock signals CKA and CKB based on clock signal CLK1, denoted as CKA1 and CKB1. The first voltage VA generated based on CKA1 is input to the second input terminal of comparator 11, and the second voltage VB generated based on CKB1 is input to the first input terminal of comparator 11. After comparing VA and VB, comparator 11 determines whether the duty cycle of clock signal CLK1 is greater than or less than the target value. If the duty cycle of clock signal CLK1 is greater than the target value, the duty cycle correction module 13 reduces the duty cycle of clock signal CLK1; otherwise, it increases the duty cycle of clock signal CLK1, thereby obtaining the clock signal CLK2 with adjusted duty cycle.

[0055] This process continues until comparator 11 compares VA and VB and determines that the duty cycle of the current clock signal CLKi (where i = 0 to m, and m is an integer greater than or equal to 0) is equal to the target value. At this point, the duty cycle-adjusted clock signal CLKi output by the duty cycle correction module 13 can be locked and used as the final clock signal output to the external circuit.

[0056] Compared with the prior art, the duty cycle correction circuit of this embodiment can swap (or flip) the voltages of the first and second input terminals of the comparator in two adjacent comparison cycles, or swap (or flip) the clock signals of the input terminals of the first charge pump module and the second charge pump. This makes the input misalignment of the two input terminals of the comparator have the same effect on the high and low levels of the clock, eliminates the inherent error of duty cycle adjustment, and finally obtains a clock signal with a more balanced duty cycle.

[0057] Second Embodiment

[0058] Please refer to Figure 6 This embodiment provides a duty cycle correction circuit, which differs from the first embodiment in that, in addition to the charge pump module 10, comparator 11, control module 12, duty cycle correction module 13, frequency divider module 14, and first to sixth channel switches Q1 to Q6, the duty cycle correction circuit of this embodiment also includes a negative feedback module 15.

[0059] The negative feedback module 15 includes a second inverter U2, a seventh channel switch Q7, and an eighth channel switch Q8. The input terminals of the second inverter U2 and the seventh channel switch Q7 are both connected to the output terminal of the comparator 11. The output terminal of the second inverter U2 is connected to the input terminal of the eighth channel switch Q8. The output terminals of the seventh channel switch Q7 and the eighth channel switch Q8 are connected to the same input terminal of the control module 12. The control terminal of the seventh channel switch Q7 is connected to the first control signal CKS, and the control terminal of the eighth channel switch Q8 is connected to the second control signal CKS_B. The first control signal CKS is the inverted signal of the second control signal CKS_B.

[0060] In this embodiment, under the control of the first control signal CKS and the second control signal CKS_B, the negative feedback module 15 adjusts the loop feedback of the duty cycle correction circuit to always be negative feedback, thereby enhancing the stability of the duty cycle correction circuit, improving the nonlinear distortion of the duty cycle correction circuit, and suppressing the noise and interference inside the duty cycle correction circuit, ultimately obtaining a clock signal with a more balanced duty cycle and improving the adjustment accuracy of the clock duty cycle of the duty cycle correction circuit.

[0061] Third Embodiment

[0062] Please refer to Figure 7 This embodiment provides a duty cycle correction circuit, which differs from the second embodiment in that the third channel switch Q3 in this embodiment is no longer located between the output terminal of the first charge pump module 10A and the comparator 11, and the fourth channel switch Q4 is no longer located between the output terminal of the second charge pump module 10B and the comparator 11. Instead, the input terminal of the third channel switch Q3 is connected to the input terminal of the sixth channel switch Q6, the output terminal of the third channel switch Q3 is connected to the output terminal of the fifth channel switch Q5, the input terminal of the fourth channel switch Q4 is connected to the input terminal of the fifth channel switch Q5, and the output terminal of the fourth channel switch Q4 is connected to the output terminal of the sixth channel switch Q6. Furthermore, the control terminals of the third channel switch Q3 and the fourth channel switch Q4 are connected to a fourth control signal CKC_B, which is the inverted signal of the third control signal CKC connected to the control terminals of the fifth channel switch Q5 and the sixth channel switch Q6.

[0063] In this embodiment, the third to sixth channel switches Q3 to Q6 cooperate with each other under the control of the third control signal CKC and the fourth control signal CKC_B to control the first clock signal CKA and the second clock signal CKB to be flipped and connected to the input terminals of the first charge pump module 10A and the second charge pump module 10B in every two adjacent comparison cycles. Furthermore, the first channel switch Q1 and the second channel switch Q2 are turned on by the first control signal CKS. That is, in two adjacent comparison cycles, in the first comparison cycle, the input terminal of the first charge pump module 10A receives the first clock signal CKA, and the input terminal of the second charge pump module 10B receives the second clock signal CKN. In the second comparison cycle, the input terminal of the first charge pump module 10A receives the second clock signal CKB, and the input terminal of the second charge pump module 10B receives the first clock signal CKA. In the first comparison cycle and the second comparison cycle, the first input terminal of the comparator 11 is coupled to the output terminal of the first charge pump module 10A, and the second input terminal of the comparator 11 is coupled to the output terminal of the second charge pump module 10B. Therefore, the voltages received by the first and second input terminals of comparator 11 will flip within two adjacent comparison cycles, thereby making the input offset voltage of comparator 11 evenly distributed to the high-level and low-level phases of the first clock signal CKA and the second clock signal CKB. This can also eliminate the influence of the input offset voltage of comparator 11 on the clock duty cycle adjustment, that is, it can also eliminate the inherent error of duty cycle adjustment, and finally obtain a clock signal with a more balanced duty cycle.

[0064] Fourth embodiment

[0065] Please refer to Figure 8 and Figure 9 This embodiment also provides a chip, which includes the duty cycle correction circuit 1 described in any of the above embodiments of the present invention and a phase-locked loop circuit 2 coupled to the duty cycle correction circuit 1. The phase-locked loop circuit 2 can be disposed at the front end of the duty cycle correction circuit 1 (e.g., Figure 9 (as shown) or set at the rear end of the duty cycle correction circuit 1 (such as... Figure 8 (As shown).

[0066] Optionally, the chip in this embodiment can be a memory chip (e.g., a DDR memory chip), and the phase-locked loop circuit 2 can be a PLL circuit or a DLL circuit. Please refer to... Figure 8 When the phase-locked loop circuit 2 is positioned at the front end of the duty cycle correction circuit 1, it can be used to synchronize the clock signal of the internal circuit of the memory chip with the clock signal of the external circuit, thereby solving the clock skew problem. The duty cycle correction circuit 1 adjusts the duty cycle of the clock output by the phase-locked loop circuit 2 to the target value. Please refer to... Figure 9 When the phase-locked loop circuit 2 is located at the downstream end of the duty cycle correction circuit 1, it can synchronize the clock output by the duty cycle correction circuit 1 with the clock of the internal circuit of the memory chip, thereby solving the clock skew problem. Because the memory chip uses the duty cycle correction circuit 1 of this embodiment, its duty cycle can reach 50%. Therefore, when performing read and write operations on the memory chip based on a clock signal with a 50% duty cycle, the problems of uneven eye diagrams and incomplete data transmission at the data transmission end can be avoided.

[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.< / n> < / n> < / n> < / n>

Claims

1. A duty cycle correction circuit, characterized in that, It includes a first charge pump module, a second charge pump module, a comparator, a control module, a duty cycle correction module, and a frequency divider module; and in each comparison cycle, the frequency divider module generates a first clock signal and a second clock signal based on the clock signal output by the duty cycle correction module; the input terminal of the control module is connected to the output terminal of the comparator, and the control module is used to generate a corresponding control signal according to the comparison result of the comparator and provide it to the duty cycle correction module. The duty cycle correction module outputs a clock signal with a changing duty cycle based on the control signal output by the control module. In the first comparison period, the first input terminal of the comparator is coupled to the output terminal of the first charge pump module, and the second input terminal of the comparator is coupled to the output terminal of the second charge pump module. In the second comparison period adjacent to the first comparison period, the first input terminal of the comparator is coupled to the output terminal of the second charge pump module, and the second input terminal of the comparator is coupled to the output terminal of the first charge pump module. In both the first and second comparison periods, the input terminal of the first charge pump module receives the first clock signal, and the input terminal of the second charge pump module receives the second clock signal. Alternatively, in the first comparison period, the input terminal of the first charge pump module receives the first clock signal, and the input terminal of the second charge pump module receives the second clock signal. In the second comparison period adjacent to the first comparison period, the input terminal of the first charge pump module receives the second clock signal, and the input terminal of the second charge pump module receives the first clock signal. In both the first and second comparison periods, the first input terminal of the comparator is coupled to the output terminal of the first charge pump module, and the second input terminal of the comparator is coupled to the output terminal of the second charge pump module.

2. The duty cycle correction circuit as described in claim 1, characterized in that, It also includes first to fourth channel switches. The input terminals of the first channel switch and the fourth channel switch are both connected to the output terminal of the first charge pump module. The input terminals of the second channel switch and the third channel switch are both connected to the output terminal of the second charge pump module. The output terminals of the first channel switch and the third channel switch are both connected to the first input terminal of the comparator. The output terminals of the second channel switch and the fourth channel switch are both connected to the second input terminal of the comparator. The control terminals of the first channel switch and the second channel switch are connected to a first control signal. The control terminals of the third channel switch and the fourth channel switch are connected to a second control signal, and the second control signal is the inverted signal of the first control signal.

3. The duty cycle correction circuit as described in claim 2, characterized in that, It also includes a fifth channel switch and a sixth channel switch. The fifth channel switch is coupled between the input terminals of the frequency divider module and the first charge pump module, and the sixth channel switch is coupled between the input terminals of the frequency divider module and the second charge pump module. The control terminals of the fifth channel switch and the sixth channel switch are both connected to a third control signal.

4. The duty cycle correction circuit as described in claim 1, characterized in that, It also includes third to sixth channel switches. The fifth channel switch is coupled between the input terminals of the frequency divider module and the first charge pump module. The sixth channel switch is coupled between the input terminals of the frequency divider module and the second charge pump module. The input terminal of the third channel switch is connected to the input terminal of the sixth channel switch. The output terminal of the third channel switch is connected to the output terminal of the fifth channel switch. The input terminal of the fourth channel switch is connected to the input terminal of the fifth channel switch. The output terminal of the fourth channel switch is connected to the output terminal of the sixth channel switch. The control terminals of the fifth and sixth channel switches are both connected to a third control signal. The control terminals of the third and fourth channel switches are both connected to a fourth control signal. The fourth control signal is the inverted signal of the third control signal.

5. The duty cycle correction circuit as described in claim 4, characterized in that, It also includes a first channel switch and a second channel switch. The first channel switch is coupled between the output terminal of the first charge pump module and the first input terminal of the comparator, and the second channel switch is coupled between the output terminal of the second charge pump module and the second input terminal of the comparator. The control terminals of the first channel switch and the second channel switch are both connected to a first control signal.

6. The duty cycle correction circuit as described in any one of claims 1-5, characterized in that, The first charge pump module includes a first current source, a first MOSFET, a second MOSFET, a second current source, and a first capacitor. The first current source, the first MOSFET, the second MOSFET, and the second current source are connected in series. One end of the first capacitor is connected to the series node of the first MOSFET and the second MOSFET to form the output terminal of the first charge pump module. The gate terminal of the first MOSFET and the gate terminal of the second MOSFET are connected to form the input terminal of the first charge pump module. And / or, the second charge pump module includes a third current source, a third MOSFET, a fourth MOSFET, a fourth current source, and a second capacitor, wherein the third current source, the third MOSFET, the fourth MOSFET, and the fourth current source are connected in series, one end of the second capacitor is connected to the series node of the third MOSFET and the fourth MOSFET to form the output terminal of the second charge pump module, and the gate terminal of the third MOSFET and the gate terminal of the fourth MOSFET are connected to form the input terminal of the second charge pump module.

7. The duty cycle correction circuit as described in claim 6, characterized in that, The duty cycle correction module includes a first inverter and multiple duty cycle correction units. The input terminal of the first inverter is interconnected with the input terminals of all the duty cycle correction units to form the input terminal of the duty cycle correction module. The output terminal of the first inverter is interconnected with the output terminals of all the duty cycle correction units to form the output terminal of the duty cycle correction module.

8. The duty cycle correction circuit as described in claim 6, characterized in that, It also includes a negative feedback module, which comprises a second inverter, a seventh channel switch, and an eighth channel switch. The input terminals of the second inverter and the seventh channel switch are both connected to the output terminal of the comparator. The output terminal of the second inverter is connected to the input terminal of the eighth channel switch. The output terminals of the seventh channel switch and the eighth channel switch are connected to the same input terminal of the control module. The control terminal of the seventh channel switch is connected to a first control signal, and the control terminal of the eighth channel switch is connected to a second control signal. The first control signal is the inverted signal of the second control signal.

9. A chip, characterized in that, Includes the duty cycle correction circuit according to any one of claims 1-8.

10. The chip as described in claim 9, characterized in that, It also includes a phase-locked loop circuit coupled to the duty cycle correction circuit; wherein the phase-locked loop circuit is located at the front end of the duty cycle correction circuit or at the rear end of the duty cycle correction circuit.

11. The chip as described in claim 10, characterized in that, The chip is a memory chip, and / or the phase-locked loop circuit is a PLL circuit or a DLL circuit.

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