Low-latency high-speed output driver circuit

Abstract

The application discloses a low-delay high-speed output driving circuit, which comprises k high-side inverter chains with gradually enlarged sizes, k low-side inverter chains with gradually enlarged sizes, a high-side driving PMOS tube, a low-side driving NMOS tube, a level shift circuit, a high-side floating power supply generating circuit and a low-side power supply generating circuit. The high-speed output driving circuit adopts a high-speed level shift circuit, a high-side floating power supply generating circuit and a low-side step-down power supply generating circuit, and realizes speed improvement by reducing the amplitude of high and low level signals in the internal circuit. For different power supply voltages, the swing of the gate voltage control signal of the internal large-size output driving LDMOS tube is a fixed value, and is not affected by the change of the output driving power supply voltage.

Description

Technical Field

[0001] This invention relates to a low-delay, high-speed output drive circuit for high-voltage integrated circuits, belonging to the field of integrated circuit technology. Background Technology

[0002] The input / output (IO) interface circuit of an integrated circuit (IC) generally consists of a driver circuit that implements the output function and a receiving circuit that implements the input function. Since the capacitance of the external load capacitor of the IO is unknown and can vary greatly, the switching time of the output signal of the IO driver circuit may also change with the load capacitance. Therefore, the output driver circuit usually needs to provide sufficient drive current. High-voltage integrated circuits typically require integrated output driver circuits to convert the signals from the information electronic circuits into signals applied between the control terminal and the common terminal of the power electronic device, allowing it to be turned on or off, according to the control objectives. For semi-controlled devices, only an on-control signal is needed; for fully controlled devices, both on-control and off-control signals are required to ensure that the device reliably turns on or off as required.

[0003] The performance of the output drive circuit has a significant impact on the overall performance of the integrated circuit. A good output drive circuit can improve system reliability, increase conversion efficiency (switching and conduction losses of switching devices), reduce stress on switching devices (during the on / off process), and reduce EMI / EMC.

[0004] like Figure 1 As shown, a typical existing output drive circuit consists of multiple progressively larger P-terminal inverter chains Inv1 to Inv3 and multiple progressively larger N-terminal inverter chains Inv4 to Inv6, a P-terminal driving PMOS transistor M1, and an N-terminal driving NMOS transistor M2. The branches containing transistors M1 and M2 determine the output current of the drive circuit, and also the output impedance of the circuit. In typical MOSFET / IGBT device drives in power electronic systems, the voltage range of the power supply VCC is usually 10–30V. Figure 1 The specific implementation circuit is as follows: Figure 2 As shown, the source-drain breakdown voltage Vds of all MOS transistors, M1, and M2 inside all inverters Inv1 to Inv6 must be greater than VCC = 30V. The input pulse signal Vin simultaneously enters the P-terminal inverters Inv1 to Inv3 and the N-terminal inverters Inv4 to Inv6, respectively obtaining the gate control signal Vgp driving the PMOS transistor M1 at the P-terminal and the gate control signal Vgn driving the NMOS transistor M2 at the N-terminal, ultimately yielding the output gate voltage drive signal VO.

[0005] Among them, the duty cycles and timings of the input pulse signals Vin, Vgp, and Vgn are exactly the same, and the low level is the ground voltage VSS, while the high level is the power supply VCC. Therefore, the absolute swing of its high and low levels is VCC. Figure 2 When the circuit described above is implemented using conventional BCD technology, the source-drain breakdown voltage Vds and gate-source breakdown voltage Vgs of all devices must be greater than VCC. The aforementioned MOSFETs, M1, and M2 all require high-voltage-resistant LDMOS or HVMOS devices. However, NMOS or PMOS transistors with a gate-source breakdown voltage Vgs greater than VCC = 30V are thick-gate oxide devices, resulting in significantly larger gate lengths and parasitic resistances compared to ordinary thin-gate oxide devices. This not only affects the overall drive speed but also generates greater dynamic power consumption. Summary of the Invention

[0006] To address the speed and power consumption issues associated with using thick gate oxide devices, this invention proposes a low-delay, high-speed output drive circuit using thin gate oxide devices, thereby improving drive efficiency.

[0007] The low-delay, high-speed output drive circuit provided by this invention includes k progressively larger high-side inverter chains, k progressively larger low-side inverter chains, a high-side driving PMOS transistor M31, and a low-side driving NMOS transistor M32, where k is a positive integer. This invention also includes a low-side power supply generation circuit, a high-side floating power supply generation circuit, and a level shifting circuit. An input pulse signal Vin is connected to the input terminal of the N-terminal inverter chain, and simultaneously, the input pulse signal Vin is connected to the input terminal of the P-terminal inverter chain via the level shifting circuit. The level shifting circuit outputs a P-terminal input signal Vinp, which enters the P-terminal inverter chain. The P-terminal inverter chain outputs a control signal Vgh, which is connected to the gate of the P-terminal driving PMOS transistor M31. The N-terminal inverter chain outputs a control signal Vgl, which is connected to the gate of the N-terminal driving NMOS transistor M32. The control signals Vgh and Vgl are used to control the on and off states of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32, respectively.

[0008] The source of the P-terminal driving PMOS transistor M31 is connected to the power supply voltage VCC. The drain of the P-terminal driving PMOS transistor M31 is connected to the drain of the N-terminal driving NMOS transistor M32 and outputs a drive signal VO. The source of the N-terminal driving NMOS transistor M32 is grounded to the voltage VSS. The power supply voltage of all inverters in the P-terminal inverter chain is connected to the power supply voltage VCC, and the ground potential of all inverters in the P-terminal inverter chain is connected to the floating voltage Vsh. The power supply voltage of all inverters in the N-terminal inverter chain is connected to the low-voltage power supply VCCL, and the ground potential of all inverters in the N-terminal inverter chain is connected to the ground voltage VSS.

[0009] The floating voltage Vsh is obtained by stepping down the power supply voltage VCC through the high-side floating power supply generation circuit at the P terminal, and its voltage value Vsh = VCC - VCCL; the low-voltage power supply VCCL is generated by the low-side power supply generation circuit at the N terminal, and the VCCL voltage is less than the power supply voltage VCC; the power supply terminal of the level shifting circuit uses the power supply voltage VCC, and the ground terminal uses the floating voltage Vsh and the ground voltage VSS respectively. The level shifting circuit converts the input pulse signal Vin, which has a low level of VSS and a high level of VCCL, into the P terminal input signal Vinp, which has a low level of Vsh and a high level of VCC.

[0010] The source-drain and gate-source breakdown voltages of all PMOS and NMOS transistors within the P-terminal inverter chain and N-terminal inverter chain must be VCCL; the gate-source breakdown voltage of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32 must be VCCL, and the source-drain breakdown voltage of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32 must be VCC.

[0011] Specifically, the low-side power supply generation circuit includes: NMOS transistors M101, M102, M103, M104, M105, M106, M107, M108, M110, M109, and M111; resistors R11, R12, R13, and R14; and capacitor C11. The drain of NMOS transistor M101 is connected to the NMOS transistor M110. The gates of M101 and M102 of the NMOS transistor are connected to the reference voltage Vref via resistor R11; the gate of LDNMOS transistor M107 is also connected to the reference voltage Vref, and the source of LDNMOS transistor M107 is connected to the drain of NMOS transistor M102; the gate of PMOS transistor M103 is connected to the drain of PMOS transistor M103, the gate of PMOS transistor M104, and the source of LDPMOS transistor M105; the gate of LDPMOS transistor M105 is connected to the drain of LDPMOS transistor M105, the gate of LDPMOS transistor M106, and L... The drain of NMOS transistor M107, the drain of PMOS transistor M104, and the source of LDPMOS transistor M106 are connected. The drain of LDPMOS transistor M106 is connected to the drain of LDNMOS transistor M108, the gate of LDNMOS transistor M110, the gate of LDNMOS transistor M108, and one end of capacitor C11. The source of LDNMOS transistor M108 is connected to the other end of capacitor C11 and the upper end of resistor R12. The lower end of resistor R12 is connected to the upper end of resistor R13 and the gate of NMOS transistor M111. The lower end of resistor R13 is connected to the gate of NMOS transistor M107. The drain of transistor M109 is connected to the gate of NMOS transistor M109; the source of LDNMOS transistor M110 is connected to the drain of NMOS transistor M111 and the upper end of resistor R14, and serves as the output terminal of the low-voltage power supply VCCL; the sources of PMOS transistors M103 and M104, and the drain of LDNMOS transistor M110 are all connected to the power supply voltage VCC; the sources of NMOS transistors M101, M102, M109, and M111, and the lower end of resistor R14 are all connected to the ground voltage VSS.

[0012] Specifically, the high-side floating power supply generation circuit includes: LDPMOS transistors M201, M202, M203, M204, M205, M206, and M207; capacitors C21 and C22; resistors R21, R22, and R23; the source of LDPMOS transistor M201 is connected to the upper end of resistor R21, and the lower end of resistor R21 is connected to the upper end of resistor R22 and the gate of LDPMOS transistor M202; the lower end of resistor R22 is connected to the source of LDPMOS transistor M203 and the lower end of capacitor C21, and the lower end of capacitor C21 is connected to the upper end of capacitor C22; the gate of LDPMOS transistor M203 is connected to the drain of LDPMOS transistor M203, the gate of LDPMOS transistor M204, and the gate of LDPMOS transistor M207. 5. Drain and lower end of capacitor C22; gate of LDNMOS transistor M205 is connected to gate of LDNMOS transistor M205 and also connected to bias voltage Vb4; source of LDNMOS transistor M205 is connected to drain of NMOS transistor M207, and gate of NMOS transistor M207 is connected to reference voltage Vref; drain of LDPMOS transistor M202 is connected to source of LDPMOS transistor M204 and lower end of resistor R23, and serves as the output terminal of floating voltage Vsh; drain of LDPMOS transistor M204 is connected to drain of LDNMOS transistor M205; source of NMOS transistor M207 and source of LDNMOS transistor M205 are connected to ground voltage VSS; gate of LDPMOS transistor M201, drain of LDPMOS transistor M201, upper end of capacitor C21, source of LDPMOS transistor M202 and upper end of resistor R23 are all connected to power supply voltage VCC.

[0013] Specifically, the level shifting circuit includes: PMOS transistors M901, M902, M903, M904, M905, M906, LDPMOS transistors M907, M908, LDNMOS transistors M913, M914, NMOS transistors M909, M910, M911, and M912; resistor R91; and inverter inv91; the gate of PMOS transistor M901 is connected to the drain of PMOS transistor M902. The source of LDPMOS transistor M908 and the gate of PMOS transistor M903 are connected. The gate of PMOS transistor M902 is connected to the drain of PMOS transistor M901, the source of LDPMOS transistor M907, the lower end of resistor R91, and the gate of PMOS transistor M904. The input pulse signal Vin is connected to the input of inverter inv91 and the gate of LDNMOS transistor M914. The output of inverter inv91 is connected to the gate of LDNMOS transistor M913. The drains of LDPMOS transistors M907 and M913 are connected. The drain of LDPMOS transistor M908 and the gate of LDNMOS transistor M904 are connected. The drain of transistor M914 is connected to the drain of transistor M909 and the gate of transistor M910; the drain of transistor M904 is connected to the drain of transistor M910, the gate of transistor M909, the gate of transistor M905, and the gate of transistor M911; the drain of transistor M905 is connected to the drain of transistor M911, the gate of transistor M906, and the gate of transistor M912; the drain of transistor M906 and the drain of transistor M912 are connected and serve as the output terminal of signal Vinp; the source of transistor M913 is connected to the drain of transistor M914. The source of LDNMOS transistor M914 is simultaneously connected to ground voltage VSS; the gates of LDPMOS transistors M907 and M908, the sources of NMOS transistors M909, M910, M911, and M912 are simultaneously connected to floating voltage Vsh; the sources of PMOS transistors M901, M902, M903, M904, M905, and M906, as well as the upper end of resistor R91, are simultaneously connected to power supply voltage VCC.

[0014] The advantages of this invention are: the low-delay high-speed output drive circuit employs a high-speed level shift circuit, a high-side floating power supply generation circuit, and a low-side step-down power supply generation circuit, achieving speed improvement by reducing the amplitude of high and low level signals in the internal circuit. For different power supply voltages, the gate voltage control signal swing of the large-size output drive LDMOS transistor remains a fixed value, unaffected by changes in the output drive power supply voltage. This circuit can achieve high-speed output drive for different output drive voltages. Attached Figure Description

[0015] Figure 1 This is a structural diagram of the output drive circuit in the existing technology.

[0016] Figure 2 This is a schematic diagram of the specific implementation of the output drive circuit in the existing technology.

[0017] Figure 3 This is a circuit structure block diagram of the present invention.

[0018] Figure 4 This is a schematic diagram of the low-side power supply generation circuit of the present invention.

[0019] Figure 5 This is a schematic diagram of the high-side floating power supply generation circuit of the present invention.

[0020] Figure 6 This is a schematic diagram of the level shifting circuit of the present invention.

[0021] Figure 7 The above is a simulation waveform diagram of the low-delay high-speed output drive circuit of the present invention.

[0022] Figure 8 This is an example of the application of the present invention in a driver chip.

[0023] Figure 9 This is an example of the application of the present invention in an AC / DC power supply chip. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and examples.

[0025] like Figure 3As shown, the low-delay high-speed output drive circuit of this invention includes k (k is a positive integer) progressively larger high-side inverter chains invp1~invpk, k progressively larger low-side inverter chains invn1~invnk, a high-side driving PMOS transistor M31, a low-side driving NMOS transistor M32, a level shifting circuit 3, a high-side floating power supply generation circuit 2, and a low-side power supply generation circuit 1. The power supply voltage of all inverters within the P-side inverter chain is connected to the power supply voltage VCC, and the ground potential of all inverters is connected to the floating voltage Vsh. The power supply voltage of all inverters within the N-side inverter chain is connected to the low-voltage power supply VCCL, and the ground potential of all inverters is connected to the ground voltage VSS. The source of the N-side driving NMOS transistor M32 is grounded to the voltage VSS. The source of the P-side driving PMOS transistor M31 is connected to the power supply voltage VCC, and the drain of the P-side driving PMOS transistor M31 is connected to the drain of the N-side driving NMOS transistor M32 to output the drive signal VO.

[0026] The input pulse signal Vin enters level shift circuit 3 on one hand, and outputs the P-terminal input signal Vinp. The P-terminal input signal Vinp enters the P-terminal inverter chain invp1~invpk, obtaining the gate control signal Vgh for driving the PMOS transistor M31. On the other hand, the input pulse signal Vin directly enters the N-terminal inverter chain invn1~invnk, obtaining the gate control signal Vgl for driving the NMOS transistor M32. The control signals Vgh and Vgl are used to control the on and off states of the P-terminal driven PMOS transistor M31 and the N-terminal driven NMOS transistor M32, respectively.

[0027] The floating voltage Vsh is obtained by stepping down the power supply voltage VCC using the high-side floating power supply generation circuit 2 at the P terminal, and its voltage value Vsh = VCC - VCCL. The low-voltage power supply VCCL is a power supply with a lower voltage than the power supply voltage VCC, and is obtained by stepping down the voltage using the low-side power supply generation circuit 1 at the N terminal.

[0028] Figure 3In the circuit shown, the source-drain and gate-source breakdown voltages of all PMOS and NMOS transistors within the P-terminal and N-terminal inverter chains are required to be VCCL. The gate-source breakdown voltages of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32 are also required to be VCCL, while the source-drain breakdown voltages of these transistors remain VCC. For example, in a typical 180nm BCD process, all PMOS and NMOS transistors within the P-terminal and N-terminal inverter chains can be low-voltage MOSFETs with a breakdown voltage of 1.8V or 5V, i.e., VCCL is 1.8V or 5V. The P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32, however, require LDMOS or HVMOS devices with a Vgs breakdown voltage of 5V and a Vds breakdown voltage of 20V.

[0029] Figure 3 The presented circuit employs a high-speed level shifting circuit, a high-side floating and low-side step-down power supply generation circuit, which reduces the gate charging and discharging voltage amplitude of PMOS transistor M31 and NMOS transistor M32 from the original VCC to VCCL, effectively shortening the charging and discharging time of the equivalent gate capacitance of M31 and M32. Therefore, this invention achieves speed improvement by reducing the amplitude of high and low level signals in the internal circuit, and for different power supply voltages, the gate voltage control signal swing of its internal large-size output drive LDMOS transistor remains a fixed value VCCL, unaffected by changes in the output drive power supply voltage.

[0030] Figure 4 This is one implementation of the low-side power supply generation circuit 1 of the present invention. The circuit consists of NMOS transistors M101 and M102, PMOS transistors M103 and M104, LDPMOS transistors M105 and M106, LDNMOS transistors M107 and M108, LDNMOS transistors M110 and M109, NMOS transistors M111, resistors R11, R12, R13 and R14, and capacitor C11.

[0031] In this configuration, the drain and gate of NMOS transistor M101, as well as the gate of NMOS transistor M102, are connected to the lower end of resistor R11. The input reference voltage Vref is connected to the upper end of resistor R11 and to the gate of LDNMOS transistor M107. The source of LDNMOS transistor M107 is connected to the drain of NMOS transistor M102. The gate and drain of PMOS transistor M103, the gate of PMOS transistor M104, and the source of LDPMOS transistor M105 are connected. The gate and drain of LDPMOS transistor M105, the gate of LDPMOS transistor M106, and the drain of LDNMOS transistor M107 are connected. The drain of PMOS transistor M104 is connected to the source of LDPMOS transistor M106. The following connections are made: the drain of LDPMOS transistor M106 is connected to the drain of LDNMOS transistor M108, and is also connected to the gate of LDNMOS transistor M110 and the gate of LDNMOS transistor M108, as well as one end of capacitor C11; the source of LDNMOS transistor M108 is connected to the upper end of resistor R12, and is also connected to the other end of C11; the lower end of resistor R12 is connected to the upper end of resistor R13, and is also connected to the gate of NMOS transistor M111; the lower end of resistor R13 is connected to the drain and gate of NMOS transistor M109; the source of LDNMOS transistor M110 and the drain of NMOS transistor M111 are connected to the upper end of resistor R14, which also serves as the voltage output terminal of low-side power supply generation circuit 1, outputting VCCL. The sources of PMOS transistors M103 and M104, and the drain of LDNMOS transistor M110 are all connected to the power supply voltage VCC; the sources of NMOS transistors M101, M102, M109, and M111, and the lower end of resistor R14 are all connected to the ground voltage VSS.

[0032] Figure 4 In the given embodiment, the low-side power generation circuit 1 consists of a common-source cascode current mirror, a cascode current mirror, and a source follower, and its function is to output a stable voltage VCCL. The circuit operates as follows: the reference voltage Vref is connected to the gate of LDNMOS transistor M107, and simultaneously connected to the gates of NMOS transistors M101 and M102 through a step-down resistor R11, providing bias voltages to the common-source cascode current mirror composed of NMOS transistors M101, M102, and LDNMOS transistor M107; the drain of LDNMOS transistor M107 is connected to the cascode current mirror composed of PMOS transistors M103, M104, LDPMOS transistors M105, and M106, and the drain of LDPMOS transistor M106 receives the replicated current I. refR12 and R13 are voltage divider resistors, LDNMOS transistor M108 and NMOS transistor M109 are diode-connected MOS transistors, and capacitor C11 is used for filtering and compensation. At this time, the voltage at node A satisfies formula (1):

[0033] V A =I ref ×(R12+R13)+V ds_108 +V ds_109 (1)

[0034] V ds_108 This represents the source-drain voltage of the LDNMOS transistor M108, V. ds_109 This represents the source-drain voltage of the NMOS transistor M109.

[0035] LDNMOS transistor M110 and NMOS transistor M111 form a source follower. Therefore, when the circuit is working normally, the output voltage VCCL = VA - Vgs_110. Vgs_110 represents the gate-source voltage of LDNMOS transistor M110. It can be seen that the voltage VCCL is determined by the external reference voltage Vref, resistors R12 and R13, and the parameters of LDNMOS transistors M108, M109, and M110. By setting an appropriate combination of parameters, a voltage VCCL of 5V can be achieved.

[0036] Figure 5 This is one implementation of the high-side floating power supply generation circuit 2 of the present invention. The circuit consists of LDPMOS transistors M201, M202, M203, M204, M205, M206, and M207, capacitors C21 and C22, and resistors R21, R22, and R23.

[0037] In this configuration, the source of LDPMOS transistor M201 is connected to the upper end of resistor R21, and the lower end of resistor R21 is connected to the upper end of resistor R22, which is also connected to the gate of LDPMOS transistor M202. The lower end of resistor R22 is connected to the source of LDPMOS transistor M203, and also to the lower end of capacitor C21 and the upper end of capacitor C22. The gate and drain of LDPMOS transistor M203, the gate of LDPMOS transistor M204, and the drain of LDPMOS transistor M205 are connected together, and also connected to the lower end of capacitor C22. The gate of LDPMOS transistor M205 is connected to the gate of LDPMOS transistor M205, and also connected to the bias voltage Vb4. LDPMOS transistor M205... The source of LDPMOS transistor M202 is connected to the drain of LDPMOS transistor M204, and the gate of LDPMOS transistor M207 is connected to the reference voltage Vref. The drain of LDPMOS transistor M202 is connected to the source of LDPMOS transistor M204 and the lower end of resistor R23, which also serves as the output terminal of high-side floating power supply generation circuit 2, outputting Vsh. The drain of LDPMOS transistor M204 is connected to the drain of LDPMOS transistor M205. The source of NMOS transistor M207 and the source of LDPMOS transistor M205 are connected to ground voltage VSS. The gate and drain of LDPMOS transistor M201, the upper end of capacitor C21, the source of LDPMOS transistor M202, and the upper end of resistor R23 are all connected to the power supply voltage VCC.

[0038] Figure 5 The given embodiment provides a Vsh voltage with a fixed voltage difference from VCC. The circuit operates as follows: the reference voltage Vref is connected to the gate of NMOS transistor M207. Since the source of NMOS transistor M207 is grounded, Vref determines the drain-source current of NMOS transistor M207. LDPMOS transistors M203, M205, M205, and M207 form a cascode current mirror, replicating the source current of LDPMOS transistor M203 to the source of LDPMOS transistor M204. Resistors R21 and R22 are voltage divider resistors. When the circuit operates normally, the output voltage Vsh = VCC - V0. sd_202 V sd_202 This refers to the source-drain voltage of the LDPMOS transistor M202.

[0039] Figure 6This is one implementation of the level shifting circuit 3 of the present invention. The circuit consists of PMOS transistors M901, M902, M903, M904, M905, M906, LDPMOS transistors M907, M908, LDNMOS transistors M913, M914, NMOS transistors M909, M910, M911, and M912, resistor R91, and inverter inv91.

[0040] In this configuration, the gate of PMOS transistor M901 is connected to the drain of PMOS transistor M902 and the source of LDPMOS transistor M908, and also to the gate of PMOS transistor M903; the gate of PMOS transistor M902 is connected to the drain of PMOS transistor M901 and the source of LDPMOS transistor M907, and also to the lower end of resistor R91 and the gate of PMOS transistor M904; the gates of LDPMOS transistor M907 and M908 are connected and serve as the input terminal of voltage Vsh; the input signal Vin is connected to the input terminal of inverter inv91 and the gate of LDPMOS transistor M914, the output terminal of inverter inv91 is connected to the gate of LDPMOS transistor M913, and the drain of LDPMOS transistor M907 and L... The drains of DNMOS transistor M913 and LDPMOS transistor M908 are connected together; the drains of LDPMOS transistor M908 and LDPMOS transistor M914 are connected together; the drain of PMOS transistor M903 is connected to the drain of NMOS transistor M909 and also to the gate of NMOS transistor M910; the drain of PMOS transistor M904 is connected to the drain of NMOS transistor M910, and then to the gate of NMOS transistor M909, as well as the gates of PMOS transistors M905 and M911; the drain of PMOS transistor M905 is connected to the drain of NMOS transistor M911, and also to the gates of PMOS transistors M906 and M912; the drain of PMOS transistor M906 is connected to the drain of NMOS transistor M912 and serves as the output terminal of signal Vinp. The sources of LDPMOS transistor M913 and LDPMOS transistor M914 are both connected to ground voltage VSS. The gates of LDPMOS transistor M907 and M908, the sources of NMOS transistors M909, M910, M911, and M912 are all connected to the input floating voltage Vsh. The sources of PMOS transistors M901, M902, M903, M904, M905, and M906, as well as the upper end of resistor R91, are all connected to the power supply voltage VCC.

[0041] Figure 6 In the given embodiment, the basic function of the high-voltage level shifting circuit 3 is to convert the input pulse signal Vin, which has a low level of VSS and a high level of VCCL, into a signal Vinp, which has a low level of floating voltage Vsh and a high level of VCC, for output. The level shifting circuit 3 simultaneously uses the low-voltage power supply VCCL, the power supply voltage VCC, the ground voltage VSS, and the floating voltage Vsh.

[0042] Figure 6 The interlocked connection of two PMOS transistors, M901 and M902, forms a positive feedback loop. The interlocked connection of two NMOS transistors, M909 and M910, forms a positive feedback loop. PMOS transistors M905, M906, M911, and M912 form a buffer.

[0043] Figure 7 The simulation waveform diagram of the present invention is shown. The input Vin is a 5V square wave signal, and VCC = 24V. It can be seen that Vgh is a pulse signal with a high level of 24V and a low level of 19V, and Vgl is a pulse signal with a high level of 5V and a low level of 0V. When Vgl is 0, the output VO is 24V, and when Vgl is 5V, the output VO is 0V. The VO output level swing is the 24V drive signal. It can be seen from the figure that the signal delay from Vin to VO is 10ns, and the delay from Vin to Vgh is only 5ns.

[0044] Figure 8 This illustrates the application of the present invention in a half-bridge gate driver chip circuit. For example... Figure 8 As shown, the gate driver chip adopts a level-shift architecture, including an interface and logic circuit module, a protection circuit module, and an output driver circuit module. The output driver circuit is divided into a high-side driver circuit 81 and a low-side driver circuit 82, which transmit high-voltage drive signals and low-voltage drive signals respectively, effectively turning the half-bridge circuit on and off. The high-voltage and low-voltage signals are not grounded, achieving electrical isolation between the high and low voltages.

[0045] In normal operating mode, after the input signal enters the interface circuit, it first undergoes a medium-voltage level shift to convert the low-voltage logic level into a high-level logic signal (VCC). Then, it enters the dead-time generation circuit, generating high-side and low-side pulse drive signals with a dead-time interval. Since the high-side signal needs to pass through the high-voltage level shift circuit before entering the high-side output drive, this inevitably introduces a signal delay. Therefore, the low-side signal must pass through a delay compensation circuit before entering the low-side output drive. Finally, the high-side and low-side pulse signals are output as HO and LO drive signals respectively through the high-side drive circuit 81 and the low-side drive circuit 82. To ensure rapid charging and discharging of the gate capacitor of the high-voltage power device, enabling rapid saturation conduction and reliable turn-off, the output drive circuit requires low output impedance and high output current (several amperes). The high-side drive circuit 81 and the low-side drive circuit 82 can be implemented using this invention to reduce signal delay.

[0046] Figure 9 This illustration demonstrates the application of an embodiment of the present invention in an AC / DC power supply chip. The switching power supply controls the power on / off duty cycle, utilizes inductors to store and transfer energy, and then converts the originally varying input AC or DC voltage into the required stable DC output voltage. Functionally, the AC / DC control chip is mainly divided into four major functional modules: a reference generation module, a constant voltage control module, a constant current control module, a logic control module, and an output drive module. The reference generation module mainly includes a high-voltage regulator circuit, which receives the high voltage from the VDD pin and converts it into an internal 5V power supply voltage to provide a stable low-voltage power supply for all low-voltage modules inside the chip. The constant voltage control module samples the output voltage, and the sample / hold circuit, error amplifier EA, and negative feedback resistor together form an inverting amplifier with a fixed gain of 40. The output voltage of the error amplifier is sent to the PWM comparator to generate the turn-on signal for the power transistor. The constant current control module mainly generates constant current turn-on and constant current turn-off signals, and the system starts in constant current mode. The logic control module determines the current load conditions based on the sampled signals of each port and selects the required constant voltage or constant current turn-on / turn-off signal in the logic control circuit. The low-delay high-speed output drive module 90 designed in this invention is used to drive and buffer the turn-on / turn-off signals output by the logic control module and generate the output drive signal DRV for the power transistor.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-delay, high-speed output drive circuit, comprising k progressively larger high-side inverter chains, k progressively larger low-side inverter chains, a high-side drive PMOS transistor M31, and a low-side drive NMOS transistor M32, where k is a positive integer, characterized in that... It also includes a low-side power supply generation circuit (1), a high-side floating power supply generation circuit (2), and a level shifting circuit (3); the input pulse signal Vin is connected to the input terminal of the N-terminal inverter chain, and at the same time, the input pulse signal Vin is connected to the input terminal of the P-terminal inverter chain through the level shifting circuit (3); the level shifting circuit (3) outputs the P-terminal input signal Vinp into the P-terminal inverter chain, and the P-terminal inverter chain outputs the control signal Vgh connected to the gate of the P-terminal driving PMOS transistor M31; The N-terminal inverter chain output control signal Vgl is connected to the gate of the N-terminal driving NMOS transistor M32; the control signals Vgh and Vgl are used to control the turn-on and turn-off of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32, respectively. The source of the P-terminal driving PMOS transistor M31 is connected to the power supply voltage VCC. The drain of the P-terminal driving PMOS transistor M31 is connected to the drain of the N-terminal driving NMOS transistor M32 and outputs a drive signal VO. The source of the N-terminal driving NMOS transistor M32 is grounded to the voltage VSS. The power supply voltage of all inverters in the P-terminal inverter chain is connected to the power supply voltage VCC, and the ground potential of all inverters in the P-terminal inverter chain is connected to the floating voltage Vsh. The power supply voltage of all inverters in the N-terminal inverter chain is connected to the low-voltage power supply VCCL, and the ground potential of all inverters in the N-terminal inverter chain is connected to the ground voltage VSS. The floating voltage Vsh is obtained by the high-side floating power generation circuit (2) at the P terminal stepping down the power supply voltage VCC, and its voltage value Vsh = VCC - VCCL; the low-voltage power supply VCCL is generated by the low-side power generation circuit (1) at the N terminal, and the VCCL voltage is less than the power supply voltage VCC; the power supply terminal of the level shifting circuit (3) uses the power supply voltage VCC, and the ground terminal uses the floating voltage Vsh and the ground voltage VSS respectively. The level shifting circuit (3) converts the input pulse signal Vin with low level VSS and high level VCCL into the P terminal input signal Vinp with low level Vsh and high level VCC.

2. The low-delay high-speed output drive circuit according to claim 1, characterized in that, The source-drain and gate-source breakdown voltages of all PMOS and NMOS transistors within the P-terminal inverter chain and N-terminal inverter chain must be VCCL; the gate-source breakdown voltage of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32 must be VCCL, and the source-drain breakdown voltage of the P-terminal driving PMOS transistor M31 and the N-terminal driving NMOS transistor M32 must be VCC.

3. The low-delay high-speed output drive circuit according to claim 1, characterized in that, The low-side power supply generation circuit (1) includes: NMOS transistors M101, M102, M103, M104, M105, M106, M107, M108, M110, M109, and M111; resistors R11, R12, R13, and R14; and capacitor C11. The drain of NMOS transistor M101 is connected to the NMOS transistor M110. The gates of M101 and M102 of the NMOS transistor are connected to the reference voltage Vref via resistor R11; the gate of LDNMOS transistor M107 is also connected to the reference voltage Vref, and the source of LDNMOS transistor M107 is connected to the drain of NMOS transistor M102; the gate of PMOS transistor M103 is connected to the drain of PMOS transistor M103, the gate of PMOS transistor M104, and the source of LDPMOS transistor M105; the gate of LDPMOS transistor M105 is connected to the drain of LDPMOS transistor M105, the gate of LDPMOS transistor M106, and L... The drain of NMOS transistor M107, the drain of PMOS transistor M104, and the source of LDPMOS transistor M106 are connected. The drain of LDPMOS transistor M106 is connected to the drain of LDNMOS transistor M108, the gate of LDNMOS transistor M110, the gate of LDNMOS transistor M108, and one end of capacitor C11. The source of LDNMOS transistor M108 is connected to the other end of capacitor C11 and the upper end of resistor R12. The lower end of resistor R12 is connected to the upper end of resistor R13 and the gate of NMOS transistor M111. The lower end of resistor R13 is connected to the gate of NMOS transistor M107. The drain of transistor M109 is connected to the gate of NMOS transistor M109; the source of LDNMOS transistor M110 is connected to the drain of NMOS transistor M111 and the upper end of resistor R14, and serves as the output terminal of the low-voltage power supply VCCL; the sources of PMOS transistors M103 and M104, and the drain of LDNMOS transistor M110 are all connected to the power supply voltage VCC; the sources of NMOS transistors M101, M102, M109, and M111, and the lower end of resistor R14 are all connected to the ground voltage VSS.

4. The low-delay high-speed output drive circuit according to claim 1, characterized in that, The high-side floating power supply generation circuit (2) includes: LDPMOS transistors M201, M202, M203, M204, M205, M206, and M207; capacitors C21 and C22; resistors R21, R22, and R23; the source of LDPMOS transistor M201 is connected to the upper end of resistor R21, and the lower end of resistor R21 is connected to the upper end of resistor R22 and the gate of LDPMOS transistor M202; the lower end of resistor R22 is connected to the source of LDPMOS transistor M203 and the lower end of capacitor C21, and the lower end of capacitor C21 is connected to the upper end of capacitor C22; the gate of LDPMOS transistor M203 is connected to the drain of LDPMOS transistor M203, the gate of LDPMOS transistor M204, and the gate of LDPMOS transistor M207. The drain of LDPMOS transistor M205 is connected to the lower end of capacitor C22; the gate of LDPMOS transistor M205 is connected to the gate of LDPMOS transistor M205 and also to the bias voltage Vb4; the source of LDPMOS transistor M205 is connected to the drain of NMOS transistor M207, and the gate of NMOS transistor M207 is connected to the reference voltage Vref; the drain of LDPMOS transistor M202 is connected to the source of LDPMOS transistor M204 and the lower end of resistor R23, and serves as the output terminal of floating voltage Vsh; the drain of LDPMOS transistor M204 is connected to the drain of LDPMOS transistor M205; the sources of NMOS transistor M207 and LDPMOS transistor M205 are connected to ground voltage VSS; the gate of LDPMOS transistor M201, the drain of LDPMOS transistor M201, the upper end of capacitor C21, the source of LDPMOS transistor M202, and the upper end of resistor R23 are all connected to the power supply voltage VCC.

5. The low-delay high-speed output drive circuit according to claim 1, characterized in that, The level shifting circuit (3) includes: PMOS transistors M901, M902, M903, M904, M905, M906, LDPMOS transistors M907, M908, LDNMOS transistors M913, M914, NMOS transistors M909, M910, M911, and M912; resistor R91; and inverter inv91; the gate of PMOS transistor M901 is connected to the drain of PMOS transistor M902. The source of DPMOS transistor M908 and the gate of PMOS transistor M903 are connected. The gate of PMOS transistor M902 is connected to the drain of PMOS transistor M901, the source of LDPMOS transistor M907, the lower end of resistor R91, and the gate of PMOS transistor M904. The input pulse signal Vin is connected to the input of inverter inv91 and the gate of LDNMOS transistor M914. The output of inverter inv91 is connected to the gate of LDNMOS transistor M913. The drains of LDPMOS transistor M907 and LDNMOS transistor M913 are connected. The drain of LDPMOS transistor M908 and LDNMOS transistor M904 are connected.

14. Drains connected; PMOS transistor M903 drain connected to M909 drain and NMOS transistor M910 gate; PMOS transistor M904 drain connected to NMOS transistor M910 drain, NMOS transistor M909 gate, PMOS transistor M905 gate and NMOS transistor M911 gate; PMOS transistor M905 drain connected to NMOS transistor M911 drain, PMOS transistor M906 gate and NMOS transistor M912 gate; PMOS transistor M906 drain and NMOS transistor M912 drain connected, serving as the output terminal of signal Vinp; LDNMOS transistor M913 source and... The source of LDNMOS transistor M914 is simultaneously connected to ground voltage VSS; the gates of LDPMOS transistors M907 and M908, the sources of NMOS transistors M909, M910, M911, and M912 are simultaneously connected to floating voltage Vsh; the sources of PMOS transistors M901, M902, M903, M904, M905, and M906, as well as the upper end of resistor R91, are simultaneously connected to power supply voltage VCC.

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