Clock system frequency division switching method and system

Abstract

The application provides a clock system frequency division switching method and system. The method comprises: generating a clock non-frequency division mode signal when a clock selection signal is detected; controlling a clock frequency division module to enter a non-frequency division mode based on the clock non-frequency division mode signal; switching an output clock of a clock switching module to a preset low-frequency clock; identifying a main clock frequency control word and a clock frequency division number; adjusting the preset high-frequency clock based on the main clock control word to obtain an adjusted clock; when the clock selection signal and the clock non-frequency division mode signal are both detected to disappear, controlling the clock frequency division module to exit the non-frequency division mode, and switching the output clock of the clock switching module to the adjusted clock; and controlling the clock frequency division module to output a frequency division clock based on the clock frequency division number. It can be seen that the method and system can solve the clock phase alignment problem after the frequency division number of the module clock is changed, and can also solve the clock phase alignment adjustment problem after the system main clock is changed.

Description

Technical Field

[0001] This application relates to the field of clock system technology, and more specifically, to a clock system frequency division switching method and system. Background Technology

[0002] In complex chip system architectures, multiple functional modules are typically included. These modules may require different clock frequencies to meet operational needs. These module clocks are generally derived by dividing the system master clock. Some module clocks may also need to maintain clock phase alignment with the clocks of other functional modules. Furthermore, some functional modules may operate at different clock frequencies depending on their operating mode. This necessitates configuring different division ratio parameters for the clock division units of these modules. However, in practice, it has been found that when the division ratio parameter changes, the output module clock often changes as well, leading to many unnecessary problems. Therefore, ensuring the alignment between the clocks of certain modules when the module division ratio and the system master clock change has become one of the urgent technical problems to be solved in this field. Summary of the Invention

[0003] The purpose of this application is to provide a clock system frequency division switching method and system, which can solve the clock phase alignment problem that occurs after the frequency division of the module clock is changed, and can also solve the clock phase alignment adjustment problem that occurs after the system master clock is changed.

[0004] The first aspect of this application provides a clock system frequency division switching method, including:

[0005] When a clock selection signal is detected, a clock non-division mode signal is generated;

[0006] Based on the clock non-division mode signal, control the clock division module to enter non-division mode;

[0007] Switch the output clock of the clock switching module to a preset low-frequency clock;

[0008] Identify the master clock frequency control word and clock divider number;

[0009] The preset high-frequency clock is adjusted based on the master clock control word to obtain the adjusted clock;

[0010] When the clock selection signal and the clock non-division mode signal are both detected to be missing, the clock division module is controlled to exit the non-division mode, and the output clock of the clock switching module is switched to the adjustment clock.

[0011] The clock division module is controlled to output a divided clock based on the clock division number.

[0012] Furthermore, the step of generating a non-division clock mode signal when a clock selection signal is detected includes:

[0013] When a clock selection signal is detected, a clock synchronization reset signal is generated;

[0014] The clock division module is reset based on the clock synchronization reset signal;

[0015] Generate a clock non-division mode signal.

[0016] Furthermore, after the step of adjusting a preset high-frequency clock based on the master clock control word to obtain the adjusted clock, the method further includes:

[0017] When a frequency stability indicator is detected at the output of the phase-locked loop or clock oscillator, the clock selection signal is pulled low to make the clock selection signal disappear.

[0018] Furthermore, after the step of pulling down the clock selection signal to make the clock selection signal disappear when a frequency stability indicator output by the phase-locked loop or clock oscillator is detected, the method further includes:

[0019] Pull the clock non-division mode signal low to make the clock non-division mode signal disappear.

[0020] Further, the clock frequency division module includes a first clock frequency division submodule and a second clock frequency division submodule, and the clock frequency division number includes a first frequency division number and a second frequency division number. The step of controlling the clock frequency division module to output a divided clock based on the clock frequency division number includes:

[0021] The first clock frequency divider submodule is controlled to output a first frequency divided clock based on the first frequency division number; the second clock frequency divider submodule is controlled to output a second frequency divided clock based on the second frequency division number.

[0022] A second aspect of this application provides a clock system frequency division switching system, the clock system frequency division switching system comprising:

[0023] The generation unit is used to generate a clock non-division mode signal when a clock selection signal is detected;

[0024] The control unit is used to control the clock division module to enter the non-division mode based on the clock non-division mode signal;

[0025] The switching unit is used to switch the output clock of the clock switching module to a preset low-frequency clock.

[0026] The identification unit is used to identify the master clock frequency control word and the clock division number;

[0027] The adjustment unit is used to adjust a preset high-frequency clock based on the master clock control word to obtain an adjusted clock;

[0028] The control unit is further configured to, when it is detected that both the clock selection signal and the clock non-division mode signal have disappeared, control the clock division module to exit the non-division mode and switch the output clock of the clock switching module to the adjustment clock;

[0029] The output unit is used to control the clock division module to output a divided clock based on the clock division number.

[0030] Furthermore, the generation unit includes:

[0031] The generation subunit is used to generate a clock synchronization reset signal when a clock selection signal is detected.

[0032] The reset subunit is used to reset the clock divider module based on the clock synchronization reset signal;

[0033] The generation subunit is also used to generate a clock non-division mode signal.

[0034] Furthermore, the clock system frequency division switching system also includes:

[0035] The processing unit is configured to, after adjusting a preset high-frequency clock based on the master clock control word to obtain the adjusted clock, and upon detecting a frequency stability indicator output by the phase-locked loop or clock oscillator, pull down the clock selection signal to make the clock selection signal disappear.

[0036] Furthermore, the processing unit is also configured to, after detecting a frequency stability indicator output by a phase-locked loop or a clock oscillator, pull down the clock selection signal to make the clock selection signal disappear, and then pull down the clock non-division mode signal to make the clock non-division mode signal disappear.

[0037] Furthermore, the clock frequency division module includes a first clock frequency division submodule and a second clock frequency division submodule, and the clock frequency division number includes a first frequency division number and a second frequency division number. Specifically, the output unit is used to control the first clock frequency division submodule to output a first frequency division clock based on the first frequency division number; and to control the second clock frequency division submodule to output a second frequency division clock based on the second frequency division number.

[0038] A third aspect of this application provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor runs the computer program to cause the electronic device to perform the clock system frequency division switching method described in any one of the first aspects of this application.

[0039] The fourth aspect of this application provides a computer-readable storage medium storing computer program instructions, which, when read and executed by a processor, perform the clock system frequency division switching method described in any one of the first aspects of this application. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating a clock system frequency division switching method provided in an embodiment of this application;

[0042] Figure 2 A schematic diagram of a clock system frequency division switching system provided in this application embodiment;

[0043] Figure 3 A system functional block diagram for frequency division switching in a multi-clock system provided in this application embodiment;

[0044] Figure 4 A system functional block diagram of a clock divider module provided in an embodiment of this application;

[0045] Figure 5 This application provides a waveform diagram illustrating a clock system frequency division switching method. Detailed Implementation

[0046] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0047] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] Example 1

[0049] Please refer to Figure 1 , Figure 1 This embodiment provides a flowchart illustrating a clock system frequency division switching method. The clock system frequency division switching method includes:

[0050] S101. When a clock selection signal is detected, a clock synchronization reset signal is generated.

[0051] S102. Reset the clock divider module based on the clock synchronization reset signal.

[0052] S103, Generate clock non-division mode signal.

[0053] S104. Based on the clock non-division mode signal, control the clock division module to enter non-division mode.

[0054] S105. Switch the output clock of the clock switching module to a preset low-frequency clock.

[0055] S106. Identify the master clock frequency control word and clock division number.

[0056] S107. Adjust the preset high-frequency clock based on the master clock control word to obtain the adjusted clock.

[0057] S108. When the frequency stability indicator of the phase-locked loop or clock oscillator output is detected, pull the clock selection signal low to make the clock selection signal disappear.

[0058] S109. Pull the clock non-division mode signal low to make the clock non-division mode signal disappear.

[0059] S110. When both the clock selection signal and the clock non-division mode signal are detected to disappear, control the clock division module to exit the non-division mode and switch the output clock of the clock switching module to the adjustment clock.

[0060] S111, the first clock division submodule in the control clock division module outputs a first divided clock based on the first division number in the clock division number; the second clock division submodule in the control clock division module outputs a second divided clock based on the second division number in the clock division number.

[0061] In this embodiment, the clock frequency division module includes a first clock frequency division submodule and a second clock frequency division submodule, and the clock frequency division number includes a first frequency division number and a second frequency division number.

[0062] In this embodiment, the step of controlling the clock divider module to output a divided clock based on the clock division number includes:

[0063] The first clock frequency divider submodule is controlled to output a first frequency divider clock based on a first frequency divider number; the second clock frequency divider submodule is controlled to output a second frequency divider clock based on a second frequency divider number.

[0064] Please refer to Figure 3 , Figure 3The multi-clock system frequency division switching system shown includes a clock oscillator or phase-locked loop module 104. The function of this module is to provide a high-frequency master clock output 201 for the system. The frequency of the high-frequency master clock output by 104 is determined by the control word input 207. When 207 changes, it takes a period of time to output a stable system master clock.

[0065] Figure 3 The clock switching module 101 includes two clock inputs and one clock output. One clock input, 201, is from the oscillator output and is a high-frequency clock. The other is a low-frequency clock, 202. These two clocks can be synchronous or asynchronous. The output clock 206 of the clock switching module 101 is the system master clock after internal gating and is controlled by the input clock selection signal 203 of the clock switching module 101. The clock switching module 101 also includes two output control signals: a clock synchronization reset signal 204 (clk_rst) and a clock non-division mode signal 205 (clk_div_dis). These two signals are generated during clock switching and are used for the reset and non-division clock output of the subsequent clock division module.

[0066] Figure 3 The diagram also shows clock divider modules 102-10n, which correspond to different clock divider units. The clock for each clock divider unit is provided by the system master clock 206 output by the clock switching module 101. The module's inputs also include a synchronous clock reset signal 204 and a clock non-division control signal 205, which control the circuit state of the clock divider units during clock division number switching. Input signals 211-21n provide the division number for each clock divider module. In clock division mode (i.e., when the non-division mode signal 205 is invalid), each clock divider module generates a divided clock output 301-30n based on its corresponding input division number.

[0067] Please check Figure 4 , Figure 4 Yes Figure 3 A detailed schematic diagram of the clock divider module. Among them, Figure 4 It includes a clock divider circuit 401, a clock gating unit 402, and a clock output selection unit 403. 501 is the module's input clock, which is essentially... Figure 3 In the system master clock, 206 and 502 represent the synchronous clock reset signal (clk_rst), corresponding to... Figure 3 In this context, 204 and 503 represent the clock non-divider module control signals (clk_div_dis), corresponding to... Figure 3205.507 in the text represents the clock divider control word, corresponding to... Figure 3 In the diagram, 211 to 21n are used. 504 is the frequency divider clock output of frequency divider circuit 401, 505 is the output of gate unit 402, and then after being selected by clock gating unit 403, clock 506 is output as the final clock output of this module. For clock gating unit 403, signal 503 is used as the clock gating signal.

[0068] When in normal frequency division mode (i.e., when non-frequency division mode signal 503 is invalid), 501 is a high-frequency clock input, 504 is obtained by frequency division circuit 401 according to the division number 507, and then output to 506 after passing through clock gating module 403. At this time, the input clock 501 is controlled by signal 503 inside the gated clock module 402, so that the output gated clock signal 505 is kept at a low level.

[0069] When in non-division mode, the frequency divider circuit 401 is first reset by the clock synchronization reset signal 502, and then controlled by the non-division mode signal 503, so that the output frequency divider clock signal 504 remains at a low level. At this time, the gated clock module is activated under the control of signal 503 and outputs the gated clock 505, which is then output to 506 through the clock gating module 403.

[0070] Please refer to Figure 5 , Figure 5 This describes the waveform of the entire clock switching process, providing a clearer understanding of the principles behind clock frequency switching and clock phase alignment. Here, clk_sel corresponds to... Figure 3 The clock switching signal 203 is used in the clock switching module 101, while clk_sel_int is the clock switching signal after clk_sel has been processed by the internal logic of the clock switching module 101. Clk_in0 corresponds to... Figure 3 The low-frequency input clock 202, clk_int1 corresponds to Figure 3 The high-frequency input clock 201 in the code comes from a clock oscillator or a phase-locked loop. Clk_main corresponds to... Figure 3 206, which is the system master clock signal. Clk_div0 to clk_div1 correspond to... Figure 3 The clock divider module outputs 301-302, and clk_div2 corresponds to the 30n signal, which is the lowest frequency clock signal that needs phase alignment during clock frequency switching. This clock signal needs to be fed back to the clock switching module 101. clk_rst corresponds to... Figure 3The synchronous clock reset signal 204, clk_div_dis corresponds to the non-division mode signal 205, OSC_FCW clock oscillator or PLL clock frequency control word 207, Clk_div0_sel, clk_div1_sel, clk_div2_sel are the clock division control words for clk_div0, clk_div1, and clk_div2, respectively. Figure 3 211, 212, 213.

[0071] based on Figure 5 As can be seen, this method actually divides the frequency division switching process into three stages. A specific example is as follows:

[0072] The period from t0 to t3 is the time before the frequency division switch. During this period, clk_main operates in high-frequency mode, with its clock sourced from clk_in1 (given by the OSC / PLL). The clock phase of clk_div2 is aligned with both clk_div0 and clk_div1. Here, we assume that at time t1, the system software sets the clk_sel signal, causing the output of clk_main to switch to the clk_in0 clock. After clk_sel goes high, the internal control logic detects the rising edge of the lowest frequency clock that needs to be aligned (here, we assume it is clk_div2), and then generates the non-division mode signal clk_div_dis, causing the clock divider module to enter non-division mode. Then, at time t3, the actual strobe signal (assuming it is clk_sel_int) is generated after synchronization processing. At this time, clk_main switches to the clk_in0 input.

[0073] From stage t3 to t7, the frequency division switching stage takes place. During this period, the frequency divisions clk_div0_sel-clk_div2_sel of clk_div0-clk_div2 are reconfigured, regardless of the order of configuration. Furthermore, the frequency control word of the phase-locked loop or clock oscillator can be reconfigured to change the clock frequency of clk_in1. After the frequency control word is changed, the system software queries the frequency stability flag sent by the phase-locked loop or clock oscillator (assuming that t4-t6 is the stabilization time). If it is stable, clk_sel is pulled low. The internal logic of the clock switching module then pulls clk_div_dis low and pulls clk_sel_int low at t7, causing clk_main to return to clk_in1 strobe and the clock divider to return to normal frequency division mode.

[0074] The third stage begins at time t7. In this stage, clk_main returns to the clk_in1 input state, and the clock divider module also returns to the divider mode. At this point, we can see that the frequency of clk_in1 has changed because the frequency control word was adjusted earlier. Let's assume the frequency has doubled. clk_div0 has changed from a divider of 2 to a divider of 6, and clk_div1 has changed from a divider of 3 to a divider of 4. The frequency of div3 has not changed, but the divider number has changed from a divider of 6 to a divider of 12 because clk_main has doubled. At this point, we can see that from time t7 onwards, the phase of the clk_div3 clock is still aligned with clk_div0 and clk_div1. This completes the entire process of switching the clock divider number and changing the frequency control word.

[0075] In this embodiment, the subject executing the method can be a computing system such as a computer or server, and no limitation is made in this embodiment.

[0076] In this embodiment, the subject executing the method can also be a smart device such as a smartphone or tablet, and no limitation is made in this embodiment.

[0077] As can be seen, the clock system frequency division switching method described in this embodiment can solve the problem of multiple clock frequency switching and phase alignment with relatively simple hardware logic and system software flow, thereby reducing the complexity of circuit logic and simplifying the software operation process. Furthermore, it eliminates the need to consider the timing dependency between clock frequency division configurations, which is beneficial to improving operation efficiency.

[0078] Example 2

[0079] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a clock system frequency division switching system provided in this embodiment. Figure 2 As shown, the clock system frequency division switching system includes:

[0080] The generation unit U210 is used to generate a clock non-division mode signal when a clock selection signal is detected;

[0081] The control unit U220 is used to control the clock divider module to enter the non-division mode based on the clock non-division mode signal;

[0082] The switching unit U230 is used to switch the output clock of the clock switching module to a preset low-frequency clock;

[0083] The identification unit U240 is used to identify the master clock frequency control word and the clock division number;

[0084] The adjustment unit U250 is used to adjust the preset high-frequency clock based on the master clock control word to obtain the adjusted clock;

[0085] The control unit U220 is also used to control the clock division module to exit the non-division mode and switch the output clock of the clock switching module to the adjustment clock when the clock selection signal and the clock non-division mode signal are both detected to disappear.

[0086] The output unit U260 is used to control the clock divider module to output a divided clock based on the clock division number.

[0087] As an optional implementation, the generation unit U210 includes:

[0088] The generation subunit U211 is used to generate a clock synchronization reset signal when a clock selection signal is detected.

[0089] The reset subunit U212 is used to reset the clock divider module based on the clock synchronization reset signal;

[0090] The generation subunit U211 is also used to generate clock non-division mode signals.

[0091] As an optional implementation, the clock system frequency division switching system also includes:

[0092] The processing unit U270 is used to pull down the clock selection signal so that the clock selection signal disappears after adjusting the preset high-frequency clock based on the master clock control word and after detecting the frequency stability indicator output by the phase-locked loop or clock oscillator.

[0093] As an optional implementation, the processing unit U270 is also configured to, after detecting a frequency stability indicator output by the phase-locked loop or clock oscillator, pull down the clock selection signal to make the clock selection signal disappear, and then pull down the clock non-division mode signal to make the clock non-division mode signal disappear.

[0094] As an optional implementation, the clock divider module includes a first clock divider submodule and a second clock divider submodule, and the clock divider number includes a first divider number and a second divider number. Specifically, the output unit U260 is used to control the first clock divider submodule to output a first divided clock based on the first divider number; and to control the second clock divider submodule to output a second divided clock based on the second divider number.

[0095] In this embodiment, the clock system frequency division and switching system can be referred to as a multi-clock generation and frequency switching system, which mainly includes:

[0096] The clock oscillator unit generates the high-frequency clock required by the system based on the frequency control word.

[0097] The clock switching module has two input clocks: a high-frequency clock from the clock oscillator and a relatively low-frequency clock. The clock strobe signal is controlled by the system software to generate the master clock required by the system. During switching, a clock synchronization reset signal and a non-division mode indication signal are also generated to control the clock division module.

[0098] The clock divider module generates a divided clock based on the divider control word in divider mode, while in non-divider mode, the internal divider circuit is reset, so the system master clock is output directly without divider.

[0099] In this embodiment, the high-frequency clock of the clock switching unit can come from a clock oscillator, which can be a phase-locked loop, or it can be provided by an off-chip clock module and transmitted to the on-chip via an interface unit, without necessarily being implemented on-chip.

[0100] In this embodiment, the input clock of the clock switching unit is not necessarily two, but can be multiple, and these multiple clocks can be synchronous or asynchronous.

[0101] In this embodiment, the system can operate according to the following execution flow when controlling the corresponding execution unit:

[0102] (1) In the initial state, the system master clock is in high frequency mode. At this time, the frequency divider clocks are in phase alignment. Then, the system software changes the clock strobe signal of the clock switching unit to switch to low frequency mode. At the same time, the hardware logic of the clock switching unit generates a synchronous clock reset signal and sets the non-frequency divider mode control signal, and then sends it to each clock divider module. After receiving the reset signal, the clock divider module will reset the corresponding frequency divider circuit.

[0103] (2) The clock divider module will switch the output clock to non-division mode according to the non-division mode control signal, that is, directly take the input clock from the divider module.

[0104] (3) The system software will sequentially set the frequency division control words of each clock division unit as needed, and configure the frequency control words of the on-chip clock oscillator or phase-locked loop as required (or you can choose not to configure them). The order of setting the above control words can be random and there is no dependency between them.

[0105] (4) If the frequency control word of the clock oscillator unit is selected, the system software needs to periodically query the clock stability or lock signal given by the clock oscillator. Once the lock is found, the system software will set the clock gating control signal to re-gating the system master clock to the high-frequency clock output by the clock oscillator.

[0106] (5) After the strobe signal of the clock switching unit is reset, the non-division mode control signal will be pulled low. In this way, the output clock of the clock division module will also be reselected to be the division clock output from the internal division circuit. At the same time, the division units inside all clock division modules will start counting and dividing again (since the synchronous clock was reset when switching to low frequency, the initial state of all division units is the same), thus ensuring the alignment relationship of each division clock phase.

[0107] In this embodiment, the explanation of the clock system frequency division switching system can be referred to the description in Embodiment 1, and will not be repeated here.

[0108] As can be seen, implementing the clock system frequency division switching system described in this embodiment can solve the problems of multi-clock frequency switching and phase alignment with relatively simple hardware logic and system software flow, thereby reducing the complexity of circuit logic and simplifying the software operation process. Furthermore, it eliminates the need to consider the timing dependency between clock frequency division configurations, which is beneficial to improving operation efficiency.

[0109] This application provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor runs the computer program to enable the electronic device to perform the clock system frequency division switching method in embodiment 1 of this application.

[0110] This application provides a computer-readable storage medium storing computer program instructions. When the computer program instructions are read and executed by a processor, the clock system frequency division switching method in embodiment 1 of this application is performed.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can also be implemented in other ways. The system embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0112] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0113] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0114] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0116] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A clock system frequency division switching method, characterized in that, include: When a clock selection signal is detected, a clock synchronization reset signal is generated; The clock division module is reset based on the clock synchronization reset signal; Generate a clock non-division mode signal; Based on the clock non-division mode signal, control the clock division module to enter non-division mode; Switch the output clock of the clock switching module to a preset low-frequency clock; Identify the master clock frequency control word and clock divider number; The preset high-frequency clock is adjusted based on the master clock frequency control word to obtain the adjusted clock; When the clock selection signal and the clock non-division mode signal are both detected to be missing, the clock division module is controlled to exit the non-division mode, and the output clock of the clock switching module is switched to the adjustment clock. The clock division module is controlled to output a divided clock based on the clock division number.

2. The clock system frequency division switching method according to claim 1, characterized in that, After the step of adjusting a preset high-frequency clock based on the master clock frequency control word to obtain the adjusted clock, the method further includes: When a frequency stability indicator is detected at the output of the phase-locked loop or clock oscillator, the clock selection signal is pulled low to make the clock selection signal disappear.

3. The clock system frequency division switching method according to claim 2, characterized in that, After the step of pulling down the clock selection signal to make the clock selection signal disappear when a frequency stability indicator output by the phase-locked loop or clock oscillator is detected, the method further includes: Pull the clock non-division mode signal low to make the clock non-division mode signal disappear.

4. The clock system frequency division switching method according to claim 1, characterized in that, The clock frequency division module includes a first clock frequency division submodule and a second clock frequency division submodule. The clock frequency division number includes a first frequency division number and a second frequency division number. The step of controlling the clock frequency division module to output a divided clock based on the clock frequency division number includes: The first clock frequency divider submodule is controlled to output a first frequency divided clock based on the first frequency division number; the second clock frequency divider submodule is controlled to output a second frequency divided clock based on the second frequency division number.

5. A clock system frequency division switching system, characterized in that, The clock system frequency division switching system includes: The generation unit is used to generate a clock non-division mode signal when a clock selection signal is detected; The control unit is used to control the clock division module to enter the non-division mode based on the clock non-division mode signal; The switching unit is used to switch the output clock of the clock switching module to a preset low-frequency clock. The identification unit is used to identify the master clock frequency control word and the clock division number; The adjustment unit is used to adjust a preset high-frequency clock based on the master clock frequency control word to obtain an adjusted clock; The control unit is further configured to, when it is detected that both the clock selection signal and the clock non-division mode signal have disappeared, control the clock division module to exit the non-division mode and switch the output clock of the clock switching module to the adjustment clock; The output unit is used to control the clock division module to output a divided clock based on the clock division number; The generation unit includes: The generation subunit is used to generate a clock synchronization reset signal when a clock selection signal is detected. The reset subunit is used to reset the clock divider module based on the clock synchronization reset signal; The generation subunit is also used to generate a clock non-division mode signal.

6. The clock system frequency division switching system according to claim 5, characterized in that, The clock system frequency division switching system also includes: The processing unit is configured to, after adjusting a preset high-frequency clock based on the master clock frequency control word to obtain the adjusted clock, and upon detecting a frequency stability indicator output by the phase-locked loop or clock oscillator, pull down the clock selection signal to make the clock selection signal disappear.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory being used to store a computer program, and the processor running the computer program to cause the electronic device to perform the clock system frequency division switching method according to any one of claims 1 to 4.

8. A readable storage medium, characterized in that, The readable storage medium stores computer program instructions, which, when read and executed by a processor, perform the clock system frequency division switching method according to any one of claims 1 to 4.

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