Power transmission device and power transmission system

Abstract

A power delivery device and a power delivery system are disclosed. The power delivery device includes a substrate, a first wafer, a first bump, a second bump, and a first capacitor. The first wafer is used to receive a first reference voltage signal and a second reference voltage signal. The first bump is located between the substrate and the first wafer and is used to transmit the first reference voltage signal from the substrate to the first wafer. The second bump is located between the substrate and the first wafer and is used to transmit the second reference voltage signal from the substrate to the first wafer. The first capacitor is located on the substrate and below the first wafer, with a first terminal coupled to the first bump and a second terminal coupled to the second bump. This reduces noise in the reference voltage signal.

Description

Technical Field

[0001] This disclosure relates to a power transmission technology, and more particularly to a power transmission device and a power transmission system. Background Technology

[0002] In the field of high-speed analog front-end design, chips need to receive a reference voltage signal in the clock domain for dynamic operation. However, in high-frequency applications, such as 5G applications, the reference voltage signal is prone to noise, resulting in poor dynamic performance of the chip. Therefore, developing technologies to overcome these problems is an important issue in this field. Summary of the Invention

[0003] This invention includes a power transmission device. The power transmission device includes a substrate, a first wafer, a first bump, a second bump, and a first capacitor. The first wafer is used to receive a first reference voltage signal and a second reference voltage signal. The first bump is located between the substrate and the first wafer and is used to transmit the first reference voltage signal from the substrate to the first wafer. The second bump is located between the substrate and the first wafer and is used to transmit the second reference voltage signal from the substrate to the first wafer. The first capacitor is located on the substrate and below the first wafer, with a first terminal coupled to the first bump and a second terminal coupled to the second bump.

[0004] In some embodiments, the power transmission device further includes: a third bump located between the substrate and the first wafer, used to transmit a third reference voltage signal corresponding to the first reference voltage signal from the substrate to the first wafer; and a second capacitor located on the substrate and below the first wafer, a first end of the second capacitor being coupled to the third bump, wherein the second capacitor is different from the first capacitor.

[0005] In some embodiments, the power transmission device further includes: a fourth bump located between the substrate and the first wafer, for transmitting a second reference voltage signal from the substrate to the first wafer, wherein a second end of the second capacitor is coupled to the fourth bump.

[0006] In some embodiments, the power transmission device further includes: an interposer layer located between the first wafer and the first bump, for transmitting a first reference voltage signal from the first bump to the first wafer; and a second capacitor located in the interposer layer, a first end of the first capacitor being coupled to the first bump, and a second end of the first capacitor being coupled to the second bump.

[0007] In some embodiments, the power delivery device further includes: a second chip located on an interposer, coupled to the first chip via the interposer, and used to operate according to a first reference voltage signal and a second reference voltage signal.

[0008] In some embodiments, the power transmission device further includes: a second capacitor located below and adjacent to the substrate, a first end of the second capacitor being coupled to a first bump, and a second end of the second capacitor being coupled to a second bump.

[0009] This invention includes a power delivery system. The power delivery system includes a power supply and a power delivery device. The power supply provides a first reference voltage signal and a second reference voltage signal. The power delivery device includes a printed circuit board, a first wafer, a first bump, a second bump, a substrate, and a first capacitor. The printed circuit board receives the first reference voltage signal and the second reference voltage signal. The first wafer receives a third reference voltage signal corresponding to the first reference voltage signal and a fourth reference voltage signal corresponding to the second reference voltage signal. The first bump is located between the substrate and the first wafer. The second bump is located between the substrate and the first wafer. The substrate is located between the printed circuit board and the first bump, and is used to transmit the third voltage signal to the first bump and to transmit the fourth voltage signal to the second bump. The first capacitor is located on the substrate and below the first wafer, with a first terminal coupled to the first bump and a second terminal coupled to the second bump.

[0010] In some embodiments, the first chip includes: a first analog-to-digital converter coupled to a first capacitor and configured to operate according to a third reference voltage signal and a fourth reference voltage signal; and a first digital-to-analog converter coupled to a second capacitor and configured to operate according to a fourth reference voltage signal and a fifth reference voltage signal, wherein the second capacitor is different from the first capacitor and the fifth reference voltage signal is different from the third reference voltage signal.

[0011] In some embodiments, the power delivery system further includes: an antenna for transmitting a radio frequency signal to a first analog-to-digital converter, wherein a frequency of the radio frequency signal is greater than one gigahertz.

[0012] In some embodiments, the power delivery system further includes: a plurality of first capacitors disposed on a substrate; and a plurality of second capacitors disposed on a substrate; wherein the first chip includes: a plurality of analog-to-digital converters, each analog-to-digital converter being coupled to a first capacitor; and a plurality of digital-to-analog converters, each digital-to-analog converter being coupled to a second capacitor, wherein the distance between each of the first capacitors and the second capacitors and the first chip is less than or approximately equal to 1,400 micrometers. Attached Figure Description

[0013] Figure 1This is a schematic diagram of a power transmission system according to an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of a power transmission system according to an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of a power transmission device according to an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of a power transmission device according to an embodiment of the present invention;

[0017] Figure 5 This is a top view of a power transmission system according to an embodiment of the present invention;

[0018] Figure 6 This is a top view of a power transmission system according to an embodiment of the present invention.

[0019] [Symbol Explanation]

[0020] 100, 200, 500, 600: Power transmission system

[0021] 110, 210, 300, 400: Power transmission devices

[0022] 120, 220, VRM1, VRM2: Power supplies

[0023] VDR, VSR, VD0~VD8, VS0, VS1: Reference voltage signals

[0024] 112, 212, 310, 410, 510, 610: Printed Circuit Boards

[0025] 114, 214: Noise suppression circuits

[0026] 116, 216, 330, 430, 440, 530, 630: Chips

[0027] TL31~TL34, TL41~TL46, TL51~TL54: Transmission lines

[0028] 218, 320, 420, 520, 620: base plate

[0029] BP21~BP25, BP31~BP34, BP41, BP42, PB41, PB42: Bumps

[0030] BL21, BL22, BL31, BL32, BL41, BL42: Passing Ball

[0031] C21~C25, C31~C33, C41~C43, C51, C52, C61~C68: Capacitors

[0032] X, Y, Z: Direction

[0033] SF31, SF32, SF41~SF43: Surface

[0034] 450: Intermediary layer

[0035] BG41, BG42: Bump Groups

[0036] LG41: Transmission line assembly

[0037] ADC0~ADC3: Analog-to-Digital Converters

[0038] DAC0~DAC3: Digital-to-Analog Converters

[0039] RX1, TX1: Antenna

[0040] RF1, RF2: Radio frequency signals Detailed Implementation

[0041] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the scope of this application.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this case pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context and this case, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0044] The following describes several embodiments of this invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the invention. That is, these practical details are not essential in some embodiments disclosed herein. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0045] Figure 1 This is a schematic diagram illustrating a power delivery system 100 according to an embodiment of this invention. Figure 1 As shown, the power delivery system 100 includes a power delivery device 110 and a power supply 120. In some embodiments, the power supply 120 is used to provide reference voltage signals VDR and VSR to the power delivery device 110.

[0046] In some embodiments, the power delivery device 110 includes a printed circuit board 112, noise immunity circuitry 114, and a chip 116. For example... Figure 1 As shown, printed circuit board 112 is coupled to power supply 120 and noise suppression circuit 114. Noise suppression circuit 114 is coupled to printed circuit board 112 and chip 116. In some embodiments, chip 116 may be implemented as a die.

[0047] In some embodiments, the printed circuit board 112 is configured to output a reference voltage signal VD0 based on a reference voltage signal VDR, and to output a reference voltage signal VS0 based on a reference voltage signal VSR. In some embodiments, the noise reduction circuit 114 is configured to output reference voltage signals VD1~VD4 based on the reference voltage signal VD0, and to output a reference voltage signal VS1 based on the reference voltage signal VS0, and to reduce noise in the reference voltage signals VD1~VD4 and VS1. In some embodiments, the chip 116 is configured to operate based on the reference voltage signals VD1~VD4 and VS1. In some embodiments, the voltage levels of the reference voltage signals VDR and VD0~VD4 are approximately 0.9 volts, and the voltage levels of the reference voltage signals VSR, VS0, and VS1 are approximately 0 volts.

[0048] Figure 2 This is a schematic diagram illustrating a power transmission system 200 according to an embodiment of this invention. Figure 2 As shown, the power transmission system 200 includes a power transmission device 210 and a power supply 220. In some embodiments, the power supply 220 is used to provide reference voltage signals VDR and VSR to the power transmission device 210 via transmission lines TL21 and TL22, respectively.

[0049] like Figure 2 As shown, the power transmission device 210 includes a printed circuit board 212, a noise suppression circuit 214, a chip 216, a substrate 218, bumps BP21~BP25, and conductive balls BL21, BL22. Please refer to... Figure 1 and Figure 2 The power delivery system 200 is one embodiment of the power delivery system 100. The power supply 220, printed circuit board 212, noise suppression circuit 214, and chip 216 correspond to the power supply 120, printed circuit board 112, noise suppression circuit 114, and chip 116, respectively; therefore, some details will not be repeated. In some embodiments, the bumps BP21~BP25 and the conductive balls BL21, BL22 can be composed of conductors, and the material of the aforementioned conductors can be gold, copper, or other metallic conductive materials.

[0050] like Figure 2 As shown, conductive balls BL21 and BL22 are located between substrate 218 and printed circuit board 212. Noise suppression circuit 214 is located above substrate 218 and below wafer 216, and adjacent to substrate 218 on surface SF21. Bumps BP21~BP25 are located between substrate 218 and wafer 216, adjacent to substrate 218 on surface SF21, and adjacent to wafer 216 on surface SF22. In some embodiments, substrate 218 is implemented as a package substrate.

[0051] exist Figure 2 In the illustrated embodiment, the right side corresponds to the X direction, the top corresponds to the Y direction, and the paper feed direction corresponds to the Z direction. In some embodiments, bumps BP21~BP25 are arranged sequentially in the X direction and are configured adjacent to the noise reduction circuit 214 in the Z direction.

[0052] In some embodiments, the printed circuit board 212 is used to output reference voltage signals VD0 and VSR based on reference voltage signals VDR and VSR. Conductive balls BL21 and BL22 are used to transmit the reference voltage signals VD0 and VSR to the substrate 218, respectively. The substrate 218 is used to generate multiple reference voltage signals based on the reference voltage signals VD0 and VSR, for example... Figure 1 The reference voltage signals VD1~VD4 and VS1 are shown. Bumps BP21~BP25 are used to transmit the above-mentioned reference voltage signals to the chip 216. For example, bumps BP21~BP24 are used to transmit reference voltage signals VD1~VD4 to the chip 216, respectively.

[0053] In some embodiments, the noise reduction circuit 214 includes capacitors C21-C25. In some embodiments, capacitors C21-C25 are respectively coupled to bumps BP21-BP25 to reduce noise in the reference voltage signals transmitted by bumps BP21-BP25. For example, in an embodiment where bumps BP21-BP24 are used to transmit reference voltage signals VD1-VD4 respectively, bumps BP21-BP4 are used to reduce noise in the reference voltage signals VD1-VD4 respectively.

[0054] In some embodiments, the power delivery device 210 further includes a capacitor C20. For example... Figure 2 As shown, capacitor C20 is located below printed circuit board 212. In some embodiments, capacitor C20 is coupled to transmission lines TL21 and TL22 to reduce noise in reference voltage signals VDR and VSR.

[0055] Figure 3 This is a schematic diagram illustrating a power transmission device 300 according to an embodiment of this invention. Figure 3 As shown, the power transmission device 300 includes a printed circuit board 310, a chip 330, a substrate 320, a capacitor C31, bumps BP31 and BP32, and conductive balls BL31 and BL32. Please refer to... Figure 2 and Figure 3The power transmission device 300 is an embodiment of the power transmission device 210. Conductive balls BL31 and BL32, printed circuit board 310, chip 330 and substrate 320 correspond to conductive balls BL21 and BL22, printed circuit board 212, chip 216 and substrate 218 respectively, capacitor C31 corresponds to noise suppression circuit 214, and bumps BP31 and BP32 correspond to two of bumps BP21 to BP25. Therefore, some details will not be repeated.

[0056] like Figure 3 As shown, conductive balls BL31 and BL32 are located between substrate 320 and printed circuit board 310. Capacitor C31 is located above substrate 320 and below chip 330, and is adjacent to substrate 320 on surface SF32. Bumps BP31 and BP32 are located between substrate 320 and chip 330, and are adjacent to substrate 320 on surface SF32, and adjacent to chip 330 on surface SF31.

[0057] exist Figure 3 In the illustrated embodiment, the right side corresponds to the Z direction, the top corresponds to the Y direction, and the paper output direction corresponds to the X direction. In some embodiments, capacitor C31 and bumps BP31 and BP32 are arranged sequentially in the Z direction.

[0058] In some embodiments, the printed circuit board 310 includes transmission lines TL31 and TL32. For example... Figure 3 As shown, transmission line TL31 is used to transmit the reference voltage signal VS0 to the conduction ball BL31, and transmission line TL32 is used to transmit the reference voltage signal VD0 to the conduction ball BL32.

[0059] In some embodiments, the substrate 320 includes transmission lines TL33 and TL34. For example... Figure 3 As shown, transmission line TL34 receives a reference voltage signal VD0 from conductive ball BL32 and outputs a reference voltage signal VD1 to bump BP32 based on the reference voltage signal VD0. Transmission line TL33 receives a reference voltage signal VS0 from conductive ball BL31 and outputs a reference voltage signal VS1 to bump BP31 based on the reference voltage signal VS0. In some embodiments, the voltage level of reference voltage signal VD1 is substantially equivalent to the voltage level of reference voltage signal VD0, and the voltage level of reference voltage signal VS1 is substantially equivalent to the voltage level of reference voltage signal VS0. In some embodiments, bumps BP31 and BP32 are used to transmit reference voltage signals VS1 and VD1 to wafer 330, respectively, so that wafer 330 operates according to reference voltage signals VS1 and VD1.

[0060] like Figure 3As shown, one end of capacitor C31 is coupled to bump BP31 via transmission line TL33, and the other end of capacitor C31 is coupled to bump BP32 via transmission line TL34. In some embodiments, capacitor C31 is used to reduce noise in reference voltage signals VD1 and VS1.

[0061] In some implementations, bumps on the substrate are used to transmit a reference voltage signal to the chip, enabling the chip to operate according to the reference voltage signal. However, the chip or the power supply providing the reference voltage signal may generate excessive simultaneous switching noise (SSN) or noise caused by inductance and current variations, resulting in poor dynamic performance of the chip.

[0062] Compared to the above approach, in this embodiment of the invention, the capacitor C31 placed on the substrate 320 is coupled to bumps BP31 and BP32 to reduce noise in the reference voltage signals VD1 and VS1, thereby enhancing the dynamic performance of the chip 330.

[0063] In some embodiments, the power transmission device 300 further includes bumps BP33 and BP34 and a capacitor C32. For example... Figure 3 As shown, capacitor C32 is located above substrate 320 and below wafer 330, adjacent to substrate 320 on surface SF32. Bumps BP33 and BP34 are located between substrate 320 and wafer 330, adjacent to substrate 320 on surface SF32 and wafer 330 on surface SF31. Bumps BP33 and BP34 and capacitor C32 are arranged adjacent to bump BP32 in the Z direction and are sequentially arranged along the Z direction.

[0064] like Figure 3 As shown, bump BP33 is coupled to conductive ball BL32 via transmission line TL34, and bump BP34 is coupled to conductive ball BL31 via transmission line TL33. In some embodiments, transmission line TL33 is used to receive a reference voltage signal VS0 from conductive ball BL31 and output a reference voltage signal VS1 to bump BP34 based on the reference voltage signal VS0. Transmission line TL34 is used to receive a reference voltage signal VD0 from conductive ball BL32 and output a reference voltage signal VD2 to bump BP33 based on the reference voltage signal VD0. In some embodiments, the voltage level of reference voltage signal VD2 is substantially equivalent to the voltage level of reference voltage signal VD0.

[0065] like Figure 3As shown, one end of capacitor C32 is coupled to bump BP34 via transmission line TL33, and the other end of capacitor C32 is coupled to bump BP33 via transmission line TL34. In some embodiments, capacitor C32 is used to reduce noise in reference voltage signals VD2 and VS1.

[0066] like Figure 3 As shown, the distance between capacitor C32 and bump BP33 is less than the distance between capacitor C31 and bump BP33, and the distance between capacitor C31 and bump BP32 is less than the distance between capacitor C32 and bump BP32. Each of capacitors C32 and C31 is used to reduce the noise of the closer corresponding one of bumps BP32 and BP33. In some embodiments, the distance between capacitor C31 and bump BP32 is less than or approximately equal to 1400 micrometers, and the distance between capacitor C32 and bump BP33 is less than or approximately equal to 1400 micrometers.

[0067] In some implementations, the capacitor is located far from the bumps on the substrate, and multiple bumps share a single capacitor, resulting in poor noise reduction.

[0068] Compared to the above approach, in this embodiment of the invention, capacitor C31 is placed on the substrate 320 closer to bump BP32 to reduce noise in the reference voltage signal VD1 of bump BP32. Capacitor C32 is placed on the substrate 320 closer to bump BP33 to reduce noise in the reference voltage signal VD2 of bump BP33. Each of bumps BP32 and BP33 reduces noise through the corresponding capacitor C31 and C32 that is closer to it, resulting in a better noise reduction effect.

[0069] In some embodiments, the power delivery device 300 further includes a capacitor C33. For example... Figure 3 As shown, capacitor C33 is located below printed circuit board 310 and is coupled to transmission lines TL31 and TL32 to reduce noise in reference voltage signals VD0 and VSO.

[0070] Figure 4 This is a schematic diagram illustrating a power transmission device 400 according to an embodiment of this invention. Figure 4 As shown, the power transmission device 400 includes a printed circuit board 410, chips 430 and 440, a substrate 420, an interposer 450, capacitors C41-C43, bumps BP41, BP42, PB41, PB42, bump assemblies BG41 and BG42, and conductive balls BL41 and BL42. Please refer to... Figure 3 and Figure 4The power transmission device 400 is a variation of the power transmission device 300. The conductive balls BL41 and BL42, the printed circuit board 410, the chip 430, the substrate 420, the capacitor C41, and the bumps BP41 and BP42 correspond to the conductive balls BL31 and BL32, the printed circuit board 310, the chip 330, the substrate 320, the capacitor C31, and the bumps BP31 and BP32, respectively. Therefore, some details will not be repeated.

[0071] like Figure 4 As shown, conductive balls BL41 and BL42 are located between substrate 420 and printed circuit board 410, and are adjacent to substrate 420 on surface SF43. Capacitor C41 is located above substrate 420 and below interposer 450, and is adjacent to substrate 420 on surface SF41. Bumps BP41 and BP42 are located between substrate 420 and interposer 450, and are adjacent to substrate 420 on surface SF41 and interposer 450 on surface SF42. Capacitor C42 is located below substrate 420 and is adjacent to substrate 420 on surface SF43. Capacitor C43 is located in interposer 450 and is adjacent to surface SF42. Bumps PB41, PB42 and bump group BG41 are located between wafer 430 and interposer 450. The bump group BG42 is located between the wafer 440 and the interposer 450.

[0072] exist Figure 4 In the illustrated embodiments, the right side corresponds to the Z direction, the top corresponds to the Y direction, and the paper output direction corresponds to the X direction. In some embodiments, on surface SF41, capacitor C41 and bumps BP41 and BP42 are arranged sequentially in the Z direction. In some embodiments, on surface SF43, capacitor C42 and bump conductive balls BL41 and BL42 are arranged sequentially in the Z direction.

[0073] In some embodiments, the printed circuit board 410 includes transmission lines TL41 and TL42. For example... Figure 4 As shown, transmission line TL41 is used to transmit the reference voltage signal VS0 to the conduction ball BL41, and transmission line TL42 is used to transmit the reference voltage signal VD0 to the conduction ball BL42.

[0074] In some embodiments, the substrate 420 includes transmission lines TL43 and TL44. For example... Figure 4 As shown, transmission line TL44 receives reference voltage signal VD0 from conductive ball BL42 and outputs reference voltage signal VD1 to bump BP42 based on reference voltage signal VD0. Transmission line TL43 receives reference voltage signal VS0 from conductive ball BL41 and outputs reference voltage signal VS1 to bump BP41 based on reference voltage signal VS0.

[0075] In some embodiments, the intermediary layer 450 includes transmission lines TL45 and TL46. For example... Figure 4 As shown, transmission line TL45 is coupled to bumps BP41 and PB41, and transmission line TL46 is coupled to bumps BP42 and PB42. In some embodiments, transmission line TL45 is used to transmit a reference voltage signal VS1 from bump BP41 to bump PB41, and transmission line TL46 is used to transmit a reference voltage signal VD1 from bump BP42 to bump PB42.

[0076] like Figure 4 As shown, one end of capacitor C41 is coupled to bump BP41 via transmission line TL43, and the other end of capacitor C41 is coupled to bump BP42 via transmission line TL44. One end of capacitor C42 is coupled to bump BP41 via transmission line TL43, and the other end of capacitor C42 is coupled to bump BP42 via transmission line TL44. One end of capacitor C43 is coupled to transmission line TL45 and bump BP41, and the other end of capacitor C43 is coupled to transmission line TL46 and bump BP42. In some embodiments, capacitors C41-C43 are used to reduce noise in reference voltage signals VD1 and VS1. In some embodiments, the distance between each of capacitors C41-C43 and bumps BP41 and BP42 is less than or approximately equal to 1400 micrometers. In some embodiments, capacitor C43 can be implemented as a deep trench capacitor (DTC).

[0077] In some embodiments, the intermediary layer 450 further includes a transmission line group LG41. For example... Figure 4 As shown, transmission line group LG41 is coupled to bump groups BG41 and BG42. In some embodiments, transmission line group LG41 and bump groups BG41 and BG42 are used to transmit reference voltage signals VD1 and VS1 from wafer 430 to wafer 440, so that wafer 440 operates according to reference voltage signals VD1 and VS1.

[0078] Figure 5 This is a top view of a power transmission system 500 according to an embodiment of this invention. Figure 5 As shown, the power delivery system 500 includes a printed circuit board 510, a substrate 520, a chip 530, and capacitors C51 and C52. The substrate 520 is placed on the printed circuit board 510. The chip 530 and capacitors C51 and C52 are placed on the substrate 520.

[0079] Please refer to Figure 5 and Figure 2The power delivery system 500 is one embodiment of the power delivery system 200. The printed circuit board 510, the substrate 520 and the chip 530 correspond to the printed circuit board 212, the substrate 218 and the chip 216 respectively, and the capacitors C51 and C52 correspond to the noise suppression circuit 214. Therefore, some details will not be repeated.

[0080] Please refer to Figure 5 and Figure 3 The printed circuit board 510, substrate 520, and chip 530 can be implemented as printed circuit board 310, substrate 320, and chip 330, and capacitors C51 and C52 can be implemented as capacitors C31 and C32. Therefore, some details will not be repeated. In some embodiments, the printed circuit board 510 is coupled to the substrate 520 through conductive balls BL31 and BL32, and the substrate 520 is coupled to the chip 530 through bumps BP31 to BP34.

[0081] In some embodiments, the power transmission system 500 further includes power supplies VRM1 and VRM2 and transmission lines TL51-TL54. Power supply VRM1 is used to provide a reference voltage signal through transmission lines TL51 and TL52, for example... Figure 3 The reference voltage signals VD1 and VS1 shown are sent to chip 530, and power supply VRM2 is used to provide the reference voltage signals through transmission lines TL53 and TL54, for example... Figure 3 The reference voltage signals VD2 and VS1 shown are sent to chip 530. Figure 5 In the illustrated embodiment, power supplies VRM1 and VRM2 are mounted on printed circuit board 510. In various embodiments, power supplies VRM1 and VRM2 may also be placed in other locations. In some embodiments, power supplies VRM1 and VRM2 may be implemented as voltage regulator modules.

[0082] like Figure 5 As shown, one end of capacitor C51 is coupled to transmission line TL51, and the other end of capacitor C51 is coupled to transmission line TL52. One end of capacitor C52 is coupled to transmission line TL53, and the other end of capacitor C52 is coupled to transmission line TL54. In some embodiments, the distance between each of capacitors C51 and C52 and the wafer 530 is less than or approximately equal to 1,400 micrometers.

[0083] Please refer to Figure 3 and Figure 5In some embodiments, capacitor C51 can be implemented as capacitors C31 and C32, transmission line TL51 can be implemented as transmission line TL34, and transmission line TL52 can be implemented as transmission line TL33.

[0084] In some embodiments, power supply VRM1 generates reference voltage signals VS0 and VD0, transmission line TL52 outputs reference voltage signal VS1 based on reference voltage signal VS0, and transmission line TL51 outputs reference voltage signal VD1 based on reference voltage signal VD0. In some embodiments, power supply VRM2 generates reference voltage signals VS0 and VD0, transmission line TL54 outputs reference voltage signal VS1 based on reference voltage signal VS0, and transmission line TL53 outputs reference voltage signal VD2 based on reference voltage signal VD0.

[0085] In some embodiments, chip 530 includes an analog-to-digital converter (ADC0) and a digital-to-analog converter (DAC0). For example... Figure 5 As shown, the analog-to-digital converter ADC0 is coupled to transmission lines TL51 and TL52 to receive a reference voltage signal, for example... Figure 3 The reference voltage signals VD1 and VS1 are shown. The digital-to-analog converter DAC0 is coupled to transmission lines TL53 and TL54 to receive the reference voltage signals, for example... Figure 3 The reference voltage signals VD2 and VS1 are shown. In some embodiments, the analog-to-digital converter ADC0 operates based on the reference voltage signals VD1 and VS1, and the digital-to-analog converter DAC0 operates based on the reference voltage signals VD2 and VS1. In some other embodiments, the analog-to-digital converter ADC0 may also operate based on the reference voltage signal VD2, and the digital-to-analog converter DAC0 may also operate based on the reference voltage signal VD1.

[0086] In some embodiments, the power delivery system 500 further includes antennas RX1 and TX1. For example... Figure 5 As shown, antenna RX1 is used to transmit radio frequency signal RF1 to analog-to-digital converter ADC0. Antenna TX1 is used to receive radio frequency signal RF2 from digital-to-analog converter DAC0. In some embodiments, the frequencies of radio frequency signals RF1 and RF2 are greater than or approximately equal to one gigahertz (GHz).

[0087] In some practices, when the chip receives high-frequency signals, such as radio frequency signals with a frequency greater than or approximately equal to one gigahertz, the reference voltage signal received by the chip is prone to noise.

[0088] Compared to the above approach, in this embodiment of the invention, when the digital converter ADC0 receives the radio frequency signal RF1, the capacitor C51 coupled to the digital converter ADC0 can reduce the noise of the reference voltage signal received by the digital converter ADC0.

[0089] exist Figure 5 In the illustrated embodiment, power supplies VRM1, VRM2 and antennas RX1, TX1 are mounted on printed circuit board 510. In various embodiments, power supplies VRM1, VRM2 and antennas RX1, TX1 may also be mounted in other locations.

[0090] Figure 6 This is a top view of a power transmission system 600 according to an embodiment of this invention. Figure 6 As shown, the power delivery system 600 includes a printed circuit board 610, a substrate 620, a chip 630, and capacitors C61 to C68. The substrate 620 is placed on the printed circuit board 610. The chip 630 and capacitors C61 to C68 are placed on the substrate 620.

[0091] Please refer to Figure 5 and Figure 6 The power delivery system 600 is a variation of the power delivery system 500. The printed circuit board 610, the substrate 620, and the chip 630 correspond to the printed circuit board 510, the substrate 520, and the chip 530, respectively. The operation of capacitors C61 to C68 is similar to that of capacitors C51 and C52, so some details will not be repeated.

[0092] In some embodiments, chip 630 includes analog-to-digital converters ADC0~ADC3 and digital-to-analog converters DAC0~DAC3. For example... Figure 6 As shown, analog-to-digital converters ADC0-ADC3 are used to receive reference voltage signals VD1, VD3, VD5, and VD7, respectively, and digital-to-analog converters DAC0-DAC3 are used to receive reference voltage signals VD2, VD4, VD6, and VD8, respectively. Each of the analog-to-digital converters ADC0-ADC3 and the digital-to-analog converters DAC0-DAC3 is used to receive the reference voltage signal VS1. Analog-to-digital converters ADC0-ADC3 are coupled to capacitors C61-C64, and digital-to-analog converters DAC0-DAC3 are coupled to capacitors C65-C68, respectively.

[0093] like Figure 6As shown, capacitors C61 to C68 are used to receive reference voltage signals VD1 to VD8, respectively, to reduce noise in the reference voltage signals VD1 to VD8. In some embodiments, each of capacitors C61 to C68 is further used to reduce noise in the reference voltage signal VS1. In some embodiments, the distance between each of capacitors C61 to C68 and the wafer 630 is less than or approximately equal to 1,400 micrometers.

[0094] In summary, in the embodiments of the present invention, in Figure 3 In the power transmission device 300 shown, capacitor C31 placed on substrate 320 is coupled to bumps BP31 and BP32 to reduce noise in reference voltage signals VD1 and VS1, thereby improving the performance of chip 330.

[0095] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A power transmission device, characterized in that, include: One substrate; A first chip for receiving a first reference voltage signal and a second reference voltage signal from at least one power supply, and including an analog-to-digital converter and a digital-to-analog converter, wherein the at least one power supply is coupled to the analog-to-digital converter via a first transmission line and a second transmission line, and the at least one power supply is coupled to the digital-to-analog converter via a third transmission line and a fourth transmission line. A first bump is located between the substrate and the first chip, and is used to transmit the first reference voltage signal from the substrate to the first chip; A second bump is located between the substrate and the first wafer, and is used to transmit the second reference voltage signal from the substrate to the first wafer; as well as A first capacitor is located on the substrate and below the first chip. A first end of the first capacitor is coupled to the first bump, a second end of the first capacitor is coupled to the second bump, the first end of the first capacitor is coupled to the first transmission line, and the second end of the first capacitor is coupled to the second transmission line. A second capacitor, the first end of which is coupled to a third transmission line, and the second end of which is coupled to a fourth transmission line; A first antenna for transmitting a first radio frequency signal to the analog-to-digital converter; as well as A second antenna is used to receive a second radio frequency signal from the digital-to-analog converter, wherein the first antenna is different from the second antenna.

2. The power transmission device as described in claim 1, characterized in that, Also includes: A third bump is located between the substrate and the first wafer, and is used to transmit a third reference voltage signal corresponding to the first reference voltage signal from the substrate to the first wafer. The second capacitor is located on the substrate and below the first chip. A first end of the second capacitor is coupled to the third bump. The second capacitor is different from the first capacitor.

3. The power transmission device as described in claim 2, characterized in that, Also includes: A fourth bump is located between the substrate and the first wafer, and is used to transmit the second reference voltage signal from the substrate to the first wafer. One of the second terminals of the second capacitor is coupled to the fourth bump.

4. The power transmission device as described in claim 1, characterized in that, Also includes: A third capacitor is located below and adjacent to the substrate. A first end of the third capacitor is coupled to the first bump, and a second end of the third capacitor is coupled to the second bump.

5. A power transmission system, characterized in that, include: At least one power supply is used to provide a first reference voltage signal and a second reference voltage signal; A printed circuit board for receiving the first reference voltage signal and the second reference voltage signal; A first chip is configured to receive a third reference voltage signal corresponding to the first reference voltage signal and a fourth reference voltage signal corresponding to the second reference voltage signal, and includes an analog-to-digital converter and a digital-to-analog converter, wherein at least one power supply is coupled to the analog-to-digital converter via a first transmission line and a second transmission line, and the at least one power supply is coupled to the digital-to-analog converter via a third transmission line and a fourth transmission line. A first bump is located between a substrate and the first chip; A second bump is located between the substrate and the first chip; The substrate is located between the printed circuit board and the first bump, and is used to transmit the third reference voltage signal to the first bump and to transmit the fourth reference voltage signal to the second bump; as well as A first capacitor is located on the substrate and below the first chip. A first end of the first capacitor is coupled to the first bump, a second end of the first capacitor is coupled to the second bump, the first end of the first capacitor is coupled to the first transmission line, and the second end of the first capacitor is coupled to the second transmission line. A second capacitor, the first end of which is coupled to a third transmission line, and the second end of which is coupled to a fourth transmission line; A first antenna for transmitting a first radio frequency signal to the analog-to-digital converter; as well as A second antenna is used to receive a second radio frequency signal from the digital-to-analog converter, wherein the first antenna is different from the second antenna.

6. The power transmission system as described in claim 5, characterized in that, in The first analog-to-digital converter is used to operate according to the third reference voltage signal and the fourth reference voltage signal; and The first digital-to-analog converter operates based on the fourth reference voltage signal and a fifth reference voltage signal. The second capacitor is different from the first capacitor, and the fifth reference voltage signal is different from the third reference voltage signal.

7. The power transmission system as described in claim 6, characterized in that, The frequency of the first radio frequency signal is greater than one gigahertz.

8. The power transmission system as described in claim 5, characterized in that, Also includes: Multiple first capacitors are placed on the substrate; as well as Multiple second capacitors are placed on the substrate; The first chip includes: Multiple analog-to-digital converters, each of which is coupled to the first capacitor; as well as Multiple digital-to-analog converters, each coupled to one of the second capacitors, The distance between each of the first capacitors and the second capacitors and the first wafer is less than or equal to 1,400 micrometers.

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