Semiconductor device and method of forming the same

Abstract

The present disclosure provides a semiconductor device and a method of forming the same. In one aspect, a semiconductor device includes a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure disposed between the first array structure and the second array structure along a first direction, and a circuit disposed adjacent to the connection structure. The connection structure includes first and second connection regions via which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure disposed to individually expose the first conductive layers in the first array structure, and a second stepped structure disposed to individually expose the second conductive layers in the second array structure. The first and second stepped structures are disposed between the first and second connection regions along a second direction perpendicular to the first direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Background Technology

[0002] For example, high-density NAND flash memory devices can have various structures to increase the density of memory cells and lines on the chip. Three-dimensional (3D) memory devices, for instance, have been extensively explored to achieve increased memory cell density at competitive costs. To fabricate 3D memory devices, advanced word line patterning has been used, employing repeated stepped etching and hard mask finishing processes to create stepped windows for the word line contact windows that connect to the drive circuitry within the memory device. Summary of the Invention

[0003] This disclosure describes methods, systems, and techniques for managing the drive connection structure of a memory device, such as a 3D memory device, which can increase the stepped process window of the centralized word line contact window connected to the drive circuit.

[0004] One aspect of this disclosure relates to a semiconductor device comprising: a first array structure of memory cells including a first conductive layer; a second array structure of memory cells including a second conductive layer; a connection structure disposed between the first array structure and the second array structure along a first direction; and a circuit disposed adjacent to the connection structure. The connection structure includes: a first connection region through which the first conductive layer is electrically connected to the circuit; a first stepped structure disposed to individually expose the first conductive layer; a second stepped structure disposed to individually expose the second conductive layer; and a second connection region through which the second conductive layer is connected to the circuit. The first stepped structure and the second stepped structure are disposed between the first connection region and the second connection region along a second direction perpendicular to the first direction.

[0005] In some embodiments, the first and second stepped structures are adjacent to each other along a second direction. In some embodiments, the circuit includes an X-decoder.

[0006] In some embodiments, a first conductive layer is configured to be electrically connected to the circuit via a first layer contact window coupled to the first conductive layer in a first stepped structure and a first through-array contact window passing through a first connection region and coupled to the circuit, and a second conductive layer is configured to be electrically connected to the circuit via a second layer contact window coupled to the second conductive layer in a second stepped structure and a second through-array contact window passing through a second connection region and coupled to the circuit. The terms "electrical connection," "conductive connection," and "conductive coupling" are used interchangeably in this disclosure.

[0007] In some embodiments, each of the first and second contact windows is electrically connected to one of the first and second through-array contact windows via a corresponding conductive interconnect. Each of the first and second connection regions may be filled with at least one electrically insulating material.

[0008] In some embodiments, the process window covers at least a portion of the first connection region, the first stepped structure, the second stepped structure, and at least a portion of the second connection region along a second direction. Along the second direction, the length of the process window may be at least 1.5 times greater than the sum of the lengths of the first stepped structure and the second stepped structure. Along the first direction, the length of the process window may be less than at least one of the lengths of the first connection region and the second connection region.

[0009] In some cases, the length of the process window along the first direction may be greater than at least one of the lengths of the first connection region and the second connection region. In some cases, the lengths of the first connection region and the second connection region are the same. In some cases, the first and second contact windows are formed within the process window. In some cases, the first and second through-array contact windows are at least partially formed within the process window. In some cases, the first and second through-array contact windows are formed outside the process window.

[0010] In some embodiments, the connection structure further includes: a third connection region spaced apart from the first connection region along a first direction; and a fourth connection region spaced apart from the second connection region along the first direction. A first process window may cover at least a portion of the first connection region, the first stepped structure, the second stepped structure, and at least a portion of the second connection region along a second direction, and a second process window may cover at least a portion of the third connection region, the first stepped structure, the second stepped structure, and at least a portion of the fourth connection region along the second direction.

[0011] In some embodiments, the connection structure further includes: a first unprocessed structure electrically coupled to a first conductive layer in a first array structure, wherein at least a portion of the first unprocessed structure is disposed along a first direction between a first connection region and a third connection region and outside a first process window and a second process window; and a second unprocessed structure electrically coupled to a second conductive layer in a second array structure, wherein at least a portion of the second unprocessed structure is disposed along a first direction between a second connection region and a fourth connection region and outside a first process window and a second process window.

[0012] In some embodiments, another portion of the first unprocessed structure is separated from the first stepped structure along a second direction via a first connection area or a third connection area, and another portion of the second unprocessed structure is separated from the second stepped structure along a second direction via a second connection area or a fourth connection area.

[0013] In some embodiments, at least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first unprocessed conductive layer in the first unprocessed structure, a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through array contact windows.

[0014] In some embodiments, the corresponding first untreated conductive layer in the first untreated structure and the corresponding first stepped conductive layer in the first stepped structure form a single conductive layer.

[0015] In some embodiments, the corresponding first unprocessed conductive layer in the first unprocessed structure includes: a first sublayer located along a first direction in a first portion of the first unprocessed structure between a first connection region and a second connection region; and a second sublayer located along a second direction in a second portion of the first unprocessed structure separated from the first stepped structure by the first connection region and a third connection region. The first sublayer and the second sublayer form the corresponding first unprocessed conductive layer.

[0016] In some embodiments, one of the corresponding first stepped conductive layer in the first stepped structure and one of the corresponding first contact window are in one of the first process window and the second process window.

[0017] In some embodiments, at least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through-array contact windows without passing through the first untreated structure.

[0018] In some embodiments, a first conductive layer is sequentially disposed in a first array structure along a third direction perpendicular to a plane defined by a first direction and a second direction, and a second conductive layer is sequentially disposed in a second array structure along the third direction, wherein the nth first conductive layer in the first array structure and the nth second conductive layer in the second array structure are electrically connected to the same conductive pad in the circuit, where n is an integer.

[0019] Another aspect of this disclosure relates to a semiconductor device comprising: a first array structure of memory cells including a first conductive layer; a second array structure of memory cells including a second conductive layer; a connection structure disposed between the first array structure and the second array structure along a first direction; and a circuit disposed adjacent to the connection structure. The connection structure comprises: a first stepped structure configured to individually expose the first conductive layer; a first unprocessed structure electrically coupled to the first conductive layer in the first array structure; a first connection region through which the first conductive layer is electrically connected to the circuit, the first connection region being disposed between the first stepped structure and the first unprocessed structure along a second direction perpendicular to the first direction; a second stepped structure configured to individually expose the second conductive layer; a second unprocessed structure electrically coupled to the second conductive layer in the second array structure; and a second connection region through which the second conductive layer is electrically connected to the circuit, the second connection region being disposed between the second stepped structure and the second unprocessed structure along a second direction.

[0020] In some embodiments, the first stepped structure and the second stepped structure are adjacent to each other and disposed between the first connection area and the second connection area along the second direction.

[0021] In some embodiments, the first conductive layer is configured to be electrically connected to the circuit via a first layer contact window coupled to the first conductive layer in the first stepped structure and a first through-array contact window passing through the first connection area and coupled to the circuit.

[0022] In some embodiments, at least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first unprocessed conductive layer in the first unprocessed structure, a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through array contact windows.

[0023] In some embodiments, the second conductive layer is configured to be electrically connected to the circuit via a second layer contact window coupled to the second conductive layer in the second stepped structure and a second through-array contact window passing through the second connection area and coupled to the circuit.

[0024] In some embodiments, at least one of the second conductive layers in the second array structure is electrically connected to the circuit via a corresponding second untreated conductive layer in the second untreated structure, a corresponding second stepped conductive layer in the second stepped structure, a corresponding one of the second layer contact windows, and a corresponding one of the second through array contact windows.

[0025] In some embodiments, the connection structure further includes: a third connection region spaced apart from the first connection region along a first direction; and a fourth connection region spaced apart from the second connection region along the first direction. In some embodiments, a first process window covers at least a portion of the first connection region, the first stepped structure, the second stepped structure, and at least a portion of the second connection region along a second direction, and a second process window covers at least a portion of the third connection region, the first stepped structure, the second stepped structure, and at least a portion of the fourth connection region along the second direction.

[0026] In some embodiments, the first unprocessed structure includes: a first portion located along a first direction between the first connection region and the third connection region and outside the first process window and the second process window; and a second portion separated from the first stepped structure along a second direction through the first connection region and the third connection region.

[0027] In some embodiments, the second unprocessed structure includes: a third portion located along a first direction between the second connection region and the fourth connection region and outside the first process window and the second process window; and a fourth portion separated from the second stepped structure along a second direction through the second connection region and the fourth connection region.

[0028] Another aspect of this disclosure relates to a method of forming a semiconductor device, the method comprising: forming a memory cell array including a conductive layer; separating the memory cell array along a first direction into a first array structure including a first conductive layer, a second array structure including a second conductive layer, and a connection structure between the first array structure and the second array structure; forming a first through-array contact window passing through a first connection region to electrically connect to a circuit adjacent to the connection structure, and forming a second through-array contact window passing through a second connection region to electrically connect to the circuit, wherein the first connection region and the second connection region are separated along a second direction perpendicular to the first direction; and forming a first stepped structure and a second stepped structure in a process window, wherein the first stepped structure and the second stepped structure are adjacent to each other along the second direction, wherein the process window covers at least a portion of the first connection region, the first stepped structure, the second stepped structure, and at least a portion of the second connection region, and wherein the first stepped structure and the second stepped structure are along the second direction between the first connection region and the second connection region.

[0029] In some embodiments, the method further includes: forming a first contact window along a third direction perpendicular to a plane defined by a first direction and a second direction, coupled to a first conductive layer in a first stepped structure; and forming a second contact window along a third direction, coupled to a second conductive layer in a second stepped structure; and forming corresponding conductive interconnects to connect the first contact window and the second contact window to a first through-array contact window and a second through-array contact window.

[0030] The techniques implemented in this disclosure improve word line resistance-capacitance (RC) characteristics by concentrating word line contact windows for driving interconnect circuitry (e.g., X-decoders). The techniques can enlarge the stepped process window of the concentrated word line (WL) contact windows by adjusting (or reconfiguring) the position of the unprocessed structure and / or interconnect region (e.g., by moving the interconnect region between the unprocessed structure and the stepped structure). The boundary of the stepped process window can be within the interconnect region to increase the process window of the WL contact window and the minimal incremental layer cost (MiLC) process. The enlarged process window avoids smaller wedge profiles that could affect the word line contact window bonding area. Without additional shielding requirements, the techniques can select identical segments from adjacent memory array structures (e.g., along the Z direction) and maintain the feasibility of simple word line drive routes due to the concentrated WL contact windows. The techniques also achieve good pattern uniformity and a low aspect ratio for deep etching processes.

[0031] The techniques implemented in this disclosure can be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices, such as 2-level cell devices, triple-level cell (TLC) devices, or quad-level cell (QLC) devices. The techniques can be applied to various sizes of memory devices or systems, such as three-dimensional (3D) memory devices or systems.

[0032] Details of one or more of the disclosed embodiments are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and the scope of the claims. Attached Figure Description

[0033] Figure 1A An example of a system containing a memory device is shown.

[0034] Figure 1B This shows an instance block of a two-dimensional (2D) memory.

[0035] Figure 1C This shows an instance block of a three-dimensional (3D) memory.

[0036] Figure 2 An example 3D memory device is shown with a stepped region for driving connections.

[0037] Figures 3A to 3GAn example 3D memory device is shown, featuring a central stepped region with enlarged process windows positioned between memory cell array structures.

[0038] Figures 4A to 4B Other examples of process windows showing the central stepped area in a 3D memory device are shown.

[0039] Figure 5 A flowchart illustrating an example of a process for forming a drive connection structure for a 3D memory device.

[0040] The same reference numerals and labels in the accompanying drawings indicate the same elements. It should also be understood that the various illustrative embodiments shown in the drawings are for illustrative purposes only and are not necessarily drawn to scale.

[0041] Explanation of reference numerals in the attached figures

[0042] 100: System

[0043] 110: Device

[0044] 112: Device controller

[0045] 113: Processor

[0046] 114: Internal Memory

[0047] 116: Memory

[0048] 120: Main unit

[0049] 140: 2D memory block

[0050] 141, 157, 301: Memory cells

[0051] 142, 152: Unit Pages

[0052] 143: SST

[0053] 144, 154: Serial string

[0054] 145: GST

[0055] 146, 156, 214: SSL

[0056] 148, 158: GSL

[0057] 149, 159: CSL

[0058] 150: 3D Memory Block

[0059] 200: 3D Memory Device

[0060] 202: CuA layer

[0061] 210: Memory array region

[0062] 211: Conductive layer / Word line / Word line layer

[0063] 212: VC

[0064] 213: Insulation layer

[0065] 215: Through hole

[0066] 216, BL0, BL1, BL n-1 BL n Bit line

[0067] 220: Stepped area

[0068] 222, 318: TAC

[0069] 223: Conductive internal wiring

[0070] 224, 316: WL_COA

[0071] 226: Next District

[0072] 228: Insulating materials

[0073] 300: Memory Block

[0074] 302: Left-side array structure

[0075] 303-L, 303-R: Conductive contact window area

[0076] 304: Right-side array structure

[0077] 305: SSL Cutout

[0078] 306: Conductive contact window

[0079] 308: Contact gasket

[0080] 309, 309C1, 309C2, 309C3, 323, 325: Conductive slits

[0081] 309A, 309D: Intermediate conductive slit

[0082] 309B: Bottom conductive slit

[0083] 309C: Central conductive slit

[0084] 309T: Top conductive slit

[0085] 310: Central stepped area

[0086] 310-L: Part 1

[0087] 310-R: Part Two

[0088] 311: Dielectric layer

[0089] 312-L1: First Connection Area

[0090] 312-L2: Third Connection Area

[0091] 312-R1: Second Connection Area

[0092] 312-R2: Fourth Connection Area

[0093] 313-L1, 313-R1: The first letter line connects to the padding area.

[0094] 313-L2, 313-R2: The second letter line connects to the padding area.

[0095] 314, 314-L, 314-R, 420, 430, 460, 470: Process windows

[0096] 315: Boundary

[0097] 320: First Unprocessed Structure

[0098] 322: Third Unprocessed Structure

[0099] 324: Fourth Unprocessed Structure

[0100] 326: Second Unprocessed Structure

[0101] 326-1: Zone 1

[0102] 326-2: Second District

[0103] 330: Cross-sectional view Y1-Y1′

[0104] 332, 365: Conductive layer

[0105] 333: First insulating layer

[0106] 334: Second insulating layer

[0107] 340: Cross-sectional view Y2-Y2′

[0108] 350: Top View

[0109] 351, 353: Traces

[0110] 360°: Cross-sectional view X1-X1′

[0111] 361, 363: Stepped structure

[0112] 362, 364: Process openings

[0113] 370: Cross-sectional view X2-X2′

[0114] 380: Cross-sectional view X3-X3′

[0115] 381: Depressed area

[0116] 382: Flattened protrusion

[0117] 400, 450: Examples

[0118] 402: Unprocessed structure on the left side

[0119] 404, 414, 434, 444: Connection areas

[0120] 406: Left-side stepped structure

[0121] 410: Central stepped area

[0122] 412: Unprocessed structure on the right side

[0123] 416: Stepped structure on the right side

[0124] 500: Process

[0125] 502, 504, 506, 508: Steps

[0126] WL0, WL1, WL n-1 WL n : Word line

[0127] X1-X1′, X2-X2′, X3-X3′: Tangents Detailed Implementation

[0128] Figure 1A An example of system 100 is shown. System 100 includes device 110 and host device 120. Device 110 includes device controller 112 and memory 116. Device controller 112 includes processor 113 and internal memory 114. In some embodiments, device 110 includes a plurality of memories 116 coupled to device controller 112.

[0129] In some embodiments, device 110 is a storage device. For example, device 110 may be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid-state drive (SSD), or some other suitable storage device. In some embodiments, device 110 is a smartwatch, a digital camera, or a media player. In some embodiments, device 110 is a user device coupled to host device 120. For example, device 110 is an SD card in a digital camera or media player, which is host device 120.

[0130] Device controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some embodiments, device controller 112 is a memory controller of device 110. The following sections describe various techniques based on embodiments where device controller 112 is a memory controller. However, the techniques described in the following sections are also applicable to embodiments where device controller 112 is a controller of a different type than a memory controller.

[0131] Processor 113 is configured to execute instructions and process data. Instructions include firmware instructions and / or other program instructions stored as firmware code and / or other program code in auxiliary memory. Data includes program data corresponding to the firmware and / or other programs executed by the processor, as well as other suitable data. In some embodiments, processor 113 is a general-purpose microprocessor or an application-specific microcontroller. Processor 113 is also referred to as a central processing unit (CPU).

[0132] Processor 113 accesses instructions and data from internal memory 114. In some embodiments, internal memory 114 is static random access memory (SRAM) or dynamic random access memory (DRAM). For example, in some embodiments, when device 110 is an eMMC, SD card, or smartwatch, internal memory 114 is SRAM. In some embodiments, when device 110 is a digital camera or media player, internal memory 114 is DRAM.

[0133] In some embodiments, the internal memory is a cache memory included in the device controller 112, such as... Figure 1A As shown in the diagram. Internal memory 114 stores instruction codes corresponding to instructions executed by processor 113, and / or data requested by processor 113 during runtime.

[0134] Device controller 112 transmits instruction codes and / or data from memory 116 to internal memory 114. Memory 116 may be a semiconductor device. In some embodiments, memory 116 is a non-volatile memory configured for long-term storage of instructions and / or data, such as a NAND flash memory device or some other suitable non-volatile memory device. In embodiments where memory 116 is NAND flash memory, device 110 is a flash memory device, such as a flash memory card, and device controller 112 is a NAND flash controller. For example, in some embodiments, when device 110 is an eMMC or SD card, memory 116 is NAND flash; in some embodiments, when device 110 is a digital camera, memory 116 is an SD card; and in some embodiments, when device 110 is a media player, memory 116 is a hard disk drive.

[0135] The memory 116 contains multiple blocks. The memory 116 may be a two-dimensional (2D) memory containing 2D memory blocks. The memory 116 may also be a three-dimensional (3D) memory containing 3D memory blocks.

[0136] Figure 1B This illustration shows an example configuration of a 2D memory block 140 when memory 116 is a 2D memory. Block 140 includes memory cells 141, which are connected in series to row bit lines BL0, BL1, ..., BL2. n-1 and line BL n To form multiple unit strings 144, and coupled to column word lines WL0, WL1, ..., WL n-1 and column line WL n To form multiple unit pages 142.

[0137] Each memory cell in the block comprises a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at the intersection of a word line and a bit line, wherein the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to a source line, which in turn is connected to a common ground. In some instances, the gate of the flash memory cell has a dual-gate structure, comprising a control gate and a floating gate, wherein the floating gate is suspended between two oxide layers to trap electrons programming the cell.

[0138] String 144 may include multiple memory cells 141 connected in series, a source select transistor (SST) 143, and a ground select transistor (GST) 145. The gate of SST 143 is connected to a string select line (SSL) 146. The gates of SST 143 in different strings are also connected to the same SSL. The gates of memory cells 141 are respectively connected to word lines WL0, WL1, ..., WL n-1 、Word line WL n Cell string 144 or memory cell 141 is connected to common source line (CSL) 149 via GST 145. CSL 149 may be coupled to ground. The gate of GST 145 is connected to ground select line (GSL) 148. The gates of GST 145 in different strings 144 are also connected to the same GSL 148.

[0139] Page 142 may contain multiple memory cells 141. The gates of the memory cells 141 in page 142 are connected in series to individual word lines (WL). When an input voltage is applied to a word line, an input voltage is also applied to the gates of the memory cells 141 in page 142. To read a specific page 142 in block 140 during a read operation, a lower voltage is applied to the word line corresponding to that specific page 142. Simultaneously, a higher voltage is applied to the other pages in block 140.

[0140] Figure 1C This shows that when memory 116 (shown in) Figure 1A (The middle part) is an example of 3D memory, specifically 3D memory block 150. 3D memory block 150 can be... Figure 1B The stack of 2D memory blocks 140. Memory cells 157 are configured in three dimensions, for example in an XYZ coordinate system, and are coupled to multiple word lines to form multiple cell pages (conductive layers or word line layers) 152 and coupled to multiple bit lines to form multiple cell strings 154. Cell pages 152 may be, for example, layers in the XY plane, and memory cells 157 on the same layer may be coupled to a word line and have the same voltage. Each cell page 152 may be connected to a separate contact pad in a driving circuit, such as an X-decoder (or scan driver).

[0141] Cell string 154 includes a plurality of memory cells 157 connected in series vertically along the Z direction, wherein the memory cells may be coupled to a Serial Select line (SSL) 156 via an SST and to a Ground Select line (GSL) 158 via a GST. Cell string 154 is connected to one or more drivers, such as data drivers. Cell string 154 of memory cells 157 is connected to a common source line (CSL) 159 via a Ground Select transistor (GST). SSL 156 may be a conductive line or conductive layer formed on top of cell page (or word line layer) 152. Memory block 150 may include a plurality of SSL 156 on top of cell page 152. CSL 159 may be a conductive layer (or a plurality of conductive lines) formed on the substrate of 3D memory. CSL 159 may be coupled to ground.

[0142] Figure 2 A perspective view of an example 3D memory device 200 is shown. The 3D memory device 200 can be implemented as follows: Figure 1A The memory 116. The 3D memory device 200 includes a memory array region 210 and a stepped region 220, the stepped region 220 being configured to electrically connect the memory array region to a driving circuit, such as a circuit under array (CuA) layer 202. The CuA layer 202 may be formed on or in a substrate. The substrate may comprise one or any combination of silicon, doped silicon, germanium, silicon-germanium, semiconductor compounds, or other semiconductor materials.

[0143] The memory array region 210 contains multiple vertical channels (VCs) 212. Each VC 212 contains a string of memory cells, for example... Figure 1B The unit string 144 or Figure 1C The cell string 154 is coupled to the corresponding bit line (BL) 216 via the corresponding via 215. VC 212 is electrically coupled to CuA layer 202. In some embodiments, CuA layer 202 includes multiple active devices, such as transistors electrically coupled to conductive layer 211 (gate layer or word line layer) and insulated by an insulating material, and multiple conductive lines.

[0144] VC 212 extends downwards through multiple pairs of alternating conductive layers 211 (gate layer or word line layer) and an insulating layer 213. The insulating layer 213 may be made of a dielectric material such as silicon oxide (abbreviated as oxide or OX). The conductive layers 211 may be made of a conductive material such as a metal such as tungsten (W). The conductive layers may form one or more SSL 214 (e.g., Figure 1C SSL 156), one or more word lines (WL) 211 (e.g., Figure 1CWL 157) and one or more GSLs (e.g., Figure 1C (GSL 158). The outer surface of VC 212 contacts a conductive layer 211 that serves as the gate of a memory cell. VC 212 may comprise multiple layers, including a tunneling layer, a charge trapping layer, and a barrier layer. The tunneling layer may comprise silicon oxide or a silicon oxide / silicon nitride combination (e.g., oxide / nitride / oxide or ONO). The charge trapping layer may comprise silicon nitride (SiN) or other materials capable of trapping charges. The barrier layer may comprise silicon oxide, aluminum oxide, and / or a combination of such materials. Multiple layers may be formed on the inner surface of VC 212, and polysilicon may be filled in the middle of VC 212. The fill material (e.g., multiple layers and polysilicon) in each VC 212 intersecting the conductive layer 211 may form a string of memory cells along a vertical direction such as the Z direction. A bit line pad (BLP) may be formed on top of VC 212 to seal VC 212, such that the interior of VC 212 is isolated from the external environment during processing. The BLP is conductive and can be coupled to the bit line 216 via the via 215.

[0145] The stepped region 220 is configured to electrically connect the word line layer 211 to the CuA layer 202. For example... Figure 2 As shown, the stepped structure forms an extension of the memory array region 210, such that each word line layer 211 can be individually connected to a corresponding word line layer contact (WL_COA) 224 at the bonding region 226. The corresponding word line layer contact 224 is electrically connected to individual contact pads in the CuA layer 202 via corresponding through array contact (TAC) 222 passing through the insulating material 228 filled in the stepped region 220. The corresponding word line layer contact 224 is electrically connected to the corresponding TAC 222 via conductive interconnects 223.

[0146] like Figure 2 As shown, memory array region 210 is adjacent to step region 220. When the number of memory cells in each word line layer (e.g., along the Y direction) is large, such as more than several thousand memory cells, the word line resistance-capacitance (RC) characteristics of the word line layer can be affected. For example, memory cells farther away from step region 220 may have a slower response speed than memory cells closer to step region 220. In some embodiments, such as in Figures 3A to 3GFurther details are provided, stating that the memory array region can be divided into two or more memory array structures, and a central stepped region can be configured between two adjacent memory array structures to provide conductive connections from the word line layer to the CuA layer 202 in the two adjacent memory array structures. To simplify the drive signal path, it is particularly necessary to select the same segment from the two adjacent memory array structures (e.g., along the Z direction).

[0147] Furthermore, when the number of word line layers is large (e.g., along the Z direction), such as more than one hundred, the etching depth of the word line layer contact windows (e.g., WL_COA 224) in the stepped region becomes increasingly deeper, and if the stepped process window of the word line layer contact window is small, a wedge-shaped profile of the word line layer contact window can be observed. A smaller wedge-shaped profile can affect the adhesion of the word line layer contact windows, which can affect the performance of the conductive connection and thus the performance of the memory device.

[0148] Embodiments of this disclosure provide methods and techniques for enlarging the stepped process window to avoid a small wedge profile of the word line layer contact window used for conductive connections to driving circuitry (e.g., an X-decoder). In some embodiments, the stepped process window of the word line layer contact window is enlarged by adjusting (or reconfiguring) the position of the unprocessed structure and / or the connection area (e.g., by moving the connection area between the unprocessed structure and the stepped structure). The boundary of the stepped process window may be within the connection area to increase the process window of the WL layer contact window.

[0149] Figures 3A to 3G An example memory block 300 of a 3D memory device is shown. The 3D memory device can be implemented as... Figure 1A The memory 116, and the memory block 300 can be implemented as Figure 1C The memory block 150. The memory block 300 includes a central step region 310 disposed between two adjacent array structures of the memory cell (e.g., a left array structure 302 to the left of the central step region 310 and a right array structure 304 to the right of the central step region 310). The central step region 310 has an enlarged step process window for implementing word line layer contact windows to electrically connect the word line layers in array structures 302 and 304 to circuitry, such as an X-decoder (e.g., below the central step region 310). Figure 2 CuA layer 202).

[0150] Figure 3A This is a top view (in the XY plane) of memory block 300. Figure 3B and Figure 3CThese are cross-sectional views Y1-Y1′330 and Y2-Y2′340 (in the XZ plane), respectively. The left array structure 302, the central stepped region 310, and the right array structure 304 are sequentially arranged along a first direction (e.g., the Y direction). Each of the array structures 302 and 304 includes, for example, multiple alternating conductive layer pairs (e.g., ...). Figure 2 The conductive layer 211) and the insulating layer (e.g., Figure 2 Insulating layer 213) creates vertical channels (such as Figure 2 Multiple memory cells 301 are formed by VC 212. Array structures 302 and 304 are independently controlled to perform operations (e.g., read, write, and erase), and array structures 302 and 304 can be regarded as separate blocks.

[0151] The memory block 300 can be separated into different units by conductive slits 309, which include a top conductive slit 309T, a bottom conductive slit 309B, a center conductive slit 309C, and two intermediate conductive slits 309A and 309D. The conductive slits 309 extend in the YZ plane via the 3D memory array to a common source line (CSL) layer below the 3D memory array (e.g., ...). Figure 1C The CSL 159 (of the CSL). Each conductive slit 309 has a side surface (or wall) covered with a dielectric material (e.g., oxide) insulating from adjacent layers and an interior portion filled with a conductive material (e.g., metal). The common source line layer can be made of polysilicon, epitaxial (Epi), or metal. The conductive slit 309 can act as a source line, and adjacent source lines can be conductively coupled together via the CSL layer. Each cell is located between two adjacent conductive slits 309. Figure 3A As shown, each of the array structures 302 and 304 is separated into four units by three conductive slits 309 (e.g., conductive slits 309A, 309C, and 309D).

[0152] Memory block 300 may also include one or more string select line (SSL) cutouts 305 that divide block 300 (or cell) into different parts (e.g., sub-blocks). Figure 3A As shown, each cell is divided into two parts, and each of array structures 302 and 304 is divided into eight parts (or sub-blocks) by conductive slits 309 and SSL cutouts 305. Each SSL cutout 305 is filled with a dielectric material (e.g., oxide) and extends along the Y direction. The SSL cutout 305 also extends along the Z direction into multiple conductive layers on top of the word line layer of the 3D memory block 300, such that the multiple conductive layers act as SSL layers (e.g., ...). Figure 2(SSL 214). Each part (e.g., sub-blocks) can be controlled independently, for example, via the corresponding SSL layer.

[0153] like Figure 3A As shown, the central stepped region 310 has a first portion 310-L and a second portion 310-R configured along a second direction (e.g., the X direction) perpendicular to a first direction (e.g., the Y direction). The first portion 310-L is connected to the left array structure 302 and configured to conductively connect the word line layer in the left array structure 302 to the circuitry. The second portion 310-R is connected to the right array structure 304 and configured to conductively connect the word line layer in the right array structure 304 to the circuitry. The first portion 310-L and the second portion 310-R can be separated by a conductive slit 309C1, which can extend along a third direction (e.g., the Z direction) perpendicular to a plane (e.g., the XY plane) defined by the first direction (e.g., the Y direction) and the second direction (e.g., the X direction). Figure 3A As shown, the conductive slit 309C1 can be separated from the conductive slit 309C in the left array structure 302 and / or the right array structure 304.

[0154] In some implementations, along the Y direction, such as Figure 3A As shown, the central stepped region 310 includes conductive contact window regions 303-L and 303-R of array structures 302 and 304, respectively. In conductive contact window regions 303-L and 303-R, conductive contact windows 306 are conductively connected to the corresponding selected SSL layer (or transistor layer). Figure 3G The diagram further illustrates that the morphology along the Y direction includes flat protrusions 382 and recessed regions 381. Recessed regions 381 include alternating conductive layers 332 (e.g., a metal such as W) and insulating layers 334 (e.g., oxides). The slopes of recessed regions 381 are stepped structures. Conductive contact window regions 303-L and 303-R include stepped structures similar to the slopes of recessed regions 381. Each of the stepped structures individually exposes a conductive layer (e.g., an SSL layer or a transistor layer) in conductive contact window regions 303-L and 303-R. The morphology may also be a stepped structure.

[0155] like Figure 3AAs shown, the first portion 310-L, the conductive contact window region 303-L, and the left array structure 302 are electrically insulated from the second portion 310-R, the conductive contact window region 303-R, and the right array structure 304 by conductive slits 309T, 309C2, 309C1, 309C3, and 309B, which can be connected together. The sidewall surfaces of conductive slits 309C1, 309C2, and 309C3 are covered with a dielectric material (e.g., oxide). Both array structures 302 and 304 can be controlled or operated independently. Conductive slit 309C and adjacent parallel conductive slits 309D and 309A are not connected to conductive slits 309C2, 309C1, and 309C3. Therefore, the conductive layers 332 (SSL plane or word line plane) of adjacent sub-blocks within the same block (e.g., 304) are integrated in the following areas: 304, 303-R, 324, 326, as shown. Figure 3A As shown in the diagram. Similarly, the conductive layers 332 (SSL plane or word line plane) of adjacent sub-blocks within the same block (e.g., 302) are integrated in the following areas: 302, 303-L, 322, 320, as shown. Figure 3A As shown in the figure.

[0156] In some embodiments, the first portion 310-L includes a first connection area 312-L1, through which the word line layer in the left-side array structure 302 is electrically connected to circuitry adjacent to the first portion 310-L (e.g., below the first portion 310-L). For example, a plurality of through-array contact windows (TACs) 318 may be formed within the first connection area 312-L1 to pass through it. The TACs 318 may be connected to... Figure 2 Similar to TAC 222. Each TAC 318 is electrically connected to an individual contact pad 308 in the CuA layer (e.g., Figure 3B (As shown in the image). In some instances, such as Figure 3B As shown, the first connection region 312-L1 is insulated from the surrounding alternating conductive layers 332 (e.g., a metal such as W) and insulating layers 334 (e.g., OX) via a dielectric layer 311. The first connection region 312-L1 may include alternating pairs of first insulating layers 333 (e.g., SIN) and second insulating layers 334 (e.g., OX).

[0157] In some embodiments, the central step region 310 is initially formed by alternating pairs of first insulating layers 333 (e.g., SIN) and a second insulating layer 334. The first connection region 312-L1 can be formed by separating the first connection region 312-L1 from the surrounding region by a dielectric layer 311, followed by etching the surrounding region to remove the first insulating layer 333 and depositing a conductive material (e.g., a metal such as W) to form a conductive layer 332 during a gate replacement process. The dielectric layer 311 may be made of an electrically insulating material and configured to prevent the removal of the first insulating layer 333 in the first connection region 312-L1 during the gate replacement process. That is, no gate replacement process is performed in the first connection region 312-L1. In some embodiments, the first connection region 312-L1 can be formed by etching away the alternating pairs of first insulating layers 333 and the second insulating layer 334 and filled with an electrically insulating material (e.g., SIN or OX). Similarly, other connection regions 312-L2, 312-R1, and 312-R2 can be formed by a similar process.

[0158] The first connection region 312-L1 may be adjacent to the conductive contact window region 303-L, which is adjacent to the left array structure 302. In some instances, such as Figure 3A As shown, the first portion 310-L includes a third connection region 312-L2 similar to the first connection region 312-L1. The third connection region 312-L2 is adjacent to the conductive contact window region 303-R, which is adjacent to the right-side array structure 304. The third connection region 312-L2 and the conductive contact window region 303-R are separated by a conductive slit 309C3 along a second direction (e.g., the X direction). The third connection region 312-L2 is separated from the first connection region 312-L1 along the Y direction. The first connection region 312-L1 and the third connection region 312-L2 may have the same size, height (along the X direction), and / or width (along the Y direction). The connection regions 312-L1 and 312-L2 may be located a distance away from the conductive slit 309C1.

[0159] like Figures 3A to 3B As shown, the first portion 310-L includes a first word line bonding pad region 313-L1, which has a first stepped structure formed between the first connection region 312-L1 and the conductive slit 309C1. The first stepped structure in the first word line bonding pad region 313-L1 is configured to individually expose the conductive layer in the left-side array structure 302. Multiple word line layer contact windows (WL_COA) 316 (e.g., Figure 2The WL_COA224 is formed in the first word line bonding pad region 313-L1, which is connected to the corresponding word line bonding pad. The word line layer contact window (WL_COA) 316 can be accessed via a corresponding conductive interconnect (e.g., Figure 2 The internal interconnect 223 is electrically connected to the corresponding TAC 318 formed in the first connection region 312-L1. Each TAC 318 is electrically connected to a respective contact pad 308 in the CuA layer. In this way, the word line layer in the left array structure 302 can be electrically connected to the respective contact pads 308 in the circuit via the corresponding WL_COA 316, the corresponding conductive internal interconnect, and the corresponding TAC 318. Similarly, the first portion 310-L also includes a second word line bonding pad region 313-L2, which has another first stepped structure formed between the third connection region 312-L2 and the conductive slit 309C1. The word line layer in the left array structure 302 can be electrically connected to individual contact pads 308 in the array lower circuit via the corresponding WL_COA 316 (in the second word line connection pad area 313-L2), the corresponding conductive interconnect, and the corresponding TAC 318 (in the third connection area 312-L2).

[0160] Similarly, the second portion 310-R includes a second connection area 312-R1, through which the word line layer in the right-side array structure 304 is electrically connected to circuitry adjacent to the second portion 310-R (e.g., below the second portion 310-R). The second connection area 312-R1 may be similar to the first connection area 312-L1. The second connection area 312-R1 may be adjacent to the left-side array structure 302 and have the same length as the first connection area 312-L1 along a first direction (e.g., the Y direction). Figures 3A to 3B As shown, the second connection region 312-R1 and the first connection region 312-L1 can be arranged along a second direction (e.g., the X direction) on opposite sides of the conductive slit 309C1 (or conductive slit 309C).

[0161] Similarly, multiple through-array contact windows (TACs) 318 are formed within the second connection region 312-R1. The TACs 318 can be connected to... Figure 2 Similar to TAC 222. Each TAC 318 is electrically connected to an individual contact pad 308 in the CuA layer (e.g., Figure 3B (As shown in the diagram). The second connection region 312-R1 is insulated from the surrounding alternating conductive layer 332 and insulating layer 334 through the dielectric layer 311, as shown in the diagram. Figure 3BAs shown in the diagram. In some embodiments, similar to the first connection region 312-L1, the second connection region 312-R1 can be formed by etching away alternating pairs of first insulating layers 333 and second insulating layers 334 and filled with an electrically insulating material (e.g., nitride or oxide). The first connection region 312-L1 and the second connection region 312-R1 may contain alternating pairs of first insulating layers 333 and second insulating layers 334 or an electrically insulating material.

[0162] In some instances, such as Figure 3A As shown, the second portion 310-R includes a fourth connection region 312-R2 similar to the second connection region 312-R1. The fourth connection region 312-R2 is adjacent to the conductive contact window region 303-R, which is adjacent to the right-side array structure 304. The fourth connection region 312-R2 is separated from the second connection region 312-R1 along the Y direction. The second connection region 312-R1 and the fourth connection region 312-R2 may have the same size, height (along the X direction), and / or width (along the Y direction). Along the X direction, the connection regions 312-R1 and 312-R2 may be spaced apart from the conductive slit 309C1 by a distance.

[0163] like Figures 3A to 3B As shown, the second portion 310-R includes a first word line bonding pad region 313-R1, which has a second stepped structure formed between the second connection region 312-R1 and the conductive slit 309C1. The second stepped structure in the first word line bonding pad region 313-R1 is configured to individually expose the conductive layer in the right-side array structure 304. Multiple word line layer contact windows (WL_COA) 316 (e.g., Figure 2 The WL_COA224 is formed in the first word line bonding pad region 313-R1, which is connected to the corresponding word line bonding pad. The word line layer contact window (WL_COA) 316 can be accessed via a corresponding conductive interconnect (e.g., Figure 2 The internal interconnect 223 is electrically connected to the corresponding TAC 318 formed in the second connection region 312-R1. Each TAC 318 in the second connection region 312-R1 is electrically connected to a separate contact pad 308 in the CuA layer (e.g., ...). Figure 3B(As shown in the diagram). In this manner, each word line layer in the right-side array structure 304 can be electrically connected to individual contact pads 308 in the circuit via a corresponding WL_COA 316 (in the first word line bonding pad region 313-R1), a corresponding conductive interconnect, and a corresponding TAC 318 (in the second connection region 312-R1). Similarly, the second portion 310-R also includes a second word line bonding pad region 313-R2, which has another second stepped structure formed between the fourth connection region 312-R2 and the conductive slit 309C1. The word line layers in the right-side array structure 304 can be electrically connected to individual contact pads 308 in the lower array circuit via a corresponding WL_COA 316 (in the second word line bonding pad region 313-R2), a corresponding conductive interconnect, and a corresponding TAC 318 (in the fourth connection region 312-R2).

[0164] Along a second direction (e.g., the X direction), the first letter line connecting to the pad region 313-L1 in the first portion 310-L and the first letter line connecting to the pad region 313-R1 in the second portion 310-R are disposed between the first connecting region 312-L1 and the second connecting region 312-R1. The first letter line connecting to the pad region 313-L1 and the first letter line connecting to the pad region 313-R1 may be adjacent to each other along the X direction and separated by the conductive slit 309C1. Similarly, along a second direction (e.g., the X direction), the second letter line connecting to the pad region 313-L2 in the first portion 310-L and the second letter line connecting to the pad region 313-R2 in the second portion 310-R are disposed between the third connecting region 312-L2 and the fourth connecting region 312-R2. The second letter line adjacent to the pad area 313-L2 and the second letter line adjacent to the pad area 313-R2 can be adjacent to each other along the X direction and separated by the conductive slit 309C1.

[0165] In some implementations, such as Figures 3A to 3B As shown, process window 314-L has a boundary 315 and covers both the first word line bonding pad region 313-L1 in the first portion 310-L and the first word line bonding pad region 313-R1 in the second portion 310-R. Process window 314-L may also cover at least a portion of the first connection region 312-L1 in the first portion 310-L, at least a portion of the second connection region 312-R1 in the second portion 310-R, or both. In some embodiments, process window 314-L can be formed using a minimum incremental layer cost (MiLC) process to reduce costs. The MiLC process can produce multiple stepped structures with bonding pads for each word line layer. The MiLC process can produce stepped structures using minimal photoresist (or photolithography) and etching steps. Process window 314-L may be referred to as a MiLC process window.

[0166] like Figure 3B As shown, individual word line layers can be exposed in process window 314-L and can be electrically connected to individual contact pads in the circuit by forming WL_COA 316 in the stepped structure of the first word line contact pad region 313-L1 in the first portion 310-L and the first word line contact pad region 313-R1 in the second portion 310-R. In a particular example, the MiLC process can cause the deeper stepped word line layer to extend slightly shorter than the adjacent shallower stepped word line layer.

[0167] Similarly, another process window 314-R may cover both the second letter line adjacent to the pad area 313-L2 in the first portion 310-L and the second letter line adjacent to the pad area 313-R2 in the second portion 310-R. Process window 314-R may also cover at least a portion of the third connecting area 312-L2 in the first portion 310-L, at least a portion of the fourth connecting area 312-R2 in the second portion 310-R, or both. Process windows 314-L and 314-R may generally be referred to as process window 314 or individually as process window 314.

[0168] like Figures 3A to 3C As shown, in the central stepped region 310, there are multiple unprocessed structures 320, 322, 324, and 326, which are outside the process window 314 and do not have stepped or stepped structured word line layers. Each of the unprocessed structures 320, 322, 324, and 326 may be referred to as a stack of alternating conductive layers 332 and insulating layers 334 not formed by a method having a stepped structure for forming adhesive pads for word line layers (e.g., MiLC process). The unprocessed structures include a first unprocessed structure 320, a second unprocessed structure 326, a third unprocessed structure 322, and a fourth unprocessed structure 324, wherein the first unprocessed structure 320 and the third unprocessed structure 322 are in the first portion 310-L, and the second unprocessed structure 326 and the fourth unprocessed structure 324 are in the second portion 310-R.

[0169] The first unprocessed structure 320 in the first part 310-L may include a first region and a second region. The first region of the first unprocessed structure 320 is located between the first connection region 312-L1 and the third connection region 312-L2 along the Y direction, and between the conductive slit 323 and the conductive slit (source line) 309B along the X direction. The conductive slit 323 has a side surface (or wall) covered with a dielectric material (e.g., oxide) insulating from adjacent layers and an interior portion filled with a conductive material (e.g., metal). The second region of the first unprocessed structure 320 includes a first segment and a second segment. The first segment is located between the first connection region 312-L1 and the adjacent conductive slit (source line) 309B. The second segment is located between the third connection region 312-L2 and the adjacent conductive slit (source line) 309B. The first unprocessed structure 320 is outside the process window 314 and does not have a stepped or stepped structured word line layer, such as... Figures 3B to 3C As shown in the diagram. Similarly, the third unprocessed structure 322 in the first portion 310-L is located between the first letter bonding pad region 313-L1 and the second letter bonding pad region 313-L2 along the Y direction, and between the conductive slit 323 and the conductive slit 309C1 along the X direction. The first connection region 312-L1 is located between the first segment of the second region of the first unprocessed structure 320 and the first letter bonding pad region 313-L1. The third connection region 312-L2 is located between the second segment of the second region of the first unprocessed structure 320 and the second letter bonding pad region 313-L2 along the X direction. The boundary 315 of the process window 314-L can be moved away from the first letter bonding pad region 313-L1 to increase the size of the process window 314-L. The first unprocessed structure 320 and the third unprocessed structure 322 are electrically connected to the left array structure 302 via word line layer contact windows WL_COA 316 in the first word line connection pad area 313-L1 and the second word line connection pad area 313-L2.

[0170] In some implementations, such as Figure 3A As shown, the third unprocessed structure 322 is separated from the first unprocessed structure 320 along the Y direction via a conductive slit 323. The conductive slit 323 does not extend to connect the connection regions 312-L1 and 312-L2. Therefore, the word line layer in the first unprocessed structure 320 can be electrically connected to the word line layer in the third unprocessed structure 322 via the unseparated region without the conductive slit 323.

[0171] like Figure 3G As shown, the second unprocessed structure 326 in the second part 310-R may include a first region 326-1 and a second region 326-2. For example... Figure 3FAs shown, the first region 326-1 is located along the Y direction between the second connection region 312-R1 and the fourth connection region 312-R2 in the second portion 310-R, and along the X direction between the conductive slit 325 and the top conductive slit 309T. The conductive slit 325 is similar to the conductive slit 323 and has a side surface (or wall) covered with a dielectric material (e.g., oxide) insulating from adjacent layers and an interior portion filled with a conductive material (e.g., metal). The second region 326-2 (as shown...) Figure 3G (As shown) includes a first segment and a second segment with a first segment 326-1 therebetween. The first segment of the second segment 326-2 is between the second connection region 312-R1 and the top conductive slit 309T. The second segment of the second segment 326-2 is between the fourth connection region 312-R2 and the top conductive slit 309T. The second unprocessed structure 326 is also outside the process window 314 and does not have a stepped or stepped structured word line layer, such as Figures 3B to 3C As shown in the figure.

[0172] The fourth unprocessed structure 324 in the second part 310-R can be located along the Y direction between the first word line bonding pad region 313-R1 and the second word line bonding pad region 313-R2 in the second part 310-R, and along the X direction between the conductive slit 325 and the conductive slit 309C1. The second unprocessed structure 326 and the fourth unprocessed structure 324 are conductively connected to the right array structure 304 via the word line layer contact window WL_COA 316 in the word line bonding pad region 313-R1 and the word line bonding pad region 313-R2. Figure 3A As shown, the fourth unprocessed structure 324 is separated from the second unprocessed structure 326 along the Y direction via a conductive slit 325. The conductive slit 325 does not extend to connect the connection regions 312-R1 and 312-R2. Therefore, the word line layer in the fourth unprocessed structure 324 can be electrically connected to the word line layer in the second unprocessed structure 326 via the unseparated region without the conductive slit 325.

[0173] In the formation process of conductive slots 323 and 325, the strip-shaped slots used to form conductive slots 323 or 325 extend along the Z direction to pass through alternating pairs of first insulating layers 333 and a second insulating layer 334. The second insulating layer 334 may be removed by etching via the strip-shaped slots during a gate replacement process in the central step region 310 and replaced with a conductive material (e.g., tungsten) to form a conductive layer 332. In some embodiments, at least the word line layer of the conductive layer 332 (e.g., tungsten) in the fourth untreated structure 324 and the second untreated structure 326 is an integrated wafer not separated by the strip-shaped slots. The strip-shaped slots are then covered by a dielectric material (e.g., oxide) on the sidewall surface. A conductive material (e.g., tungsten) is filled within the dielectric material to form conductive slots 323 or 325. Conductive slots 323 or 325 include conductive gates that extend along the YZ plane and pass through... Figure 3C The diagram illustrates a stack of alternating conductive layers 332 (e.g., tungsten) and a second insulating layer 334 (e.g., oxide). Similarly, at least the word line layer of the conductive layers 332 (e.g., tungsten) in the first untreated structure 320 and the third untreated structure 322 may be an integrated sheet not separated by the strip slit or conductive slit 323.

[0174] Figure 3BThis is a cross-sectional view 330 along the Y1-Y1′ line across process window 314-L. The length of process window 314-L along the X direction is greater than the sum of the lengths of the first letter-adjacent pad region 313-L1 in the first portion 310-L and the first letter-adjacent pad region 313-R1 in the second portion 310-R, but less than the distance from the boundary of the first connecting region 312-L1 to the boundary of the second connecting region 312-R1. In at least one instance along the X direction, the sum of the lengths of the third untreated structure 322 and the fourth untreated structure 324 is substantially equal to the sum of the lengths of the first letter-adjacent pad region 313-L1 and the first letter-adjacent pad region 313-R1. In some instances, the length of process window 314-L along the X direction is at least 1.5 times (e.g., about 166%) greater than the sum of the lengths of the first letter-adjacent pad region 313-L1 and the first letter-adjacent pad region 313-R1. In a specific example, the length of the process window 314-L along the X direction is 5 / 8 of the length of block 300. The sum of the lengths of the first word line adjacent to the pad area 313-L1 and the first word line adjacent to the pad area 313-R1 is 2 / 8 of the length of block 300. The length of block 300 along the X direction can be the distance between conductive slits 309B and 309T. Therefore, the word line layer contact window WL_COA 316 is formed within the process window 314-L, and the TAC 318 formed in the first connection area 312-L1 and the second connection area 312-R1 can also be formed within the process window 314-L.

[0175] In addition, such as Figure 3A As shown, along the Y direction, the length of process window 314-L or process window 314-R can be less than the length of connection region 312-L1 or connection region 312-R1, or connection region 312-L2 or connection region 312-R2. In some instances, such as Figure 4A As shown, along the Y direction, the length of the process window can be greater than the length of the connection area.

[0176] Figure 3C A cross-sectional view 340 is shown along the Y2-Y2′ line across unprocessed structures 320, 322, 324, and 326 without crossing the process window 314. It shows that there are no stepped word line layers outside the process window 314, unprocessed structures 320, 322, 324, and 326. Additionally, along the Z-direction, the third unprocessed structure 322, the first unprocessed structure 320, and the nth first conductive layer in the left array structure 302, and the fourth unprocessed structure 324, the second unprocessed structure 326, and the nth second conductive layer in the right array structure 304 can be in the same layer, where n is an integer.

[0177] To further describe memory block 300, a cross-sectional view in the YZ plane is shown. For example, Figure 3D This is a top view 350 of memory block 300 (in the XY plane), and Figures 3E to 3G These are cross-sectional views X1-X1′360, X2-X2′370, and X3-X3′380 (in the YZ plane). The X1-X1′ tangent intersects with the word line array contact window WL_COA 316 in the word line adjacency pad area 313-R1 and word line adjacency pad area 313-R2. Furthermore, the X1-X1′ tangent intersects with the fourth unprocessed structure 324. The X2-X2′ tangent intersects with the through-array contact window TAC 318 in the connection area 312-R1 and connection area 312-R2. Furthermore, the X2-X2′ tangent intersects with the second unprocessed structure 326. The X3-X3′ tangent intersects with the first region 326-1 and the second region 326-2 of the second unprocessed structure 326.

[0178] The central stepped region 310 may include one or more process windows depending on the number of word line layers visible in the memory block 300. For example, the memory block 300 may contain 100 word line layers along the Z direction, and the process window (e.g., MiLC process window 314) may be configured to expose 5 word line layers. The central stepped region 310 may include 20 process windows for driving the connection contact windows of the 100 word line layers.

[0179] like Figure 3E As shown, the X1-X1′ tangent intersects with the letter line adjacency padding areas 313-R1 and 313-R2 in the second portion 310-R. Furthermore, the X1-X1′ tangent intersects with the fourth unprocessed structure 324. The first letter line adjacency padding area 313-R1 in the second portion 310-R and the first letter line adjacency padding area 313-L1 in the first portion 310-L are in the same process window 314-L. The width (in the Y direction) of the letter line adjacency padding area (313-R1 or 313-L1) in the same process window 314-L may have the same width as the process window 314-L. Similarly, the second letter line adjacency padding area 313-R2 in the second portion 310-R and the second letter line adjacency padding area 313-L2 in the first portion 310-L are in the same process window 314-R. Figure 3DAs shown, the width (in the Y direction) of the word line bonding pad area (313-R2 or 313-L2) in the same process window 314-R can have the same width as process window 314-R. Word line bonding pad areas 313-R1 and 313-R2 are located in separate process windows 314-L and 314-R. Process windows (314-L and 314-R) are obtained by performing a method (e.g., MiLC process) with a stepped structure for forming bonding pads for the word line layer. Return to Figure 3E The word line bonding pad regions 313-R1 and 313-R2 each have separate process openings 362 and 364, which may have different depth steps (along the Z direction) to expose target word line layers (e.g., 5 word line layers). These target word line layers are further etched to form separate stepped structures 361 and 363. Each word line layer contact window 316 is formed to electrically connect to the respective stepped word line layers in the word line bonding pad regions 313-R1 and 313-R2. Figure 2 Similar to WL_COA 224, the word line layer contact window 316 is electrically coupled to the corresponding TAC 318 formed in the connection areas 312-R1 and 312-R2, such as Figure 3F As shown in the image. Figure 3E As shown, along the Y direction from left to right, process openings 362 and 364 can become increasingly deeper, and the stepped letter line layer can be formed along the Z direction from top to bottom.

[0180] Each word line layer in the right-side array structure 304 is electrically connected to a separate contact pad 308 in the circuit. In some embodiments, such as Figure 3D As shown, at least one of the word line layers in the right-hand array structure 304 extends to the second unprocessed structure 326 (shown in...). Figure 3G and Figure 3F The corresponding conductive layer 365 in the middle, and the fourth untreated structure 324 extends to the first word line of the second portion 310-R, which is connected to the same stepped conductive layer 365 in the pad region 313-R1 (shown in Figure 3E (Chinese). For example Figure 3E As shown, the corresponding word line layer contact window WL_COA316 is connected to the same stepped conductive layer 365 and is electrically connected to... Figure 3F The corresponding through-array contact window TAC 318 in the second connection area 312-R1. The corresponding through-array contact window TAC 318 is connected to the individual contact pads 308 in the circuit. Therefore, signals, current or voltage can be transmitted via, as shown in the figure. Figure 3D The trace 351 shown transmits between the circuit and the word line layer in the right array structure 304.

[0181] In some implementations, such as Figure 3D As shown, at least one word line layer in the right-side array structure 304 extends to a corresponding conductive layer in the second unprocessed structure 326, and the fourth unprocessed structure 324 extends to the same stepped conductive layer in the second word line adjoint pad regions 313-R2. A corresponding word line layer contact window WL_COA 316 connects to the same stepped conductive layer and is electrically connected to a corresponding through-array contact window TAC 318 in the fourth connection region 312-R2. The corresponding through-array contact window TAC 318 connects to individual contact pads 308 in the circuit. Therefore, signals, current, or voltage can be transmitted between the circuit and the word line layer in the right-side array structure 304 via trace 353.

[0182] The word line layer in the right array structure 304 can be along trace 351 (e.g. Figure 3D (as shown in the diagram) or trace 353 is electrically connected to the circuit. In some embodiments, at least one of the word line layers in the right array structure 304 is electrically connected to the circuit via a corresponding stepped conductive layer in the second word line contact pad region 313-R2, a corresponding word line layer contact window 316, and a corresponding through-array contact window TAC 318 without passing through the second unprocessed structure 326 and / or the fourth unprocessed structure 324.

[0183] In some embodiments, the corresponding conductive layer 365 is as follows: Figure 3G The diagram shows the second region 326-2 and the first region 326-1 of the second untreated structure 326 along the X3-X3′ tangent. The conductive layer 365 in the first region 326-1 of the second untreated structure 326 is along the Y direction (e.g., ...). Figure 3F As illustrated, along the X2-X2′ tangent, between the second connection region 312-R1 and the fourth connection region 312-R2. The conductive layer 365 further extends from the first region 326-1 of the second untreated structure 326 to the fourth untreated structure 324, word line adjacency pad region 313-R1, or word line adjacency pad region 313-R2 (as shown in the diagram). Figure 3F As shown in the diagram, along the X1-X′ tangent. The conductive layer 365 is via, as... Figure 3D The unseparated region without the conductive slit 325 shown is integrated in the first region 326-1 of the second untreated structure 326 and the fourth untreated structure 324. It can be a single conductive layer (e.g., Figures 3E to 3G The conductive layer 365 (shown) extends from the right array structure 304 to the second unprocessed structure 326, the fourth unprocessed structure 324, and the word line bonding pad area 313-R1 or word line bonding pad area 313-R2 in the same word line layer.

[0184] Figure 4AAnother example 400 of the process windows 420 and 430 of the central stepped region 410 in a 3D memory device is shown. The central stepped region 410 is positioned between two adjacent array structures of the memory cell, for example, Figure 3A The left array structure 302 and the right array structure 304.

[0185] The central stepped region 410 contains the left-side array structure (e.g., Figure 3A The first part of the left array structure 302) and the right array structure (e.g., Figure 3A The second part of the right array structure 304. Along the X direction, the first part includes the left unprocessed structure 402, two connection areas 404, connection area 434 and the left stepped structure 406, and the second part includes the right stepped structure 416, two connection areas 414, connection area 444 and the right unprocessed structure 412.

[0186] The process window can have different sizes and / or different shapes. Figures 3A to 3B Compared to process windows 314-L or 314-R, process windows 420 and 430 of the central stepped region 410 may have a length along the Y direction greater than that of connecting regions 404, 414, 434, or 444. Process windows 420 and 430 may also have a rectangular shape. Process windows 420 and 430 may have a length along the X direction greater than the sum of the lengths of the left stepped structure 406 and the right stepped structure 416, but less than the sum of the lengths of the left stepped structure 406 and the right stepped structure 416, and the lengths of connecting regions 404 and 414.

[0187] Figure 4B Another example 450 of the process windows 460 and 470 in the central stepped area 410 is shown. Unlike... Figure 4A Process windows 420, 430, 460, and 470 can be square in shape. Along the Y-direction, process windows 460 and 470 have a length less than that of connecting areas 404, 414, 434, and 444. Along the X-direction, process windows 460 and 470 can have a length greater than the sum of the lengths of the left stepped structure 406 and the right stepped structure 416, but less than the sum of the lengths of the left stepped structure 406 and the right stepped structure 416, and the lengths of connecting areas 404 and 414.

[0188] Figure 5 A flowchart illustrating an example of a process 500 for forming a drive connection structure for a 3D memory device. The 3D memory device can be implemented as... Figure 1A The memory 116.

[0189] In step 502, an array of memory cells containing a conductive layer is formed. The memory cells may be... Figure 3A The memory cell 301. The memory cell array can be formed by forming alternating conductive layers (e.g., made of metal) and insulating layers (e.g., OX) and then forming vertical channels (VC) through the alternating conductive layers and insulating layers.

[0190] At step 504, along a first direction (e.g., the Y direction), the memory cell array is separated into a first array structure (e.g., Figure 3A The left array structure 302), the second array structure (e.g., Figure 3A The right-side array structure 304) and the connection structure between the first array structure and the second array structure (e.g., Figure 3A (Central stepped area 310).

[0191] At step 506, a connection is formed through the first connection region (e.g., Figure 3A The first through-array contact window of the first connection area 312-L1 (e.g., Figure 3A TAC 318) and through the second connection area (e.g., Figure 3A The second through-array contact window of the second connection area 312-R1 is electrically connected to the circuit (e.g., Figure 2 The CuA layer 202). The first connection region and the second connection region are separated along a second direction (e.g., the X direction) perpendicular to the first direction.

[0192] At step 508, the first stepped structure and the second stepped structure are formed at the process window (e.g., Figure 3A In the process window 314-L. The first stepped structure and the second stepped structure are adjacent to each other along the second direction. The process window covers at least a portion of the first connection area, the first stepped structure, the second stepped structure, and at least a portion of the second connection area. The first stepped structure and the second stepped structure are located between the first connection area and the second connection area along the second direction.

[0193] Process 500 may further include: forming a first contact window (e.g., along a third direction (e.g., the Z direction) perpendicular to the plane defined by the first and second directions) coupled to the first conductive layer in the first stepped structure. Figure 3A The word line layer contact window WL_COA 316), and the second layer contact window (e.g., formed along a third direction and coupled to the second conductive layer in the second stepped structure) Figure 3A WL_COA 316). Process 500 may further include: forming corresponding conductive interconnects (e.g., WL_COA 316). Figure 2The internal connection 223) connects the first layer contact window and the second layer contact window to the first through array contact window and the second through array contact window.

[0194] In some instances, along the first direction, the length of the process window may be less than at least one of the lengths of the first connection region and the second connection region. In some instances, the length of the process window along the first direction is greater than at least one of the lengths of the first connection region and the second connection region. The length of the first connection region may be the same as the length of the second connection region. A first layer of contact windows and a second layer of contact windows may be formed within the process window. A first through-array contact window and a second through-array contact window may be formed at least partially within the process window or outside the process window.

[0195] In some embodiments, the connection structure further includes a third connection region spaced apart from the first connection region along a first direction (e.g., Figure 3A The third connection region 312-L2), and the fourth connection region spaced apart from the second connection region along the first direction (e.g., Figure 3A The fourth connection region 312-R2). The second process window (e.g., Figure 3A The process window 314-R can cover at least a portion of the third connection area, the first stepped structure, the second stepped structure, and at least a portion of the fourth connection area along the second direction.

[0196] The connection structure may include: a first untreated structure electrically coupled to a first conductive layer in the first array structure (e.g., Figure 3A (320) and the second untreated structure (e.g., electrically coupled to the second conductive layer in the second array structure) and the second untreated structure. Figure 3A (326).

[0197] The first connecting region can be disposed between the first stepped structure and the first untreated structure along a second direction perpendicular to the first direction, and the second connecting region can be disposed between the second stepped structure and the second untreated structure along the second direction. The first stepped structure and the second stepped structure can be adjacent to each other and disposed between the first connecting region and the second connecting region along the second direction.

[0198] At least a portion of the first unprocessed structure may extend along a first direction between the first and third connection regions and outside the first and second process windows. The second unprocessed structure (e.g., Figure 3F At least a portion of (326-1) may be located along the first direction between the second and fourth connection regions and outside the first and second process windows. Another portion of the first untreated structure may be separated from the first stepped structure along the second direction through the first or third connection region. The second untreated structure (e.g., Figure 3GAnother part of 326-2) separates from the second stepped structure along the second direction through the second connecting area or the fourth connecting area.

[0199] In some embodiments, at least one of the first conductive layers in the first array structure is transmitted via a corresponding first unprocessed conductive layer in the first unprocessed structure (e.g., Figure 3F and Figure 3G (365), the corresponding first-step conductive layer in the first-step structure (e.g., Figure 3E (365), one corresponding to the first contact window and one corresponding to the first through-array contact window are electrically connected to the circuit. The corresponding first unprocessed conductive layer in the first unprocessed structure and the corresponding first stepped conductive layer in the first stepped structure form a single conductive layer, such as... Figures 3E to 3G As shown in the diagram, the corresponding first untreated conductive layer in the first untreated structure may include a first portion of the first untreated structure between the first connection region and the second connection region along a first direction (e.g., Figure 3F The first sub-layer in (e.g., 326-1) Figure 3F (365) and the second part of the first untreated structure separated from the first stepped structure along the second direction through the first connecting area and the third connecting area (e.g., Figure 3G The second sub-layer in (e.g., 326-2) Figure 3E (365). The first sublayer and the second sublayer can form a corresponding first untreated conductive layer.

[0200] In some embodiments, the corresponding first stepped conductive layer in the first stepped structure and the corresponding first contact window are located in one of the first process window and the second process window.

[0201] In some embodiments, at least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through-array contact windows without passing through the first untreated structure.

[0202] A first conductive layer may be sequentially disposed in a first array structure along a third direction (e.g., the Z direction) perpendicular to the plane defined by the first and second directions, and a second conductive layer may be sequentially disposed in a second array structure along the third direction. The nth first conductive layer in the first array structure and the nth second conductive layer in the second array structure may be electrically connected to the same conductive pad in the circuit (e.g., ...). Figure 3B (308), where n is an integer.

[0203] While this disclosure may describe many features, such features should not be construed as limiting the scope claimed or assertable by this disclosure, but rather as describing features specific to a particular embodiment. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even initially claimed in this manner, one or more features from the claimed combinations may be removed from said combinations in some cases, and the claimed combinations may be for sub-combinations or variations thereof. Similarly, although operations are depicted in a particular order in the drawings, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order, or to perform all the operations shown to achieve the desired result.

[0204] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations, as well as other implementations, can be made based on the disclosed content.

Claims

1. A semiconductor device, comprising: A first array structure of memory cells includes a first conductive layer; The second array structure of the memory cells includes a second conductive layer; A connecting structure is disposed between the first array structure and the second array structure along a first direction; as well as The circuit is configured adjacent to the connection structure. The connection structure includes: A first connection region, wherein the first conductive layer is electrically connected to the circuit via the first connection region; The first stepped structure is configured to individually expose the first conductive layer; A second-step structure is configured to individually expose the second conductive layer; and The second connection region allows the second conductive layer to be connected to the circuit. The first stepped structure and the second stepped structure are disposed between the first connecting area and the second connecting area along a second direction perpendicular to the first direction; The first conductive layer is sequentially disposed in the first array structure along a third direction perpendicular to the plane defined by the first direction and the second direction, and the second conductive layer is sequentially disposed in the second array structure along the third direction. The first array structure, the first connection region, and the first step structure are separated from the second array structure, the second connection region, and the second step structure by a conductive slit structure. The conductive slit structure includes: A first slit portion is disposed between the first and second stepped structures along a second direction, the first slit portion extending along both the first and third directions. A second slit portion is disposed along a first direction between the first array structure and the second connection area, the second slit portion extending along the second direction and a third direction, and A third slit portion is located between the first connection area and the second array structure along the first direction, and the third slit portion extends along the second direction and the third direction.

2. The semiconductor device according to claim 1, The first conductive layer is configured to be electrically connected to the circuit via a first contact window coupled to the first conductive layer in the first stepped structure and a first through-array contact window passing through the first connection area and coupled to the circuit. The second conductive layer is configured to be electrically connected to the circuit via a second contact window coupled to the second conductive layer in the second stepped structure and a second through-array contact window passing through the second connection area and coupled to the circuit.

3. The semiconductor device of claim 2, wherein each of the first contact window and the second contact window is electrically connected to each of the first through-array contact window and the second through-array contact window via a corresponding conductive interconnect.

4. The semiconductor device of claim 2, wherein the process window covers at least a portion of the first connection region, the first stepped structure, the second stepped structure, and at least a portion of the second connection region along the second direction.

5. The semiconductor device of claim 4, wherein along the first direction, the length of the process window is less than at least one of the length of the first connection region and the length of the second connection region.

6. The semiconductor device of claim 2, wherein the connection structure further comprises: The third connection region is spaced apart from the first connection region along the first direction; as well as The fourth connection region is spaced apart from the second connection region along the first direction. The first process window covers at least a portion of the first connection area, the first stepped structure, the second stepped structure, and at least a portion of the second connection area along the second direction. The second process window covers at least a portion of the third connection area, the first stepped structure, the second stepped structure, and at least a portion of the fourth connection area along the second direction.

7. The semiconductor device of claim 6, wherein the connection structure further comprises: A first unprocessed structure is electrically coupled to the first conductive layer in the first array structure, wherein at least a portion of the first unprocessed structure is disposed along the first direction between the first connection region and the third connection region and outside the first process window and the second process window; as well as The second unprocessed structure is electrically coupled to the second conductive layer in the second array structure, wherein at least a portion of the second unprocessed structure is disposed along the first direction between the second connection region and the fourth connection region and outside the first process window and the second process window.

8. The semiconductor device of claim 7, wherein another portion of the first unprocessed structure is separated from the first stepped structure along the second direction via the first connection region or the third connection region, and Another portion of the second unprocessed structure separates from the second stepped structure along the second direction through the second connection area or the fourth connection area.

9. The semiconductor device of claim 7, wherein at least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first unprocessed conductive layer in the first unprocessed structure, a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through-array contact windows.

10. The semiconductor device of claim 9, wherein the corresponding first unprocessed conductive layer in the first unprocessed structure and the corresponding first stepped conductive layer in the first stepped structure form a single conductive layer.

11. The semiconductor device of claim 9, wherein the corresponding first untreated conductive layer in the first untreated structure comprises: The first sublayer is located along the first direction in the first portion of the first unprocessed structure between the first connection region and the second connection region; as well as The second sublayer, located along the second direction, is in the second portion of the first unprocessed structure separated from the first stepped structure by the first connection area and the third connection area. The first sub-layer and the second sub-layer form the corresponding first untreated conductive layer.

12. The semiconductor device of claim 9, wherein the corresponding first stepped conductive layer in the first stepped structure and the corresponding one of the first layer contact windows are located in one of the first process window and the second process window.

13. The semiconductor device of claim 7, wherein at least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through-array contact windows without passing through the first unprocessed structure.

14. The semiconductor device according to claim 2, The nth first conductive layer in the first array structure and the nth second conductive layer in the second array structure are electrically connected to the same conductive pad in the circuit, where n is an integer.

15. A semiconductor device, comprising: A first array structure of memory cells includes a first conductive layer; The second array structure of the memory cells includes a second conductive layer; A connecting structure is disposed between the first array structure and the second array structure along a first direction; as well as The circuit is configured adjacent to the connection structure. The connection structure includes: The first stepped structure is configured to individually expose the first conductive layer; The first unprocessed structure is electrically coupled to the first conductive layer in the first array structure; A first connection region, wherein the first conductive layer is electrically connected to the circuit via the first connection region, and the first connection region is disposed between the first stepped structure and the first untreated structure along a second direction perpendicular to the first direction; The second stepped structure is configured to individually expose the second conductive layer; The second unprocessed structure is electrically coupled to the second conductive layer in the second array structure; and The second connection region, through which the second conductive layer can be electrically connected to the circuit, is disposed along the second direction between the second stepped structure and the second untreated structure.

16. The semiconductor device of claim 15, wherein the first conductive layer is configured to be electrically connected to the circuit via a first contact window of the first conductive layer coupled to the first stepped structure and a first through-array contact window passing through the first connection region and coupled to the circuit. At least one of the first conductive layers in the first array structure is electrically connected to the circuit via a corresponding first unprocessed conductive layer in the first unprocessed structure, a corresponding first stepped conductive layer in the first stepped structure, a corresponding one of the first layer contact windows, and a corresponding one of the first through-array contact windows. The second conductive layer is configured to be electrically connected to the circuit via a second contact window coupled to the second conductive layer in the second stepped structure and a second through-array contact window passing through the second connection area and coupled to the circuit. At least one of the second conductive layers in the second array structure is electrically connected to the circuit via a corresponding second unprocessed conductive layer in the second unprocessed structure, a corresponding second stepped conductive layer in the second stepped structure, a corresponding one of the second layer contact windows, and a corresponding one of the second through array contact windows.

17. The semiconductor device of claim 15, wherein the connection structure further comprises: The third connection region is spaced apart from the first connection region along the first direction; as well as The fourth connection region is spaced apart from the second connection region along the first direction. The first process window covers at least a portion of the first connection area, the first stepped structure, the second stepped structure, and at least a portion of the second connection area along the second direction. The second process window covers at least a portion of the third connection area, the first stepped structure, the second stepped structure, and at least a portion of the fourth connection area along the second direction.

18. The semiconductor device according to claim 17, The first unprocessed structure includes: The first part is located along the first direction between the first connection area and the third connection area, and outside the first process window and the second process window; as well as The second part separates from the first stepped structure along the second direction through the first connecting area and the third connecting area, and The second unprocessed structure includes: The third part is located along the first direction between the second connection area and the fourth connection area, and outside the first process window and the second process window; as well as The fourth part separates from the second stepped structure along the second direction through the second connecting area and the fourth connecting area.

19. A method of forming a semiconductor device, comprising: Forming a memory cell array including a conductive layer; The memory cell array is separated along a first direction into a first array structure including a first conductive layer, a second array structure including a second conductive layer, and a connection structure between the first array structure and the second array structure. A first through-array contact window is formed through the first connection area to be electrically connected to a circuit adjacent to the connection structure, and a second through-array contact window is formed through the second connection area to be electrically connected to the circuit, wherein the first connection area and the second connection area are separated along a second direction perpendicular to the first direction; as well as A first stepped structure and a second stepped structure are formed within the process window, wherein the first stepped structure and the second stepped structure are adjacent to each other along the second direction. The process window covers at least a portion of the first connection area, the first stepped structure, the second stepped structure, and at least a portion of the second connection area, and the first stepped structure and the second stepped structure are located between the first connection area and the second connection area along the second direction.

20. The method of forming a semiconductor device according to claim 19, further comprising: A first contact window is formed along a third direction perpendicular to the plane defined by the first direction and the second direction, coupled to the first conductive layer in the first stepped structure; and a second contact window is formed along the third direction, coupled to the second conductive layer in the second stepped structure. as well as Corresponding conductive interconnects are formed to connect the first layer contact window and the second layer contact window to the first through-array contact window and the second through-array contact window.

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