Magnetic memory elements and methods of making the same

Abstract

A magnetic memory element and a method of fabricating the same are disclosed. The magnetic memory element includes a bottom electrode layer, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer. The metal cap layer includes a plurality of first metal layers and a plurality of second metal layers alternately stacked.

Description

Technical Field

[0001] This invention relates to a magnetic memory element and its manufacturing method, and more particularly to a magnetoresistive random access memory with a multi-layered metal capping layer and its manufacturing method. Background Technology

[0002] Magnetoresistive random access memory (MRAM) is a new type of memory that has received much attention in recent years. It integrates the advantages of various current memory types, such as access speed comparable to static random access memory (SRAM), non-volatility and low power consumption of flash memory, high density and durability of dynamic random access memory (DRAM), and can be integrated with current semiconductor back-end manufacturing processes. Therefore, it has the potential to become the main memory used in semiconductor chips.

[0003] Magnetoresistive random access memory (MRAM) comprises a memory stack structure disposed between upper and lower interconnect structures, including a magnetic tunneling junction (MTJ). Unlike traditional memory that stores data by storing charge, MRAM operates by applying an external magnetic field to the MMTJ to control its magnetization direction, thereby obtaining different tunneling magnetoresistive (TMR) values ​​to store digital data. Preventing impurities (such as ambient gases or elements from other material layers) from diffusing into the MMTJ and causing abnormal tunneling magnetoresistive properties is a key consideration in the fabrication of MRAM. Summary of the Invention

[0004] In view of the above problems, the present invention provides an improved magnetic memory element and a method for manufacturing the same, which includes a metal capping layer with a multilayer structure, which can provide better protection for the underlying magnetic tunneling junction (MTJ) stack and reduce the problem of impurities diffusing into the MTJ and causing abnormal tunneling magnetoresistance.

[0005] An embodiment of the present invention provides a magnetic memory element, which includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric capping layer disposed on the MTJ stack, and a metal capping layer disposed on the dielectric capping layer, wherein the metal capping layer includes a plurality of alternating first metal layers and second metal layers.

[0006] Another embodiment of the present invention provides a method for fabricating a magnetic memory element, comprising forming a magnetic tunneling junction stack on a bottom electrode layer, then forming a dielectric capping layer on the magnetic tunneling junction stack, and then forming a metal capping layer on the dielectric capping layer, wherein the metal capping layer comprises a plurality of alternating first metal layers and second metal layers. Attached Figure Description

[0007] Figures 1 to 4 This is a cross-sectional schematic diagram of a magnetic memory element according to an embodiment of the present invention during its fabrication.

[0008] Figure 5 This is a cross-sectional schematic diagram of a magnetic memory element according to another embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 10 base

[0011] 12 dielectric layers

[0012] 14. Internal Wiring Structure

[0013] 16 Dielectric Layers

[0014] 18. Internal Wiring Structure

[0015] 20 Magnetic tunneling stack

[0016] 24 Reference Layer

[0017] 25 Fixed Layer

[0018] 26. Tunneling through the energy barrier layer

[0019] 28 Free Layer

[0020] 30 Dielectric capping layer

[0021] 32 Metal capping layer

[0022] 34 Hard mask layers

[0023] 35 storage units

[0024] 40 protective layers

[0025] 42 interlayer dielectric layers

[0026] 44 Internal Wiring Structure

[0027] 32a First metal layer

[0028] 32b Second metal layer

[0029] BE bottom electrode layer

[0030] P1 Tempering process

[0031] P2 Patterning process Detailed Implementation

[0032] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in conjunction with the accompanying drawings. The accompanying drawings are schematic diagrams and not drawn to scale, and the same or similar features are generally described using the same reference numerals. The embodiments and drawings described herein are for reference and illustration only and are not intended to limit the present invention. The scope of the present invention is defined by the claims. Anything with the same meaning as the claims of the present invention should also be included within the scope of the present invention.

[0033] Figures 1 to 3 The illustration shows the steps of a method for manufacturing a magnetic memory element according to an embodiment of the present invention. Please refer to... Figure 1 First, a substrate 10 is provided, such as a silicon substrate, a silicon-on-insulator substrate, a group III-V semiconductor substrate, etc., but not limited to these. The substrate 10 may include fabricated semiconductor components, such as transistors, capacitors, resistors, inductors, etc., which are not shown in the accompanying drawings for simplicity. At least one dielectric layer and interconnect structures formed in the dielectric layer may be provided on the substrate 10, for example... Figure 1 As shown, a dielectric layer 12 and an interconnect structure 14 (e.g., a metal interconnect structure) located in the dielectric layer 12 may be provided on the substrate 10, as well as another dielectric layer 16 disposed on the dielectric layer 12 and an interconnect structure 18 (e.g., a contact plug) passing through the dielectric layer 16 and in direct contact with the interconnect structure 14. The dielectric layer 12 and the dielectric layer 16 may each include silicon oxide (SiO2) or a low-k dielectric material, wherein the low-k dielectric material is, for example, fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, or organic polymer dielectric material, but is not limited thereto. Interconnection structure 14 and interconnection structure 18 may each include conductive metal materials or metal compounds, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), but are not limited thereto.

[0034] Please refer to Figure 2Next, a stacked structure 100 is formed on the substrate 10. The stacked structure 100, from bottom to top, may sequentially include a bottom electrode layer BE, a magnetic tunneling junction (MTJ) stack 20, a dielectric capping layer 30, a metal capping layer 32, and a hard mask layer 34. The bottom electrode layer BE is disposed on the dielectric layer 16 and is in direct contact with the interconnect structure 18. The bottom electrode layer BE may include a conductive metal material or metal compound, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), but is not limited thereto.

[0035] The magnetic tunneling stack 20 comprises a multi-layer structure, which, from bottom to top (from near the substrate 10 to away from the substrate 10), may sequentially include a reference layer 24, a pinned layer 25, a tunneling barrier layer 26, and a free layer 28. The reference layer 24 is used to fix or restrict the magnetization direction of adjacent layers, and mainly includes antiferromagnetic (AFM) materials, such as platinum-manganese (PtMn), iridium-manganese (IrMn), platinum-iridium (PtIr), or combinations thereof, but is not limited to these. The pinned layer 25 and the free layer 28 mainly include ferromagnetic materials, such as iron (Fe), cobalt (Co), nickel (Ni), iron-nickel (FeNi), iron-cobalt (FeCo), cobalt-nickel (CoNi), iron-boron (FeB), iron-platinum (FePt), iron-palladium (FePd), cobalt-iron-boron (CoFeB), or combinations thereof, but are not limited to these. The magnetization direction of the fixed layer 25 is fixed by the reference layer 24, while the magnetization direction of the free layer 28 can be changed by an external magnetic field. The tunneling barrier layer 26 is sandwiched between the fixed layer 25 and the free layer 28, and may include metal oxides such as magnesium oxide (MgO), aluminum oxide (Al2O3), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (Ta2O5), molybdenum oxide (MoO2), titanium oxide (TiO2), tungsten oxide (WO2), or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, the tunneling barrier layer 26 includes magnesium oxide (MgO). The reference layer 24, fixed layer 25, tunneling barrier layer 26, and free layer 28 may each be a single-layer or multi-layer structure, with the thickness of each layer approximately between a few angstroms. Between tens of nanometers (nm).

[0036] The dielectric capping layer 30 can be directly disposed on the free layer 28 of the magnetic tunneling junction stack 20 to protect the magnetic tunneling junction stack 20. The material of the dielectric capping layer 30 may include metal oxides such as magnesium oxide (MgO), aluminum oxide (Al2O3), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (Ta2O5), molybdenum oxide (MoO2), titanium oxide (TiO2), tungsten oxide (WO2), manganese oxide (MnO), etc., but is not limited thereto. According to one embodiment of the present invention, the dielectric capping layer 30 includes magnesium oxide (MgO).

[0037] The metal capping layer 32 can be directly disposed on the dielectric capping layer 30, or it can be disposed on the dielectric capping layer 30 as a buffer layer (e.g.) Figure 5 The metal capping layer 32 has a multilayer structure, including multiple (e.g., n+1, where n is a positive integer greater than or equal to 2) first metal layers 32a and multiple (e.g., n) second metal layers 32b, wherein the first metal layers 32a are located at the bottom and top layers a of the metal capping layer 32, and each of the second metal layers 32b is sandwiched between the first metal layers 32a. When the metal capping layer 32 is directly disposed on the dielectric capping layer 30, the dielectric capping layer 30 will be in direct contact with the bottom first metal layer 32a. The first metal layer 32a preferably includes a metal material with excellent conductivity and that can protect the underlying layers from oxidation, such as ruthenium (Ru). Ruthenium can react with oxygen to form a dense ruthenium oxide on its surface, preventing oxygen from penetrating and continuing to oxidize the underlying material layers. More importantly, ruthenium oxide still has excellent conductivity and will not cause abnormal resistance values. The second metal layer 32b preferably comprises a metallic material that can react with the unoxidized first metal layer 32a to form an alloy during subsequent high-temperature steps (e.g., tempering (annealing) process P1), to prevent the unoxidized first metal layer 32a from diffusing into the magnetic tunneling junction stack 20 and affecting the tunneling magnetoresistance. According to an embodiment of the present invention, when the first metal layer 32a comprises ruthenium (Ru), the second metal layer 32b may comprise a metallic material such as vanadium (V), manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re), or osmium (Os) with an alloy forming enthalpy of approximately -330 to -15 kJ / mol, so as to more easily form an alloy with ruthenium (Ru). According to one embodiment of the present invention, all first metal layers 32a of the metal capping layer 32 comprise ruthenium (Ru), and the second metal layers 32b may comprise one of manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), or tungsten (W). According to one embodiment of the present invention, all second metal layers 32b of the metal capping layer 32 comprise the same metallic material, such as manganese (Mn). Figure 2As shown, the thickness of the topmost first metal layer 32a can be selected to be greater than the thickness of the remaining first metal layers 32a below it, so as to serve as the main oxygen isolation layer.

[0038] The hard mask layer 34 can be directly disposed on the metal capping layer 32 and is in direct contact with the topmost first metal layer 32a. The hard mask layer 34 may include a conductive metal material or metal compound, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), but is not limited thereto. According to one embodiment of the present invention, the hard mask layer 34 includes titanium nitride (TiN). The hard mask layer 34 can be fabricated in a patterning process P2 (see reference). Figure 3 In the memory cell 35 (reference), it acts as an etch barrier layer to protect the underlying structure and helps to obtain a more vertical sidewall. Figure 3 It can also be used as the top electrode of the storage unit 35.

[0039] Please continue to refer to this. Figure 2 After forming the stacked structure 100, a tempering process P1 can be performed on the stacked structure 100 to improve the perpendicular magnetic anisotropy (PMA) of the magnetic material in the magnetic tunneling junction stack 20. According to one embodiment of the present invention, the tempering process P1 can be performed at a temperature between 350°C and 450°C for a time between 30 minutes and 5 hours, but is not limited thereto. The tempering process P1 promotes the downward diffusion of elements (e.g., nitrogen in titanium nitride) in the hard mask layer 34 and the material (e.g., ruthenium) in the first metal layer 32a of the metal capping layer 32. The present invention avoids the diffusion of ruthenium into the magnetic tunneling junction stack 20 by selecting the material of the second metal layer 32b as manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), or tungsten (W), which can react with ruthenium to form an alloy, and also blocks the diffusion of nitrogen, thereby reducing the problem of nitriding of the ferromagnetic material in the magnetic tunneling junction stack 20.

[0040] Please refer to Figure 3 Next, a patterning process P2 (e.g., photolithography and etching process) is performed to remove excess bottom electrode layer BE, magnetic tunneling junction stack 20, dielectric capping layer 30, metal capping layer 32 and hard mask layer 34, to obtain memory cells 35 located directly above the interconnect structure 18.

[0041] Please refer to Figure 4Next, a protective layer 40 is formed on the substrate 10, conformally covering the surface of the dielectric layer 16 and the top and sidewalls of the memory cell 35. Then, an interlayer dielectric layer 42 is formed on the protective layer 40 to completely cover the memory cell 35 and fill the gaps between the memory cells 35. The protective layer 40 may include an insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN), but is not limited thereto. The interlayer dielectric layer 42 may include silicon oxide (SiO2) or a low-k dielectric material, such as fluorinated silicon glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, or organic polymer dielectric material, but is not limited thereto. Subsequently, an interconnect structure 44 is formed directly above the memory cell 35. The interconnect structure 44 passes through the interlayer dielectric layer 42 and the protective layer 40, and is in direct contact and electrically connected to the hard mask layer 34 (as the top electrode) of the memory cell 35. The interconnect structure 44 may include conductive metal materials or metal compounds, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), but is not limited thereto.

[0042] Please continue to refer to this. Figure 4 The magnetic memory element provided by this invention includes a bottom electrode layer BE, a magnetic tunneling junction stack 20 disposed on the bottom electrode layer, a dielectric capping layer 30 disposed on the magnetic tunneling junction stack 20, a metal capping layer 32 disposed on the dielectric capping layer 30, and a hard mask layer 34 disposed on the metal capping layer 32. The metal capping layer 32 includes a plurality of alternatingly stacked first metal layers 32a and second metal layers 32b, wherein the top and bottom layers of the metal capping layer 32 are the first metal layers 32a, and the second metal layers 32b are sandwiched between the first metal layers 32a. This invention utilizes an alternating stacking design of the metal capping layers, and preferably selects the first metal layer 32a to include ruthenium (Ru) and the second metal layer 32b to include at least one of manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), or tungsten (W), which can effectively reduce the risk of oxidation and / or nitriding of the underlying magnetic tunneling junction stack 20.

[0043] Please refer to Figure 5 This is a cross-sectional schematic diagram of a magnetic memory element according to another embodiment of the present invention. Figure 5 Magnetic memory elements and Figure 4 The same material layers of magnetic memory elements are identified by the same designation. For detailed descriptions of each material layer, please refer to the previous text, which will not be repeated here. Figure 5 Magnetic memory elements and Figure 4 The main difference between magnetic memory elements is that Figure 5 The magnetic memory element further includes a buffer layer 31 disposed between the dielectric capping layer 30 and the metal capping layer 32, and in direct contact with the bottom first metal layer 32a of the metal capping layer 32. The buffer layer 31 can buffer the stress on the magnetic tunneling junction 20 by the metal capping layer 32 and the hard mask layer 34 above it. The buffer layer 31 may include ferromagnetic materials, such as iron (Fe), cobalt (Co), nickel (Ni), iron-nickel (FeNi), iron-cobalt (FeCo), cobalt-nickel (CoNi), iron-boron (FeB), iron-platinum (FePt), iron-palladium (FePd), cobalt-iron-boron (CoFeB), or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, the buffer layer 31 may include cobalt-iron-boron (CoFeB).

[0044] In summary, the magnetic memory element of the present invention has a multilayer metal capping layer between the dielectric capping layer 30 and the hard mask layer 34 to prevent oxygen or elements of the hard mask layer 34 from diffusing into the magnetic tunneling junction stack 20, thereby reducing the problem of tunneling magnetoresistance offset.

[0045] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A magnetic memory element, comprising: Bottom electrode layer; A magnetic tunnel junction (MTJ) stack is disposed on the bottom electrode layer; A dielectric capping layer is disposed on the magnetic tunneling stack; as well as A metal capping layer is disposed on the dielectric capping layer, wherein the metal capping layer includes a plurality of alternating first metal layers and a plurality of second metal layers, wherein the plurality of first metal layers each include ruthenium (Ru), and the plurality of second metal layers each include a metal material that can react with the unoxidized first metal layer to form an alloy during a subsequent high-temperature step, wherein the metal material of the plurality of second metal layers each includes manganese (Mn) or zinc (Zn).

2. The magnetic memory element of claim 1, wherein the plurality of second metal layers are respectively sandwiched between two of the plurality of first metal layers.

3. The magnetic memory element of claim 1, wherein the dielectric cap layer is in direct contact with one of the plurality of first metal layers.

4. The magnetic memory element of claim 1, wherein the dielectric capping layer comprises magnesium oxide (MgO).

5. The magnetic memory element of claim 1, further comprising a hard mask layer disposed on the metal capping layer and in direct contact with one of the plurality of first metal layers.

6. The magnetic memory element of claim 5, wherein the hard mask layer comprises titanium nitride (TiN).

7. The magnetic memory element of claim 1, wherein the thickness of the first metal layer located at the top of the metal cap layer is greater than the thickness of the other first metal layers.

8. The magnetic memory element of claim 1, further comprising: A buffer layer is disposed between the dielectric capping layer and the metal capping layer, wherein the buffer layer is in direct contact with one of the plurality of first metal layers.

9. The magnetic memory element of claim 8, wherein the buffer layer comprises cobalt iron boron (CoFeB).

10. A method for manufacturing a magnetic memory element, comprising: A magnetic tunneling junction stack is formed on the bottom electrode layer; A dielectric capping layer is formed on the magnetic tunneling stack; as well as A metal capping layer is formed on the dielectric capping layer, wherein the metal capping layer comprises a plurality of alternating first metal layers and second metal layers, wherein the plurality of first metal layers each comprise ruthenium (Ru), and the plurality of second metal layers each comprise a metal material that can react with the unoxidized first metal layer during a subsequent high-temperature step to form an alloy, wherein the metal material of the plurality of second metal layers each comprises manganese (Mn) or zinc (Zn).

11. The method for manufacturing a magnetic memory element as claimed in claim 10, wherein the plurality of second metal layers are respectively sandwiched between two of the plurality of first metal layers.

12. The method of manufacturing a magnetic memory element as claimed in claim 10, wherein the dielectric cap layer is in direct contact with one of the plurality of first metal layers.

13. The method for manufacturing a magnetic memory element as claimed in claim 10, wherein the dielectric capping layer comprises magnesium oxide (MgO).

14. The method of fabricating a magnetic memory element as claimed in claim 10, further comprising forming a hard mask layer on the metal capping layer and in direct contact with one of the plurality of first metal layers.

15. The method of fabricating a magnetic memory element as claimed in claim 14, wherein the hard mask layer comprises titanium nitride (TiN).

16. The method of manufacturing a magnetic memory element as claimed in claim 10, wherein the thickness of the first metal layer located at the top of the metal cap layer is greater than the thickness of the other first metal layers.

17. The method for manufacturing a magnetic memory element as described in claim 10, further comprising: A buffer layer is formed on the dielectric capping layer; as well as The metal capping layer is formed on the buffer layer.

18. The method of manufacturing a magnetic memory element as claimed in claim 17, wherein the buffer layer comprises cobalt iron boron (CoFeB).

Images