In situ drift mitigation liner for column cell pcm

Abstract

A method for forming an in-situ drift mitigation liner on sidewalls of a phase change material (PCM) device stack, comprising: providing an intermediate device comprising a substrate comprising a bottom wiring portion, a bottom electrode metal layer, a drift mitigation liner layer, an active region layer, a carbon layer, a top electrode metal layer; patterning the top electrode metal layer to form a top electrode; performing a first intermediate angle ion beam etching (IBE) to etch the carbon layer and the active region layer formed on the drift mitigation liner to form a carbon portion and an active region portion of the PCM device stack; and performing a low angle IBE to etch the drift mitigation liner and to re-deposit material etched from the drift mitigation liner as a conductive liner material on sidewalls of the PCM device stack comprising exposed portions of the carbon portion, active region portion, and top electrode.

Description

Background Technology

[0001] This invention relates to semiconductor devices, and more particularly to a method for forming in-situ drift mitigation pads on the sidewalls of a phase change memory (PCM) device during ion beam etching.

[0002] Phase-change memory (PCM) is based on chalcogenide glass materials that, when a suitable current is applied, change their phase from crystalline to amorphous and then back again. GST alloy (germanium-antimony-tellurium or Ge2Sb2Te5) is one such chalcogenide glass material. Each phase has a different resistance level that remains stable until the phase is changed. The maximum and minimum resistance levels in a PCM device are based on binary 1 or 0 values.

[0003] During the electrical programming of a PCM device, at least some (or in some cases all) of the phase change materials undergo a phase change, which alters the resistance of the PCM device.

[0004] Phase change materials suffer from resistivity drift, particularly in amorphous phases, where the resistance increases with time according to a power law. For simulation applications where calculations require multiple states, mitigation of this resistivity drift is necessary.

[0005] One way to do this is by using conductive pads that can act as variable resistors in parallel to separate the write and read paths of a PCM cell. For PVD-based columnar cells, this involves depositing conductive pads around the GST filler. However, air exposure after RIE and oxidation of the GST are challenges. Summary of the Invention

[0006] According to an embodiment of the present invention, a method for forming an in-situ drift mitigation pad on the sidewall of a phase change material (PCM) device stack includes: providing an intermediate device comprising a substrate (including a bottom wiring portion), a bottom electrode metal layer, an active region layer, a carbon layer, a top electrode metal layer, a dielectric hard mask layer, an OPL, a silicon-based antireflective coating, and a patterning resist (201); and patterning the dielectric hard mask and the top electrode metal layer using the patterning resist to form a... Form the top electrode (202); perform a first intermediate angle ion beam etching (IBE) to etch the carbon layer and the active region layer formed on the drift mitigation pad to form the carbon portion and the active region portion of the PCM device stack (203); and perform a low angle IBE to etch the drift mitigation pad and redeposit the material etched from the drift mitigation pad as a conductive pad material on the sidewalls of the PCM device stack including the carbon portion, the active region portion and the exposed portion of the top electrode (204).

[0007] According to some embodiments, a phase-change memory (PCM) device includes: a substrate (101) including a bottom wiring portion (102); a PCM device stack (110) having sidewalls including a bottom electrode (103) disposed on the bottom wiring portion, a drift mitigation pad (104) disposed on the bottom electrode, an active region layer (105) disposed on the drift mitigation pad, a carbon layer (106) disposed on the active region layer, and a top electrode (107) disposed on the carbon layer; and a conductive pad material (108) forming a portion of the sidewalls of the PCM device stack on exposed portions of the carbon layer, the active region layer, and the top electrode.

[0008] As used herein, a “facilitating” action includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Therefore, by way of example and not limitation, instructions executing on one processor can facilitate or assist in performing an action by sending appropriate data or commands, thus facilitating an action performed by instructions executing on a remote processor. To avoid confusion, where the actor facilitates the action through actions other than performing the action, the action is still performed by an entity or combination of entities.

[0009] One or more embodiments of the present invention, or elements thereof, can be implemented in the form of a computer program product comprising a computer-readable storage medium having computer-usable program code for performing the indicated method steps. Furthermore, one or more embodiments of the present invention, or elements thereof, can be implemented in the form of a system (or apparatus) including a memory and at least one processor coupled to the memory and operable to perform the exemplary method steps. Further, in another aspect, one or more embodiments of the present invention, or elements thereof, can be implemented in the form of an apparatus for performing one or more of the method steps described herein; the apparatus may include (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or multiple such media) and implemented on a hardware processor, or (iii) a combination of (i) and (ii); any of (i)-(iii) implements the specific techniques set forth herein.

[0010] The technology of this invention can provide substantially beneficial technical effects. For example, one or more embodiments can provide:

[0011] A method for forming an in-situ drift mitigation pad on the sidewall of a PCM device;

[0012] A method for forming an in-situ drift mitigation pad on the sidewall of a PCM device to prevent air exposure after RIE; and

[0013] A method for forming an in-situ drift mitigation pad on the sidewall of a PCM device to prevent GST oxidation.

[0014] These and other features and advantages of the invention will become apparent from the following detailed description of exemplary embodiments of the invention, which is read in conjunction with the accompanying drawings. Attached Figure Description

[0015] Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings:

[0016] Figure 1 A PCM device according to at least one embodiment of the present invention is shown;

[0017] Figure 2 A method for forming an in-situ drift mitigation pad on the sidewall of a PCM device according to at least one embodiment of the present invention is shown; and

[0018] Figures 3-7 A method for forming an in-situ drift mitigation pad on the sidewall of a PCM device is shown according to at least one embodiment of the present invention. Detailed Implementation

[0019] Embodiments of the present invention relate to a method for forming in-situ drift mitigation pads on the sidewalls of a PCM device during ion beam etching (IBE).

[0020] According to at least one embodiment of the present invention, the PCM device 100 includes a substrate 101 (interlayer dielectric (ILD)) and a bottom wiring layer 102. A stack 110 disposed on the bottom wiring layer 102 includes a bottom electrode 103, a drift mitigation pad 104, a GST 105, a carbon layer 106, and a top electrode 107. Sidewall conductive pads 108 are disposed on the sidewalls of the stack 110. The sidewall conductive pads 108 have a thickness of about 2 to 10 nanometers (nm). The stack 110 and the sidewall conductive pads 108 are encapsulated in a SiN layer (encapsulation layer 109).

[0021] According to some embodiments, IBE is used to pattern the active region of the device GST. The PCM device is encapsulated in situ using a low-angle (relative to normal) IBE by redepositing a portion of the drift mitigation pad from below the GST onto the sidewall of the device. Optional surface treatments can then be applied to modify the microstructure or composition of this conductive pad (without oxidizing or altering the GST / pad interface).

[0022] Figure 2 A method 200 for forming an in-situ drift mitigation pad on the sidewall of a PCM device stack, according to at least one embodiment of the present invention, is shown. Figure 2The method includes: providing an intermediate device comprising, in sequence, a substrate (including a bottom wiring portion), a bottom electrode metal layer, a drift mitigation pad layer, an active area layer, a carbon layer, a top electrode metal layer, a dielectric hard mask layer, an OPL, a silicon-based antireflective coating, and a patterning resist (201); and patterning the dielectric hard mask and the top electrode metal layer using the patterning resist to form a top electrode (202). The method further includes performing an intermediate-angle (e.g., between approximately 40° and 60° relative to vertical) IBE etching of the carbon layer and GST layer formed on the drift mitigation pad (203). At block 204, a low-angle (e.g., between approximately 5° and 20° relative to vertical) IBE etching of the drift mitigation pad is performed, and the etched material (from the drift mitigation pad) is then deposited in situ as a conductive pad material onto the sidewalls of a PCM device stack. Here, the PCM device stack includes GST 105, a carbon layer 106, and a top electrode 107. At box 205, a second intermediate angle IBE is performed to etch the remaining portion of the drift-reducing pad and the bottom electrode material to complete the PCM device stack. At box 206, an in-situ surface treatment (e.g., plasma-based treatment and / or thermal annealing) is performed to alter the composition or microstructure of the conductive pad material on the sidewalls of the PCM device stack.

[0023] According to at least one embodiment, the IBE process performed at blocks 203 and 204 may include etching performed at more than one voltage. For example, the intermediate-angle IBE process 203 may include performing a first etching at a first relatively high voltage, followed by performing a second etching at a second relatively low voltage.

[0024] According to some embodiments, Figure 3 A device stack 300 is shown with layers deposited on a substrate 101 (interlayer dielectric (ILD)) and a bottom wiring layer 102. The device stack 300 includes a bottom electrode metal layer 301, a drift mitigation pad layer 302, a GST layer 303, a carbon layer 304, a top electrode metal layer 305, a dielectric hard mask 306, an organic planarization layer (OPL) 307, a silicon-containing antireflective coating (SiARC) layer 308, and a photoresist 309.

[0025] According to some embodiments, resist 309, SiARC 308 and OPL 307 are removed by reactive ion etching (RIE), which is a selective etching of these layers.

[0026] like Figure 4As shown, pattern transfer is performed from resist 309 to the dielectric hard mask 306 and the top electrode metal layer 305, stopping at the carbon layer 304. Therefore, the top electrode 107 is formed by the dielectric hard mask cap 401. According to some embodiments, pattern transfer may include a RIE based on halide chemicals.

[0027] like Figure 5 As shown, an intermediate angle (e.g., between approximately 40° and 60° relative to vertical) IBE (e.g., Ar (argon) or Ar / H2 (hydrogen) or Ar / N2 (nitrogen) chemistry) removes the unprotected portions of carbon layer 304 and GST film 303 from the dielectric hard mask cap 401. The remaining stack includes GST 105, carbon layer 106, top electrode 107, and dielectric hard mask cap 401.

[0028] like Figure 6 As shown, a low-angle (e.g., between approximately 5° and 20° relative to vertical) IBE (e.g., Ar or Ar / H2 or Ar / N2 chemicals) is performed to redeposit a portion of the drift mitigation pad layer 302 onto the sidewalls and form a conductive pad 108 on the stacked sidewalls. According to some embodiments, the low-angle IBE is configured to form a conductive pad 108 having a thickness of approximately 2-10 nm.

[0029] According to one or more embodiments, the conductive pad 108 is configured to contact the GST 105, the carbon layer 106, and the top electrode 107. According to some embodiments, the conductive pad 108 may be formed of a nitride, carbide, or oxide of titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), vanadium (V), or ruthenium (Ru). For example, the conductive pad 108 may be formed of, for example, titanium nitride (TiN), titanium carbide (TiC), tungsten carbide (WC), tungsten nitride (WN), carbon (C), hafnium nitride (HfN), hafnium carbide (HfC), vanadium nitride (VN), vanadium carbide (VC), tantalum nitride (TaN), tantalum carbide (TaC), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), other transitional carbides or nitrides, refractory metals, etc. According to some embodiments, the conductive pad 108 is made of carbon or a carbon-containing material (e.g., SiC).

[0030] like Figure 7 As shown, the second intermediate angle (between approximately 40° and 60°) IBE removes the residual drift mitigation pad layer 302 and patterns the bottom electrode metal layer 301 to form a completed stack 110 including the bottom electrode 103 and the drift mitigation pad 104.

[0031] According to some embodiments, optional surface treatments are performed on the conductive pad 108. The stoichiometry of the drift mitigation layer can be modified during the IBE redeposition process 204, for example, due to damage caused by the removal of N from TiN or WN or other metal nitride films by Ar-based plasmas. Thus, surface treatments (e.g., plasma nitriding or carburizing of metal carbides) can restore the stoichiometry of the drift mitigation layer. According to some embodiments, the surface treatment may include applying an H2-based plasma to remove oxygen from the conductive pad 108, followed by applying an N2 / NH3 plasma to incorporate nitrogen into the conductive pad 108. For example, an H2-based plasma can be used to reduce the oxide layer to a metallic form, which can then undergo nitriding or carburizing to adjust the stoichiometry and film properties.

[0032] According to some embodiments, one or more thermal annealing processes are performed in an H2 or H2 / N2 atmosphere.

[0033] According to some embodiments, the method further includes dielectrically encapsulating the stack with a SiN film 109 to obtain... Figure 1 The device shown.

[0034] According to some embodiments, the substrate 101 is formed of silicon nitride (SiN). According to at least one embodiment, the top electrode 103 and the bottom electrode 107 may be formed of, for example, TiN, W, WN, or TaN.

[0035] According to some embodiments, at blocks 203 and 204, another rare gas with a heavy atomic mass (e.g., xenon (Xe)) can be used to replace the Ar-based gas used for IBE.

[0036] Summary:

[0037] According to some embodiments, a method for forming an in-situ drift mitigation pad on the sidewall of a phase change material (PCM) device stack includes providing an intermediate device comprising a substrate (including a bottom wiring portion), a bottom electrode metal layer, a drift mitigation pad layer, an active region layer, a carbon layer, a top electrode metal layer, a dielectric hard mask layer, an OPL, a silicon-based antireflective coating, and a patterning resist (201); and using the patterning resist to pattern the dielectric hard mask and the top electrode metal layer to form a top electrode metal layer. The top electrode (202) is subjected to a first intermediate angle ion beam etching (IBE) to etch the carbon layer and the active region layer formed on the drift mitigation pad to form the carbon portion and the active region portion of the PCM device stack (203); and a low angle IBE is performed to etch the drift mitigation pad and to redeposit the material etched from the drift mitigation pad as a conductive pad material on the sidewall of the exposed portion of the PCM device stack including the carbon portion, the active region portion and the top electrode (204).

[0038] According to some embodiments, a phase-change memory (PCM) device includes: a substrate (101) including a bottom wiring portion (102); a PCM device stack (110) having sidewalls including a bottom electrode (103) disposed on the bottom wiring portion; a drift mitigation pad (104) disposed on the bottom electrode; an active region layer (105) disposed on the drift mitigation pad; a carbon layer (106) disposed on the active region layer; and a top electrode (107) disposed on the carbon layer; and a conductive pad material (108) forming a portion of the sidewalls of the PCM device stack on exposed portions of the carbon layer, the active region layer, and the top electrode.

[0039] References to this principle in the specification as "one embodiment" or "embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this principle. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0040] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should also be understood that when the terms “comprises” and / or “comprising” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0042] All means or steps in the following claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing the function in conjunction with other claimed elements as specifically claimed. Various embodiments of the invention have been described for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming an in-situ drift mitigation pad on the sidewall of a phase change material (PCM) device stack, comprising: An intermediate device is provided, the intermediate device comprising, in sequence: a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift mitigation pad layer, an active region layer, a carbon layer, a top electrode metal layer, a dielectric hard mask layer, an organic planarization layer (OPL), a silicon-based anti-reflective coating, and a patterned resist. The dielectric hard mask and the top electrode metal layer are patterned using the patterned resist to form the top electrode; Perform a first intermediate angle ion beam etching (IBE) to etch the carbon layer and the active region layer formed on the drift mitigation pad to form the carbon portion and active region portion of the PCM device stack; and A low-angle IBE is performed to etch the drift mitigation pad, and the material etched from the drift mitigation pad is redeposited as a conductive pad material on the sidewalls of the PCM device stack, which includes the carbon portion, the active region portion, and the exposed portion of the top electrode.

2. The method of claim 1, further comprising performing a second intermediate angle IBE, etching the remaining portion of the drift mitigation pad and the bottom electrode metal layer to form the bottom electrode and drift mitigation portion of the PCM device stack, wherein the bottom electrode is in electrical contact above the bottom wiring portion of the substrate.

3. The method of claim 1, further comprising performing a surface treatment on the conductive pad material on the sidewall of the PCM device stack.

4. The method according to claim 3, wherein, The surface treatment is a plasma-based process.

5. The method according to claim 3, wherein, The surface treatment is thermal annealing.

6. The method according to claim 3, wherein, The surface treatment removes oxygen from the conductive pad material.

7. The method according to claim 3, wherein, The surface treatment incorporates nitrogen into the conductive pad.

8. The method of claim 2, further comprising encapsulating the PCM device stack.

9. The method according to claim 8, wherein, The PCM device stack is encapsulated in a silicon nitride film.

10. The method according to claim 1, wherein, The PCM device stack is not exposed to air before the conductive pad material is deposited on the sidewalls of the PCM device stack.

11. The method according to claim 1, wherein, Before the conductive pad material is deposited on the sidewalls of the PCM device stack, the active region portion of the PCM device stack is not exposed to air.

12. A phase-change memory (PCM) device, comprising: Substrate, including the bottom wiring portion; PCM device stack, the PCM device stack having sidewalls, the PCM device stack comprising: The bottom electrode is disposed on the bottom wiring portion; Drift mitigation pads are disposed on the bottom electrode; An active region layer is disposed on the drift mitigation pad; A carbon layer is disposed on the active region layer; and Top electrode, disposed on the carbon layer; and Conductive pad material is applied to the exposed portions of the carbon layer, the active region layer, and the top electrode, forming part of the sidewalls of the PCM device stack. The conductive pad material is not formed on the sidewalls of the bottom electrode and the drift mitigation pad.

13. The PCM device of claim 12, further comprising a film encapsulating the PCM device stack.

14. The PCM device according to claim 13, wherein, The membrane is disposed on the exposed portion of the substrate.

15. The PCM device according to claim 12, wherein, The conductive pad material has a thickness between 2 nanometers and 10 nanometers.

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